PIC24FJ256GA705 Family Flash Programming Specificationww1.microchip.com/downloads/en/DeviceDoc/PIC24FJ256GA705... · 2018. 8. 15. · PIC24FJ256GA705 FAMILY DS30010102C-page 2 2015-2018

PIC24FJ256GA705 FAMILYPIC24FJ256GA705 Family

Flash Programming Specification

1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the PIC24FJ256GA705 family of 16-bit micro-controllers. This programming specification is requiredonly for those developing programming support for thefollowing devices:

Topics covered include:

• Section 1.0 “Device Overview”• Section 2.0 “Programming Overview”• Section 3.0 “Device Programming – ICSP”• Section 4.0 “Device Programming – Enhanced

ICSP”• Section 5.0 “Programming the Programming

Executive to Memory”• Section 6.0 “The Programming Executive”• Section 7.0 “Device ID” • Section 8.0 “Checksum Computation”• Section 9.0 “AC/DC Characteristics and

Timing Requirements”

• PIC24FJ256GA705 • PIC24FJ256GA702• PIC24FJ128GA705 • PIC24FJ128GA702• PIC24FJ64GA705 • PIC24FJ64GA702• PIC24FJ256GA704• PIC24FJ128GA704• PIC24FJ64GA704

2015-2018 Microchip Technology Inc. DS30010102C-page 1

PIC24FJ256GA705 FAMILY

2.0 PROGRAMMING OVERVIEWThere are two methods of programming that arediscussed in this programming specification:

• In-Circuit Serial Programming™ (ICSP™)• Enhanced In-Circuit Serial Programming

The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe device.

The Enhanced ICSP protocol uses a faster method thattakes advantage of the Programming Executive (PE), asillustrated in Figure 2-1. The PE provides all the neces-sary functionality to erase, program and verify the chipthrough a small command set. The command set allowsthe programmer to program a PIC24FJ256GA705 familydevice without dealing with the low-level programmingprotocols.

FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™

This programming specification is divided into twomajor sections that describe the programming methodsindependently. Section 3.0 “Device Programming –ICSP” describes the ICSP method. Section 4.0“Device Programming – Enhanced ICSP” describesthe Enhanced ICSP method.

2.1 Required ConnectionsThese devices require specific connections for program-ming to take place. These connections include power,VCAP, MCLR and one programming pair (PGEDx/PGECx). Table 2-1 describes these connections (referto the specific device data sheet for pin descriptions andpower connection requirements).

2.2 Power RequirementsAll PIC24FJ256GA705 family devices power their coredigital logic at a nominal 1.8V. To simplify systemdesign, all devices in the PIC24FJ256GA705 familyincorporate an on-chip regulator that allows the deviceto run its core logic from VDD.

The regulator provides power to the core from the otherVDD pins. A low-ESR capacitor (such as ceramic ortantalum) must be connected to the VCAP pin (seeTable 2-1 and Figure 2-2). This helps to maintain thestability of the regulator. The specifications for core volt-age and capacitance are listed in Section 9.0 “AC/DCCharacteristics and Timing Requirements”.

FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR

TABLE 2-1: PINS USED DURING PROGRAMMING

PIC24FJ256GA705

Programmer ProgrammingExecutive

On-Chip Memory

VDD

VCAP

VSS

PIC24FJ256GA705

CEFC

3.3V

(10 µF typ)

AVDD

AVSS

Pin Name Pin Type Pin Description

MCLR I Programming EnableVDD and AVDD(1) P Power Supply(1)

VSS and AVSS(1) P Ground(1)

VCAP P On-Chip Voltage Regulator Filter CapacitorPGECx I Programming Pin Pair: Serial Clock PGEDx I/O Programming Pin Pair: Serial Data Legend: I = Input O = Output P = PowerNote 1: All power supply and ground pins must be connected, including AVDD and AVSS.

DS30010102C-page 2 2015-2018 Microchip Technology Inc.


2.3 Pin DiagramsThe following figures show the pin diagrams for thePIC24FJ256GA705 families. The pins that are requiredfor programming are listed in Table 2-1 and are indi-cated in bold text in the figures. Refer to the appropriatedevice data sheet for complete pin descriptions.

2.3.1 PGECx AND PGEDx PIN PAIRSAll devices in the PIC24FJ256GA705 family have threeseparate pairs of programming pins, labeled asPGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3.Any one of these pin pairs may be used for deviceprogramming by either ICSP or Enhanced ICSP. Unlikevoltage supply and ground pins, it is not necessary toconnect all three pin pairs to program the device.However, the programming method must use both pinsof the same pair.

Pin Diagrams (28-Pin QFN)

Legend: Bold indicates pins used in device programming; the complete list of functions associated with programming/emulation pins is shown in the accompanying table.

Note 1: The PGEC2/PGED2 pin pair on 28-pin packages does not support Enhanced ICSP™, but does allow normal ICSP operation.

28-Pin QFN

MC

LRAV

DD

/VD

D

AVSS

/VSS

VSS

VDD

VSSVCAP

RB12PGED1/RB0PGEC1/RB1

RB2RB3

OSCI/RA2OSCO/RA3

RB4

RA4

PGED

3/R

B5PG

EC3/

RB6

RB7

RB8

RB9

PGED2/RB10(1)PGEC2/RB11(1)

RB13

RB

14R

B15

RA

0R

A1

10 11

2

3

6

1

18

19

12 13 14

15

8

7

16

17

232425262728

9

PIC24FJ256GA7025

4

20

21

22



Pin Diagrams (28-Pin PDIP)

28-Pin PDIP

MCLR

VSS

VDD

RA0RA1

AVDD/VDDAVSS/VSS

PGED1/RB0

PGEC3/RB6

RA4RB4

VSSOSCO/RA3OSCI/RA2 VCAP

RB7

RB9RB8

RB3RB2

PGEC1/RB1

1234567891011121314

2827262524232221201918171615

RB15RB14RB13RB12

PGED2/RB10(1)PGEC2/RB11(1)

PGED3/RB5

PIC

24FJ

256G

A70

2


Note 1: The PGEC2/PGED2 pin pair on 28-pin packages does not support Enhanced ICSP™, but does allow normal ICSP operation.



Pin Diagrams (44-Pin TQFP/QFN)

44-Pin TQFP/QFN

RB

8R

B7

PGEC

3/R

B6

PGED

3/R

B5

V DD

RA

9R

A4

VSS

RC

5R

C4

RC

3

RB12PGEC2/RB11PGED2/RB10

VCAPVSSRC9RC8RC7RC6RB9

RB13 RB2RB3RC0RC1RC2

RB4

VDDVSSOSCI/RA2OSCO/RA3RA8

PGEC

1/R

B1

PGED

1/R

B0

RA

1R

A0

MC

LR

RA

10

AVD

D

AVSS

RB

15R

B14

RA

7

1011

23456

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

37PIC24FJ256GA704




Pin Diagrams (48-Pin TQFP/QFN)

48-Pin TQFP/QFN

1011

23456

118 19 20 21 22 2313 14 15

38

87

44 43 42 41 40 39

16 17

29303132333435

25262728

47 4546

9

37

RA

14VD

D

VSS

RC

5R

C4

RB

6/PG

EC3

RB

5/PG

ED3

RC

3R

A9

RA

4

RB

7

PGEC2/RB11PGED2/RB10

RA11VCAP

VSSRC9RC8RC7RC6RB9

RB12

OSCO/RA3RA8

RB2RB3RC0

OSCI/RA2

RC1RC2VDDVSSRA13

RA

1R

A0

RA

12M

CLR

AVD

D

PGED

1/R

B0

AVss

RB

15R

B14

RA

7R

A10

12RB13

24PG

EC1/

RB

1

36 RB4

48R

B8

PIC24FJ256GA705




2.4 Program Memory Write/Erase Requirements

The program Flash memory has a specific write/eraserequirement that must be adhered to for proper deviceoperation. The rule is that any given word in memorymust not be written without first erasing the page inwhich it is located. Thus, the easiest way to conform tothis rule is to write all the data in a programming blockwithin one write cycle. The programming methodsspecified in this document comply with this requirement.

2.5 Memory MapThe program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide,it is more appropriate to think of each address of theprogram memory as a lower and upper word, with theupper byte of the upper word being unimplemented.

The lower word always has an even address, while theupper word has an odd address.

Program memory addresses are always word-aligned onthe lower word and addresses are incremented or decre-mented by two during code execution. This arrangementalso provides compatibility with data memory spaceaddressing and makes it possible to access data in theprogram memory space.

Locations, 0x80 0100 through 0x80 0FFE, are reservedfor executive code memory. This region stores theProgramming Executive (PE) and the debuggingexecutive, which is used for device programming. Thisregion of memory cannot be used to store user code.See Section 6.0 “The Programming Executive” formore information.

Locations, 0x80 1700 through 0x80 17FE, are reservedfor the customer data. This area can be used for storingproduct information, such as serial numbers, systemmanufacturing dates, manufacturing lot numbers andother application-specific information. It is described inSection 2.6.3 “Customer OTP Memory”.Locations, 0xFF 0000 and 0xFF 0002, are reserved forthe Device ID Word registers. These bits can be usedby the programmer to identify which device type isbeing programmed. They are described in Section 7.0“Device ID”. The Device ID registers read outnormally, even after code protection is applied.

Figure 2-3 shows the generic memory map for thedevices described in this specification. See the“Memory Organization” chapter in the specific devicedata sheet for exact memory addresses.

Table 2-2 lists the code memory size, the size of theerase blocks and the number of erase blocks presentin each device variant.

TABLE 2-2: PROGRAM MEMORY SIZES AND BOUNDARIES(2)

DeviceProgram Memory Upper Boundary

(Instruction Words)Write Blocks(1) Erase Blocks(1)

PIC24FJ256GA70X 0x02 AFFE (86K) 1376 172PIC24FJ128GA70X 0x01 5FFE (44K) 704 88PIC24FJ64GA70X 0x00 AFFE (22K) 352 44Note 1: 1 Write Block (Row) = 128 Instruction Words; 1 Erase Block (Page) = 1024 Instruction Words.

2: To maintain integer page sizes, the memory sizes are not exactly half of each other.



FIGURE 2-3: PROGRAM MEMORY MAP

0x00 0000

0xFA 00FE0xFA 0100

0xFE FFFE

0xFF FFFF

Con

figur

atio

n M

emor

y Sp

ace

Use

r Mem

ory

Spac

e

Legend: Memory areas are not shown to scale.Note 1: Exact boundary addresses are determined by the size of the implemented program memory. See Table 2-2

for details.

Flash Write Latches

DEVID (2)

Reserved

0xFF 0000

0xF9 FFFE0xFA 0000

0x80 00000x7F FFFF

Reserved

Configuration Words0x0X XX00(1)0x0X XXFE(1)

UnimplementedRead ‘0’

0xFF 0004Reserved

Reserved

0x80 0FFE0x80 0100

Customer OTP Memory 0x80 1700

Reserved 0x80 1000

0x80 16FE

0x80 1600

Executive Code Memory

UDID 0x80 1608

0x80 17FE0x80 1800

User Program Memory

Reserved



2.6 Configuration Bits2.6.1 OVERVIEWThese bits can be set or cleared to select various deviceconfigurations. There are two types of Configuration bits:system operation bits and code-protect bits. The systemoperation bits determine the power-on settings forsystem-level components, such as the oscillator and theWatchdog Timer. The code-protect bits prevent programmemory from being read and written.

Table 2-3 lists the Configuration register address rangefor each device. Table 2-4 lists all of the Configurationbits found in the PIC24FJ256GA705 family devices, aswell as their Configuration register locations. Refer tothe “Special Features” chapter in the specific devicedata sheet for the full Configuration register descriptionfor a specific device.

2.6.2 CODE-PROTECT CONFIGURATION BITS

The devices implement an intermediate security featuredefined by the FSEC register. The Boot Segment (BS) isthe higher privileged segment and the General Segment(GS) is the lower privileged segment. The total usercode memory can be split into BS or GS. The size of thesegments is determined by the BSLIM bits. Therelative location of the segments within user space doesnot change, such that BS (if present) occupies thememory area just after the Interrupt Vector Table (IVT),and the GS occupies the space just after the BS (or if theAlternate IVT is enabled, just after it).

The Configuration Segment (or CS) is a small segment(less than a page, typically just one row) within userFlash address space. It contains all user configurationdata that is loaded by the NVM controller during theReset sequence.

TABLE 2-3: CONFIGURATION WORD ADDRESSESConfiguration

Register PIC24FJ256GA70X PIC24FJ128GA70X PIC24FJ64GA70X

FSEC 0x02 AF00 0x01 5F00 0x00 AF00FBSLIM 0x02 AF10 0x01 5F10 0x00 AF10FSIGN 0x02 AF14 0x01 5F14 0x00 AF14FOSCSEL 0x02 AF18 0x01 5F18 0x00 AF18FOSC 0x02 AF1C 0x01 5F1C 0x00 AF1CFWDT 0x02 AF20 0x01 5F20 0x00 AF20FPOR 0x02 AF24 0x01 5F24 0x00 AF24FICD 0x02 AF28 0x01 5F28 0x00 AF28FDEVOPT1 0x02 AF2C 0x01 5F2C 0x00 AF2C



TA

BLE

2-4

:C

ON

FIG

UR

ATI

ON

REG

ISTE

R M

AP

Reg

iste

r N

ame

Bits

23

-16

Bit

15B

it 14

Bit

13B

it 12

Bit

11B

it 10

Bit

9B

it 8

Bit

7B

it 6

Bit

5B

it 4

Bit

3B

it 2

Bit

1B

it 0

FSE

C—

AIV

TDIS

——

—C

SS

C

WR

PG

SS

G

WR

P—

BS

S

BW

RP

FBS

LIM

——

——

BS

LIM

FS

IGN

—S

IGN

——

——

——

——

——

——

——

—FO

SC

SE

L—

——

——

——

PLL

96D

IV

IES

OP

LLM

OD

E

FNO

SC

FO

SC

——

——

——

——

—FC

KSM

IO

L1W

AYPL

LSS

SOSC

SEL

OSC

IOFN

CPO

SC

MD

FW

DT

——

WD

TCLK

S

—W

DTC

MX

—W

DTW

IN

WIN

DIS

FWD

TEN

W

DTP

RE

WD

TPS

FP

OR

——

——

——

——

——

——

—D

NV

PE

NR

ETV

RD

ISB

OR

EN

FI

CD

—N

OBT

SWP

——

——

——

—B

KB

UG

—JT

AG

EN

——

—IC

S

FDEV

OPT

1—

——

——

——

——

——

—D

OP

T<4:

1>—

Lege

nd:

— =

uni

mpl

emen

ted,

read

as

‘1’



2.6.3 CUSTOMER OTP MEMORYPIC24FJ256GA705 family devices provide 384 bytesof One-Time-Programmable (OTP) memory, located ataddresses, 0x80 1700 through 0x80 17FE. Thismemory can be used for persistent storage ofapplicationspecific information that will not be erasedby reprogramming the device. This includes manytypes of information, such as:

• Application checksums• Code revision information• Product information• Serial numbers• System manufacturing dates• Manufacturing lot numbers

Customer OTP memory may be programmed in anymode, including user RTSP mode, but it cannot beerased. Data is not cleared by a Chip Erase.

Note: The OTP memory resides within theECC controlled Flash memory region,but is exempt from erase operations.Therefore, the OTP must strictly bewritten to once. Writing multiple times tothe OTP region may cause a double-bitECC error, which will force a processorReset when the OTP region is read.There is no mechanism to remove theECC error if the OTP area has beenwritten more than once.



3.0 DEVICE PROGRAMMING – ICSPICSP mode is a special programming protocol thatallows you to read and write to device memory. TheICSP mode is the most direct method used to programthe device, which is accomplished by applying controlcodes and instructions serially to the device, using thePGECx and PGEDx pins. ICSP mode also has theability to read executive memory to determine if theProgramming Executive (PE) is present and to writethe PE to executive memory if Enhanced ICSP modewill be used.

In ICSP mode, the system clock is taken from thePGECx pin, regardless of the device’s Oscillator Con-figuration bits. All instructions are shifted serially into aninternal buffer, then loaded into the Instruction Register(IR) and executed. No program fetching occurs frominternal memory. Instructions are fed in 24 bits at atime. PGEDx is used to shift data in, and PGECx isused as both the serial shift clock and the CPUexecution clock.

3.1 Overview of the Programming Process

Figure 3-1 illustrates the high-level overview of theprogramming process. After entering ICSP mode, thefirst action is to Chip Erase program memory. Next, thecode memory is programmed, followed by the deviceConfiguration bits. Code memory (including the Config-uration bits) is then verified to ensure that programmingwas successful. Then, the code-protect Configurationbits are programmed, if required.

FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW

Note 1: During ICSP operation, the operatingfrequency of PGECx must not exceed5 MHz.

2: ICSP mode is slower than EnhancedICSP mode for programming.

Start

Perform ChipErase

Program Memory,

Verify Program Memory,

End

Enter ICSP™

Program Code-Protect

Exit ICSP

Configuration Wordsand User ID Words


Configuration Bits



3.2 Entering ICSP ModeAs shown in Figure 3-2, entering ICSP Program/Verifymode requires three steps:

1. MCLR is briefly driven high, then low (P21).2. A 32-bit key sequence is clocked into PGEDx.

The interval of at least P18 must elapse beforepresenting the key sequence on PGEDx.

3. MCLR is held low during a specified period, P19,and then driven high.

4. After a P7 + 5 * P1 delay, five clock pulses mustbe generated on the PGECx pin.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 0x4D43 4851 inhexadecimal). The device will enter ICSP mode only ifthe sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.

On successful entry, the program memory can beaccessed and programmed in serial fashion.

FIGURE 3-2: ENTERING ICSP™ MODE

Note: If a capacitor is present on the MCLR pin, thehigh time for entering ICSP mode can vary.

MCLR

PGEDx

PGECx

VDD

P6

P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 0x4D43 4851

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 1

P7VDD VDD

P21P1 * 5

1 2 3 4 5



3.3 ICSP OperationAfter entering into ICSP mode, the CPU is Idle.Execution of the CPU is governed by an internal statemachine. A 4-bit control code is clocked in usingPGECx and PGEDx, and this control code is used tocommand the CPU (see Table 3-1).

The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device through the VISIregister.

TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE

3.3.1 SIX SERIAL INSTRUCTION EXECUTION

The SIX control code allows execution of assemblyinstructions. When the SIX code is received, the CPU issuspended for 24 clock cycles as the instruction is thenclocked into the internal buffer. Once the instruction isshifted in, the state machine allows it to be executed overthe next four clock cycles. While the received instructionis executed, the state machine simultaneously shifts inthe next 4-bit command (see Figure 3-3).

FIGURE 3-3: SIX SERIAL EXECUTION

4-Bit Control Code Mnemonic Description

0000 SIX Shift in 24-bit instruction and execute.

0001 REGOUT Shift out the VISIregister.

0010-1111 N/A Reserved.

Note 1: The device will latch input PGEDx dataon the rising edge of PGECx. For all datatransmissions, the Least Significant bit(LSb) is transmitted first.

2: TBLRDH, TBLRDL, TBLWTH and TBLWTLinstructions must be followed by two NOPinstructions.

3: During ISCP programming, the CLKO pinwill toggle. If external logic is connected toCLKO, be sure that this toggling will noteffect the circuitry during the programmingsequence.

P4

1 2 3 23 24 1 2 3 4P1

PGECxP4A

PGEDx

24-Bit Instruction Fetch Execute 24-Bit Instruction,Execute PC – 1,Fetch SIX Control Code Fetch Next Control Code

4 5 6 7 8 18 19 20 21 2217

LSB X X X X X X X X X X X X X X MSB

PGEDx = Input

P2

P3P1B

P1A

1 2

0 0 0 00 0

3 4

0 0



3.3.2 REGOUT SERIAL INSTRUCTION EXECUTION

The REGOUT control code allows for data to beextracted from the device in ICSP mode. It is used toclock the contents of the VISI register out of the deviceover the PGEDx pin. After the REGOUT control code isreceived, the CPU is held Idle for eight cycles. Afterthese eight cycles, an additional 16 cycles are requiredto clock the data out (see Figure 3-4).

The REGOUT code is unique because the PGEDx pin isan input when the control code is transmitted to thedevice. However, after the control code is processed,the PGEDx pin becomes an output as the VISI registeris shifted out.

FIGURE 3-4: REGOUT SERIAL EXECUTION

Note: The device will output data on the PGEDxline on the rising edge of PGECx. For alldata transmissions, the Least Significantbit (LSb) is transmitted first.

1 2 3 4 1 2 7 8PGECx

P4

PGEDx

PGEDx = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register

P5

PGEDx = Output

1 2 3 1 2 3 4

P4A

11 13 15 161412

No Execution Takes Place,Fetch Next Control Code

0 0 0 0 0

PGEDx = Input

MSb1 2 3 41

4 5 6

LSb 141312... 11100

Fetch REGOUT Control Code

0



3.4 Flash Memory Programming in ICSP Mode

3.4.1 PROGRAMMING OPERATIONSFlash memory write/erase operations are controlled bythe NVMCON register. Programming is performed bysetting NVMCON to select the type of erase operation(Table 3-2) or write operation (Table 3-3) and initiatingthe programming by setting the WR control bit(NVMCON).

In ICSP mode, all programming operations areself-timed. The WR control bit is cleared by hardwarewhen the programming operation is complete. TheICSP programmer must supply enough clock pulses onthe PGECx pin to complete the erase or program oper-ation. Refer to Section 9.0 “AC/DC Characteristicsand Timing Requirements” for detailed informationabout the maximum number of clock pulses requiredfor erase or write operations.

TABLE 3-2: NVMCON ERASE OPERATIONS

TABLE 3-3: NVMCON WRITE OPERATIONS

3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE

For protection against accidental operations, the erase/write initiate sequence must be written to the NVMKEYregister to allow any erase or program operation toproceed. The three instructions following the start ofthe programming sequence should be NOPs. To start anerase or write sequence, the following steps must becompleted:

1. Write 0x55 to the NVMKEY register.2. Write 0xAA to the NVMKEY register.3. Set the WR bit in the NVMCON register.4. Execute three NOP instructions.

All erase and write cycles are self-timed. The WR bitcan be polled to supply enough PGECx clock pulses forthe operation and determine if the erase or write cyclehas been completed.

NVMCONValue Erase Operation

0x400E Chip Erase (erases user memory; does not erase executive memory, Device ID or customer OTP).

0x4003 Erase a page of program or executive memory.

NVMCONValue Write Operation

0x4001 Double-word program operation.0x4002 Row programming operation.



3.5 Erasing Program MemoryThe general procedure for erasing user memory isshown in Figure 3-5. The process for Chip Erase andPage Erase are all similar, and are described inTable 3-4 through Table 3-5.

The last row of the last page of program memorycontains the Configuration Words. Before programmingthese Words, they must be erased. If they are erasedwith a Page Erase operation, all other rows in the pagewill also be erased. Users may want to either avoidusing the rest of this page for application code or ensurethat the non-configuration data in the CS page is copiedbefore the erase and reprogrammed afterwards.

FIGURE 3-5: ERASE FLOW

TABLE 3-4: SERIAL EXECUTION FOR CHIP ERASE

Note 1: Program memory must be erased beforewriting any data to program memory.

2: For Page Erase operations, theNVMADR/NVMADRU registers mustalso be loaded with the address of thepage to be erased.

Start

End

Set the WR Bit to Initiate Erase

Write Appropriate Value to NVMCON

Poll WR Bit to Supply Enough Clock Pulsesand Determine when Erase Cycle

is Completed

Command (Binary)

Data (Hex) Description

Step 1: Exit the Reset vector.000000000000

000000040200000000

NOPGOTO 0x200NOP

Step 2: Configure the NVMCON register to perform a Chip Erase.00000000

2400E0883B00

MOV #0x400E, W0MOV W0, NVMCON

Step 3: Set the WR bit.00000000000000000000000000000000

200550883B30200AA0883B30A8E761000000000000000000

MOV #0x55, W0MOV W0, NVMKEYMOV #0xAA, W0MOV W0, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 4: Repeat this step to poll the WR bit until it is cleared by hardware.00000000000000000000000000010000

040200000000803B02000000883C22000000

000000

GOTO 0x200NOPMOV NVMCON, W2NOPMOV W2, VISINOP; Clock out the contents of the VISI register.NOP

Step 5: Clear the WREN bit.00000000

200000883B00

MOV #0000, W0MOV W0, NVMCON



TABLE 3-5: SERIAL EXECUTION FOR PAGE ERASECommand (Binary)

Data (Hex) Description


000000 040200 000000

NOPGOTO 0x200NOP

Step 2: Set the NVMCON register to erase a page.00000000

240030 883B00

MOV #0x4003, W0MOV W0, NVMCON

Step 3: Load the address of the page to be erased into the NVMADR register pair.0000000000000000

200000 883B10 200000 883B20

MOV #PAGE_ADDR_LO, W0MOV W0, NVMADRMOV #PAGE_ADDR_HI, W0MOV W0, NVMADRU


200550 883B30 200AA0 883B30 A8E761 000000 000000 000000



040200 000000 803B02 000000883C22 000000

000000

GOTO 0x200NOPMOV NVMCON, W2NOPMOV W2, VISINOP; Clock out the contents of the VISI register.NOP

Step 6: Clear the WREN bit.00000000

200000 883B00




3.6 Writing Code MemoryFor PIC24FJ256GA705 devices, code memory is writtenin three steps:

• Writing the data to memory-mapped write latches (located in the configuration memory space at addresses, 0xFA 0000 through 0xFA 00FE);

• Setting a destination address; and• Initiating the memory write sequence

There are two methods available for writing to codememory: double-word writes using the write latches or128-word row writes. Figure 3-7 provides a high-leveldescription of the two methods.

Double-word writes program code memory with twoinstruction words at a time. Two words are loaded intothe write latches. Next, the write sequence is initiated,and finally, the WR bit is checked for the sequence tobe complete. This process continues for all the data tobe programmed.

Table 3-6 provides an example of ICSP programmingfor a double-word write operation.

The data loaded into the programming latches must bein the packed format, as shown in Figure 3-6.

FIGURE 3-6: PACKED INSTRUCTION WORD FORMAT

Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 cannot be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word



FIGURE 3-7: PROGRAM CODE MEMORY FLOW

Start

Configure Devicefor Writes

All Data Written?

No

Yes

Initiate WriteSequence and Poll

WR Bit to be Cleared

Initialize Write Pointerwith Row Address

(DestinationAddress)

Load Two Words intoWrite Latches

IncrementWrite Pointer

End

No

Using RAM RowProgramming

Using Two-WordProgramming

Load 128 Wordsinto Write Latches



TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:TWO-WORD LATCH WRITES

Command(Binary)

Data(Hex) Description


000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize the TBLPAG register for writing to the latches.00000000

200FAC8802AC

MOV #0xFA, W12MOV W12, TBLPAG

Step 3: Load W0:W2 with the next two packed instruction words to program.000000000000

2xxxx02xxxx12xxxx2

MOV #, W0MOV #, W1MOV #, W2

Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.0000000000000000000000000000000000000000000000000000000000000000

EB0300000000EB0380000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000

CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL.W [W6++], [W7++]NOP NOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address.0000000000000000

2xxxx32xxxx4883B13883B24

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 6: Set the NVMCON register to program two instruction words.000000000000

24001A883B0A000000

MOV #0x4001, W10MOV W10, NVMCONNOP

Step 7: Initiate the write cycle.00000000000000000000000000000000

200551883B31200AA1883B31A8E761000000000000000000




Step 8: Wait for program operation to complete and make sure the WR bit is clear.0000000000000001000000000000

—

803B00883C20000000

000000040200000000

—

MOV NVMCON, W0MOV W0, VISINOP; Clock out the contents of the VISI register.NOPGOTO 0x200NOP; Repeat until the WR bit is clear.

Step 9: Repeat Steps 3-8 until all code memory is programmed.Step 10: Clear the WREN bit.

00000000

200000 883B00


TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:TWO-WORD LATCH WRITES (CONTINUED)

Command(Binary)




Row writes program one row (128 instruction words) ata time. First, the Table Pointer is initialized to point tothe program latches and data is written into them withTable Writes. Next, the Write Pointer is initialized(NVMADRU and NVMADR register pair) with the rowaddress (DestinationAddress). Finally, the writesequence is initiated and the WR bit is checked for therow programming to be complete. This process isrepeated for all data to be programmed. Table 3-7shows the ICSP programming details for row writes.

To minimize programming time, the data to be pro-grammed is stored in the W0:W5 registers in a packeddata format (Figure 3-8). This is the same packedformat used by the PE. See Section 6.2.2 “PackedData Format” for additional information.

FIGURE 3-8: PACKED INSTRUCTION WORD STORAGE IN W0:W5

MSB0MSB1

LSW1

LSW0

0715

MSB2MSB3

LSW3

LSW2

W0

W1

W2

W3

W4

W5

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY: ROW WRITES

Command(Binary)



000000040200000000

NOPGOTO 0x200NOP

Step 2: Set the NVMCON register to program 128 instruction words.00000000

240020883B00

MOV #0X4002, W0MOV W0, NVMCON


200FAC8802AC


Step 4: Load W0:W5 with the next four instruction words to program.000000000000000000000000

2xxxx02xxxx12xxxx22xxxx32xxxx42xxxx5

MOV #, W0MOV #, W1MOV #, W2MOV #, W3MOV #, W4MOV #, W5

Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.0000000000000000000000000000

EB0300000000EB0380000000BB0BB6000000000000

CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7]NOPNOP



Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. (Continued)000000000000000000000000000000000000000000000000000000000000000000000000000000000000

BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000

TBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOP

Step 6: Repeat Steps 4 and 5, for a total of 32 times, to load the write latches with 128 instructions.Step 7: Set the NVMADRU/NVMADR register pair to point to the correct address.

0000000000000000



Step 8: Execute the WR bit unlock sequence and initiate the write cycle.00000000000000000000000000000000

200550883B30200AA0883B30A8E761000000000000000000



040200 000000 803B02 883C22 000000

000000

GOTO 0x200NOPMOV NVMCON, W2MOV W2, VISINOP; Clock out the contents of the VISI register.NOP

Step 10: Reset the device’s internal Program Counter (PC).00000000

040200000000

GOTO 0x200NOP

Step 11: Repeat Steps 3 through 9 until all code memory is programmed.Step 12: Clear the WREN bit.

00000000

200000 883B00


TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY: ROW WRITES (CONTINUED)

Command(Binary)




3.7 Writing Configuration BitsThe procedure for writing Configuration bits is similar tothe procedure for writing code memory. Table 3-8shows the ICSP programming details for writing theConfiguration bits.

To change the values of the Configuration bits once theyhave been programmed, the device must be erased, asdescribed in Section 3.5 “Erasing Program Memory”,and reprogrammed to the desired value. Note that it isonly possible to program a Configuration bit from ‘1’ to‘0’ to enable code protection; it is not possible toprogram it from ‘0’ to ‘1’.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CONFIGURATION WORDS:TWO-WORD LATCH WRITES

Command(Binary)



000000040200000000

NOPGOTO 0x200NOP


200FAC8802AC


Step 3: Load W0:W1 with the next two Configuration Words to program.00000000—

0000

2xxxx02FFxx1

—2FFFF2

MOV #, W0MOV #, W1; Upper word is 0xFFFF for all Configuration Words except FBTSEQMOV #0xFFFF, W2

Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.0000000000000000000000000000000000000000000000000000000000000000


CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL.W [W6++], [W7++] NOPNOP







24001A883B0A000000

MOV #0x4001, W10MOV W10, NVMCONNOP


200551883B31200AA1883B31A8E761000000000000000000



—

803B00883C20000000

000000040200000000

—

MOV NVMCON, W0MOV W0, VISINOP; Clock out the contents of the VISI register.NOPGOTO 0x200NOP; Repeat until the WR bit is clear.


00000000

200000 883B00


TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CONFIGURATION WORDS:TWO-WORD LATCH WRITES (CONTINUED)

Command(Binary)




3.8 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.

Table 3-9 shows the ICSP programming details forreading code memory.

To minimize reading time, the same packed data formatthat the PE uses is utilized. See Section 6.2 “Pro-gramming Executive Commands” for more detailson the packed data format.

3.9 Reading Configuration WordsThe procedure for reading Configuration Words is iden-tical to the procedure for reading code memory, shownin Table 3-9. Since there are multiple ConfigurationWords, they are read one at a time.

TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand

(Binary)Data(Hex) Description


000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize the Write Pointer (W7) to point to the VISI register.00000000

207847000000

MOV #VISI, W7NOP

Step 3: Initialize the TBLPAG register and the Read Pointer (W6) for a TBLRD instruction.000000000000

200xx08802A02xxxx6

MOV #, W0MOV W0, TBLPAGMOV #, W6

Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command.

000000000000000100000000000000000000000000000001000000000000000000010000

BA0B96000000000000

000000BADBB6000000000000BAD3D6000000000000

000000BA0BB6000000000000

000000

TBLRDL [W6], [W7]NOPNOP; Clock out the contents of the VISI register.NOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7--]NOPNOP; Clock out the contents of the VISI register.NOPTBLRDL [W6++], [W7]NOPNOP; Clock out the contents of the VISI register.NOP

Step 5: Reset the device’s internal Program Counter.00000000

040200000000

GOTO 0x200NOP

Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset the device’s internal Program Counter” will be Step 5).



3.10 Verify Code Memory and Configuration Bits

The verify step involves reading back the code memoryspace and comparing it against the copy held in theprogrammer’s buffer. The Configuration Words areverified with the rest of the code.

The verify process is illustrated in Figure 3-9. The lowerword of the instruction is read, and then the lower byteof the upper word is read and compared against theinstruction stored in the programmer’s buffer. Referto Section 3.8 “Reading Code Memory” forimplementation details of reading code memory.

FIGURE 3-9: VERIFY CODE MEMORY FLOW

3.11 Exiting ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as illustrated in Figure 3-10. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and program signals onPGECx and PGEDx, before removing VIH.

FIGURE 3-10: EXITING ICSP™ MODE

Note: Because the Configuration bytes includethe device code protection bit, codememory should be verified immediatelyafter writing if the code protection is to beenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bithas been cleared.

Read Low Word

Read High Byte

Data?

AllCode Memory

Verified?

No

Yes

No

Set Table Pointer to 0

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

DoesInstruction Word

= Expected

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VIH

VIH

P17



4.0 DEVICE PROGRAMMING – ENHANCED ICSP

This section discusses programming the devicethrough Enhanced ICSP and the ProgrammingExecutive (PE). The PE resides in executive memory(separate from code memory) and is executed whenEnhanced ICSP Programming mode is entered. ThePE provides the mechanism for the programmer (hostdevice) to program and verify the PIC24FJ256GA705family devices, using a simple command set andcommunication protocol. There are several basicfunctions provided by the PE:

• Read Memory• Erase Memory• Program Memory• Blank Check

The PE performs the low-level tasks required forerasing, programming and verifying a device. Thisallows the programmer to program the device byissuing the appropriate commands and data. A detaileddescription for each command is provided inSection 6.2 “Programming Executive Commands”.

4.1 Overview of the Programming Process

Figure 4-1 shows the high-level overview of theprogramming process. First, it must be determined if thePE is present in executive memory, and then, EnhancedICSP mode is entered. The program memory is thenerased, and the program memory and ConfigurationWords are programmed and verified. Last, thecode-protect Configuration bits are programmed (ifrequired) and Enhanced ICSP mode is exited.

FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW

Note: The PE uses the device’s data RAM forvariable storage and program execution.After running the PE, no assumptionsshould be made about the contents ofdata RAM.

Start

End

Program Memory,

Verify Program Memory,

Erase

Program Code-Protect

Exit Enhanced ICSP

Enter Enhanced

Configuration Words

Configuration Bits

ICSP™ Mode

Program Memory


and User ID Words

Confirm Presence ofProgramming Executive



4.2 Confirming the Presence of the Programming Executive

Before programming, the programmer must confirmthat the PE is stored in executive memory. Theprocedure for this task is illustrated in Figure 4-2.

First, ICSP mode is entered. Then, the unique Applica-tion ID Word, stored in executive memory, is read. If theApplication ID has the value, 0xE0, the ProgrammingExecutive is resident in memory and the device can beprogrammed. However, if the Application ID Word is notpresent, the PE must be programmed to executive codememory using the method described in Section 5.0“Programming the Programming Executive toMemory”. Section 3.0 “Device Programming – ICSP”describes the ICSP programming method. Section 4.3“Reading the Application ID Word” describes theprocedure for reading the Application ID Word in ICSPmode.

FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE

Is

Start

Enter ICSP™ Mode

Content = 0xE0?

Yes

No

Application IDCheck the

be ProgrammedProg. Executive must

by Reading Address0x80 0FF0

End

Exit ICSP Mode

Enter Enhanced

Sanity Check

ICSP Mode



4.3 Reading the Application ID WordThe Application ID Word is stored at address,0x80 0FF0, in executive code memory. To read thismemory location, you must use the SIX control code tomove this program memory location to the VISI regis-ter. Then, the REGOUT control code must be used toclock the contents of the VISI register out of the device.The corresponding control and instruction codes thatmust be serially transmitted to the device to performthis operation are shown in Table 4-1.

If the Application ID has the value, 0xE0, theProgramming Executive is resident in memory and thedevice can be programmed using the mechanismdescribed in this section. However, if the ApplicationID has any other value, the PE is not resident inmemory; it must be loaded to memory before thedevice can be programmed. The procedure for loadingthe PE to memory is described in Section 5.0“Programming the Programming Executive toMemory”.

TABLE 4-1: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORDCommand



000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize TBLPAG and the Read Pointer (W0) for the TBLRD instruction.000000000000000000000000000000000000

2008008802A020FF00207841000000BA0890000000000000000000

MOV #0x80, W0 MOV W0, TBLPAGMOV #0xFF0, W0 MOV #VISI, W1 NOP TBLRDL [W0], [W1] NOPNOPNOP

Step 3: Output the VISI register using the REGOUT command.0001 ; Clock out the contents of the VISI register.



4.4 Entering Enhanced ICSP ModeAs illustrated in Figure 4-3, entering Enhanced ICSPProgram/Verify mode requires three steps:

1. The MCLR pin is briefly driven high and thenlow.

2. A 32-bit key sequence is clocked into PGEDx.3. MCLR is then driven high within a specified

period of time and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in PIC24FJ256GA705 familydevices. There is no minimum time requirement forholding at VIH. After VIH is removed, an interval of atleast P18 must elapse before presenting the keysequence on PGEDx.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 0x4D43 4850 in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MostSignificant bit (MSb) of the most significant nibble mustbe shifted in first.

Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An intervaltime of at least P19, P7 and P1 * 5 must elapse beforepresenting data on PGEDx. During the P7 interval, theprogrammer’s PGEDx and PGECx lines must betri-stated.

On successful entry, the program memory can beaccessed and programmed in serial fashion. While inthe Program/Verify mode, all unused I/Os are placed inthe high-impedance state.

4.5 Blank CheckThe term, “Blank Check”, implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’.

The Device ID registers (0xFF 0000:0xFF 0002) can beignored by the Blank Check, since this region storesdevice information that cannot be erased. Additionally,all unimplemented memory space should be ignored bythe Blank Check.

The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.

FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE

Note: The PGEC2/PGED2 pair on 28-pinpackages does not support EnhancedICSP, but does allow normal ICSPoperation.

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434850h

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 0

P7VIH VIH

P21 P1 * 5

PGEDx/PGECx must bein a High-Impedance State

during P7 Interval

X

X



4.6 Code Memory Programming

4.6.1 PROGRAMMING METHODOLOGYThere are two commands that can be used forprogramming code memory when utilizing the PE. ThePROG2W command programs and verifies two 24-bitinstruction words into the program memory, starting at theaddress specified. The second and faster command,PROGP, allows up to 128 instruction words (each 24 bits)to be programmed and verified into program memory,starting at the address specified. See Section 6.0 “TheProgramming Executive” for a full description for eachof these commands.

Figure 4-4 and Figure 4-5 show the programmingmethodology for the PROG2W and PROGP commands. Inboth instances, 87552 instruction words of the deviceare programmed.

FIGURE 4-4: FLOWCHART FOR DOUBLE-WORD PROGRAMMING

FIGURE 4-5: FLOWCHART FOR MULTIPLE WORD PROGRAMMING

Note: If a bootloader needs to be programmed, itscode must not be programmed into the firstpage of code memory. For example, if a boot-loader, located at address, 0x200, attemptsto erase the first page, it would inadvertentlyerase itself. Instead, program the bootloaderinto the second page (e.g., 0x400).

BaseAddress = 0x0RemainingCmds = 43776

Start

FailureReport ErrorEnd

Yes

No

RemainingCmds =RemainingCmds – 1

Yes

PASS?

No

BaseAddressCommand to Program

Send PROG2W

RemainingCmdsIs

‘0’?

BaseAddress + 0x04BaseAddress =

PROG2W ResponseIs

BaseAddress = 0x0RemainingCmds = 684

Start

FailureReport ErrorEnd

Yes

No

RemainingCmds =RemainingCmds – 1

Yes

PASS?

No

BaseAddressCommand to Program

Send PROGP

RemainingCmdsIs

‘0’?

BaseAddress + 0x100BaseAddress =

PROGP ResponseIs



4.7 Configuration Bit ProgrammingConfiguration bits are programmed one at a time usingthe PROG2W command. This command specifies theconfiguration data and address. When Configurationbits are programmed, any unimplemented bits must beprogrammed with a ‘1’.

Multiple PROG2W commands are required to programall Configuration bits. A flowchart for Configuration bitprogramming is shown in Figure 4-6.

FIGURE 4-6: CONFIGURATION BIT PROGRAMMING FLOW

4.8 Programming VerificationAfter code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared against the copy held inthe programmer’s buffer.

The READP command can be used to read back all theprogrammed code memory and Configuration Words.

Alternatively, you can have the programmer performthe verification after the entire device is programmedusing a checksum computation.

See Section 8.0 “Checksum Computation” for moreinformation on calculating the checksum.

4.9 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VIHfrom MCLR, as illustrated in Figure 4-7. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and program signals onPGECx and PGEDx, before removing VIH.

FIGURE 4-7: EXITING ENHANCED ICSP™ MODE

Send PROG2WCommand

IsPROG2W Response

PASS?

No

Yes

No

FailureReport Error

Start

End

Yes

LastConfiguration

Byte?

ConfigAddress =ConfigAddress +

0x04

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VIH

VIH

P17



5.0 PROGRAMMING THE PROGRAMMING EXECUTIVETO MEMORY

5.1 OverviewIf it is determined that the PE is not present in executivememory (as described in Section 4.2 “Confirming thePresence of the Programming Executive”), the PEmust be programmed to executive memory.

Figure 5-1 shows the high-level process of program-ming the PE into executive memory. First, ICSP modemust be entered, and executive memory and usermemory are erased; then, the PE is programmed andverified. Finally, ICSP mode is exited.

FIGURE 5-1: HIGH-LEVEL PROGRAMMING EXECUTIVE PROGRAM FLOW

5.2 Erasing Executive MemoryExecutive memory can be erased through a series ofPage Erase operations, as shown in Figure 5-2. Thisconsists of setting NVMCON to 0x4003, executing theprogramming cycle and repeating for the rest of thepages of executive memory.

Table 5-1 illustrates the ICSP programming process forBulk Erasing memory.

FIGURE 5-2: BULK ERASE FLOW

Note: The Programming Executive (PE) can beobtained from each device page on theMicrochip website: www.microchip.com.

Start

End

Read/Verify the

Program the

Enter ICSP™ Mode

Erase

Programming Executive

Programming Executive

Memory

Exit ICSP Mode

Note: The PE must always be erasedbefore it is programmed, as describedin Figure 5-1.

Start

i = 4Address = 0x80 0000

Write 0x4003

Set WR Bit

Delay P11 + P10

i = 0?

i = i – 1

N

End

Y

Address =

to NVMCON

to Initiate EraseAddress + 1024



TABLE 5-1: SERIAL INSTRUCTION EXECUTION FOR ERASING EXECUTIVE MEMORYCommand

(Binary)Data

(Hex) Description


000000040200000000000000

NOPGOTO 0x200NOPNOP

Step 2: Set the NVMCON register to erase a page.00000000

240030883B00

MOV #0x4003, W0MOV W0, NVMCON

Step 3: Load the address of the page to be erased into the NVMADR register pair.0000000000000000

200004883B14200800883B20

MOV #0000, W4MOV W4, NVMADRMOV #0080, W0MOV W0, NVMADRU


200550883B30200AA0883B30A8E761000000000000000000



040200000000803B02883C22000000

000000


Step 6: Increment W4 by 1024 (0x400).000000000000

204003418204883B14

MOV #400, W3ADD W3, W4, W4MOV W4, NVMADR

Step 7: Repeat Steps 4-6 until the entire test memory has been erased.Step 8: Clear the WREN bit.

00000000

200000 883B00




5.3 Program the Programming Executive

Storing the PE to executive memory is similar to normalprogramming of code memory. The executive memorymust first be erased and then programmed, usingeither two-word writes (two instruction words) or rowwrites (128 instruction words). The control flow for bothmethods is identical to that for programming codememory, as shown in Figure 3-7.

Table 5-2 and Table 5-3 illustrate the ICSP programmingprocesses for PE memory. To minimize programmingtime, the same packed data format that the PE uses isutilized. See Section 6.2 “Programming ExecutiveCommands” for more details on the packed dataformat.

TABLE 5-2: PROGRAMMING THE PROGRAMMING EXECUTIVE (TWO-WORD LATCH WRITES)

Command(Binary)



000000040200000000

NOPGOTO 0x200NOP


200FAC8802AC


Step 3: Load W0:W2 with the next two packed instruction words to program.000000000000

2xxxx02xxxx12xxxx2

MOV #, W0MOV #, W1MOV #, W2

Step 4: Set the Read Pointer (W6) and the Write Pointer (W7), and load the write latches.0000000000000000000000000000000000000000000000000000000000000000


CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B [W6++], [W7++] NOPNOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL.W [W6++], [W7++] NOPNOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct row.0000000000000000




24001A000000883B0A000000000000

MOV #0x4001, W10NOPMOV W10, NVMCONNOPNOP




200551883B31200AA1883B31A8E761000000000000000000



—

000000803B00000000883C20000000

000000040200000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOP; Clock out the contents of the VISI register.NOPGOTO 0x200NOP; Repeat until the WR bit is clear.


00000000

200000 883B00


TABLE 5-2: PROGRAMMING THE PROGRAMMING EXECUTIVE (TWO-WORD LATCH WRITES) (CONTINUED)

Command(Binary)




TABLE 5-3: PROGRAMMING THE PROGRAMMING EXECUTIVE (ROW WRITES)Command



000000040200000000

NOPGOTO 0x200NOP

Step 2: Set the NVMCON register to program 128 instruction words.00000000

240020883B00

MOV #0X4002, W0MOV W0, NVMCON


200FAC8802AC


Step 4: Load W0:W5 with the next four instruction words to program.000000000000000000000000

2xxxx02xxxx12xxxx22xxxx32xxxx42xxxx5

MOV #, W0MOV #, W1MOV #, W2MOV #, W3MOV #, W4MOV #, W5

Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0300000000EB0380000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000

CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOPTBLWTL [W6++], [W7]NOPNOPTBLWTH.B [W6++], [W7++]NOPNOPTBLWTH.B [W6++], [++W7]NOPNOPTBLWTL [W6++], [W7++]NOPNOP

Step 6: Repeat Steps 4 and 5, for a total of 32 times, to load the write latches with 128 instructions.






Step 8: Execute the WR bit unlock sequence and initiate the write cycle.0000000000000000000000000000000000000000

200550883B30200AA0883B30A8E761000000000000000000000000000000

MOV #0x55, W0MOV W0, NVMKEYMOV #0xAA, W0MOV W0, NVMKEYBSET NVMCON, #WRNOPNOPNOPNOPNOP


040200 000000 803B00 A8E761 000000

000000



040200000000

GOTO 0x200NOP

Step 11: Repeat Steps 3 through 9 until all code memory is programmed.Step 12: Clear the WREN bit.

00000000

200000 883B00


TABLE 5-3: PROGRAMMING THE PROGRAMMING EXECUTIVE (ROW WRITES) (CONTINUED)Command




5.4 Reading Executive MemoryReading from executive memory is performed byexecuting a series of TBLRD instructions and clockingout the data using the REGOUT command.

Table 5-4 shows the ICSP programming details forreading executive memory.

To minimize reading time, the same packed dataformat that the PE uses is utilized. See Section 6.2“Programming Executive Commands” for moredetails on the packed data format.

TABLE 5-4: SERIAL EXECUTION FOR READING EXECUTIVE MEMORYCommand

(Binary)Data

(Hex) Description


000000040200000000

NOPGOTO 0x200NOP

Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000

200xx08802A02xxxx6

MOV #, W0MOV W0, TBLPAGMOV #, W6

Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory in W0:W5.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0380000000BA1B96000000000000BADBB6000000000000BADBD6000000000000BA1BB6000000000000BA1B96000000000000BADBB6000000000000BADBD6000000000000BA0BB6000000000000

CLR W7NOPTBLRDL [W6], [W7++]NOPNOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7++]NOPNOPTBLRDL [W6++], [W7++]NOPNOPTBLRDL [W6], [W7++]NOPNOPTBLRDH.B [W6++], [W7++]NOPNOPTBLRDH.B [++W6], [W7++]NOPNOPTBLRDL [W6++], [W7]NOPNOP



Step 4: Output W0:W5 using the VISI register and the REGOUT command.000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000

883C20000000

000000883C21000000

000000883C22000000

000000883C23000000

000000883C24000000

000000883C25000000

000000

MOV W0, VISINOP; Clock out the contents of the VISI register.NOPMOV W1, VISINOP; Clock out the contents of the VISI register.NOPMOV W2, VISINOP; Clock out the contents of the VISI register.NOPMOV W3, VISINOP; Clock out the contents of the VISI register.NOPMOV W4, VISINOP; Clock out the contents of the VISI register.NOPMOV W5, VISINOP; Clock out the contents of the VISI register.NOP


000000040200000000

NOPGOTO 0x200NOP

Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset the device’s internal Program Counter” will be Step 5).

TABLE 5-4: SERIAL EXECUTION FOR READING EXECUTIVE MEMORY (CONTINUED)Command

(Binary)Data

(Hex) Description



5.5 Verify Programming ExecutiveThe verify step involves reading back the executivememory space and comparing it against the copy heldin the programmer’s buffer.

The verify process is illustrated in Figure 5-3. The lowerword of the instruction is read, and then the lower byteof the upper word is read and compared against theinstruction stored in the programmer’s buffer. Referto Section 5.4 “Reading Executive Memory” forimplementation details of reading executive memory.

FIGURE 5-3: VERIFY PROGRAMMING EXECUTIVE MEMORY FLOW

Read Low Word

Read High Byte

Does

= ExpectedData?

AllExecutive Memory

Verified?

No

Yes

No

Set Table Pointer to 0

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

Instruction Word



6.0 THE PROGRAMMING EXECUTIVE

6.1 Programming Executive Communication

The programmer and PE have a master-slaverelationship, where the programmer is the masterprogramming device and the PE is the slave.

All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the PE. In turn, the PE only sends oneresponse to the programmer after receiving andprocessing a command. The PE command set isdescribed in Section 6.2 “Programming ExecutiveCommands”. The response set is described inSection 6.3 “Programming Executive Responses”.

6.1.1 COMMUNICATION INTERFACE AND PROTOCOL

The ICSP/Enhanced ICSP interface is a 2-wire SPI,implemented using the PGECx and PGEDx pins. ThePGECx pin is used as a clock input pin and the clocksource must be provided by the programmer. ThePGEDx pin is used for sending command data to, andreceiving response data from, the PE.

Since a 2-wire SPI is used, and data transmissions arebidirectional, a simple protocol is used to control thedirection of PGEDx. When the programmer completesa command transmission, it releases the PGEDx lineand allows the PE to drive this line high. The PE keepsthe PGEDx line high to indicate that it is processing thecommand.

FIGURE 6-1: PROGRAMMING EXECUTIVE SERIAL TIMING

After the PE has processed the command, it bringsPGEDx low (P9B) to indicate to the programmer that theresponse is available to be clocked out. The programmercan begin to clock out the response after a maximum wait(P9B) and it must provide the necessary amount of clockpulses to receive the entire response from the PE.

After the entire response is clocked out, theprogrammer should terminate the clock on PGECx untilit is time to send another command to the PE. Thisprotocol is illustrated in Figure 6-2.

6.1.2 SPI RATEIn Enhanced ICSP mode, the PIC24FJ256GA705family devices operate from the Fast Internal RC (FRC)Oscillator, which has a nominal frequency of 8 MHz.This oscillator frequency yields an effective systemclock frequency of 4 MHz. To ensure that theprogrammer does not clock too fast, it is recommendedthat a 2 MHz clock be provided by the programmer.

FIGURE 6-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL

Note: For Enhanced ICSP, all serial data istransmitted on the falling edge of PGECxand latched on the rising edge of PGECx.All data transmissions are sent to the MSbfirst, using 16-bit mode (see Figure 6-1).

PGECx

PGEDx

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1BP1A

1 2 15 16 1 2 15 16

PGECx

PGEDx

PGECx = Input PGECx = Input (Idle)

Host TransmitsLast Command Word

PGEDx = Input PGEDx = Output

P8

1 2 15 16

MSB X X X LSB1 0

P9B

PGECx = InputPGEDx = Output

P9A

Programming ExecutiveProcesses Command Host Clocks Out Response

Note 1: See Table 9-1 for timing information.

MSB X X X LSB MSB X X X LSB



6.1.3 TIME-OUTSThe PE uses no Watchdog Timer or time-out fortransmitting responses to the programmer. If theprogrammer does not follow the flow control mechanismusing PGECx, as described in Section 6.1.1“Communication Interface and Protocol”, it ispossible that the PE will behave unexpectedly whiletrying to send a response to the programmer. Since thePE has no time-out, it is imperative that the programmercorrectly follow the described communication protocol.

As a safety measure, the programmer should use thecommand time-outs identified in Table 6-1. If the com-mand time-out expires, the programmer should resetthe PE and start programming the device again.

6.2 Programming Executive Commands

The PE command set is shown in Table 6-1. This tablecontains the opcode, mnemonic, length, time-out anddescription for each command. Functional details on eachcommand are provided in the command descriptions(Section 6.2.4 “Command Descriptions”).

6.2.1 COMMAND FORMATAll PE commands have a general format, consisting ofa 16-bit header and any required data for the command(see Figure 6-3). The 16-bit header consists of a 4-bitopcode field, which is used to identify the command,followed by a 12-bit command length field.

FIGURE 6-3: COMMAND FORMAT

The command opcode must match one of those in thecommand set. Any command that is received, whichdoes not match the list in Table 6-1, will return a “NACK”response (see Section 6.3.1.1 “Opcode Field”). The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. The PE uses thecommand length field to determine the number ofwords to read from the SPI port. If the value of this fieldis incorrect, the command will not be properly receivedby the PE.

TABLE 6-1: PROGRAMMING EXECUTIVE COMMAND SET

15 12 11 0

Opcode Length

Command Data First Word (if required)

•

•

Command Data Last Word (if required)

Opcode Mnemonic Length(16-bit words) Time-out Description

0x0 SCHECK 1 1 ms Sanity check.0x1 READC 3 1 ms Read an 8-bit word from the specified Configuration register

or Device ID register.0x2 READP 4 1 ms/row Read ‘N’ 24-bit instruction words of primary Flash memory,

starting from the specified address.0x3 PROG2W 6 5 ms Program a double instruction word of code memory at the

specified address and verify.0x4 Reserved N/A N/A This command is reserved; it will return a NACK.0x5 PROGP 99 5 ms Program 128 words of program memory at the specified

starting address, then verify.0x6 Reserved N/A N/A This command is reserved; it will return a NACK.0x7 ERASEB 1 125 ms Chip Erase the device.0x8 Reserved N/A N/A This command is reserved; it will return a NACK.0x9 ERASEP 3 25 ms Command to erase a page.0xA Reserved N/A N/A This command is reserved; it will return a NACK.0xB QVER 1 1 ms Query the PE software version.0xC CRCP 5 1s Perform a CRC-16 on the specified range of memory.0xD Reserved N/A N/A This command is reserved; it will return a NACK.0xE QBLANK 5 700 ms Query to check whether the code memory is blank.



6.2.2 PACKED DATA FORMATWhen 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format illustrated in Figure 6-4. Thisformat minimizes traffic over the SPI and provides thePE with data that is properly aligned for performingTable Write operations.

FIGURE 6-4: PACKED INSTRUCTION WORD FORMAT

6.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING

The PE will “NACK” all unsupported commands. Addi-tionally, due to the memory constraints of the PE, nochecking is performed on the data contained in theprogrammer command. It is the responsibility of theprogrammer to command the PE with valid commandarguments or the programming operation may fail.Additional information on error handling is provided inSection 6.3.1.3 “QE_Code Field”.

6.2.4 COMMAND DESCRIPTIONSAll commands supported by the PE are described inSection 6.2.4.1 “SCHECK Command” throughSection 6.2.4.10 “QBLANK Command”.

6.2.4.1 SCHECK Command

Table 6-2 shows the description for the SCHECKcommand.

TABLE 6-2: COMMAND DESCRIPTION

The SCHECK command instructs the PE to do nothingbut generate a response. This command is used as a“Sanity Check” to verify that the PE is operational.

Expected Response (2 words):0x1000 0x0002

Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 cannot be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word

15 12 11 0Opcode Length

Field Description

Opcode 0x0Length 0x1

Note: This instruction is not required forprogramming, but is provided fordevelopment purposes only.



6.2.4.2 READC Command

Table 6-3 shows the description for the READCcommand.


The READC command instructs the PE to readN Configuration registers or Device ID registers,starting from the 24-bit address specified by Addr_MSBand Addr_LS. This command can only be used to read8-bit or 16-bit data.

When this command is used to read Configurationregisters, the upper byte in every data word returnedby the PE is 0x00 and the lower byte contains theConfiguration register value.

Expected Response (4 + 3 * (N – 1)/2 words for N odd):

0x1100

2 + N

Configuration Register or Device ID Register 1

...

Configuration Register or Device ID Register N

6.2.4.3 READP Command

Table 6-4 shows the description for the READPcommand.


The READP command instructs the PE to read N 24-bitwords of code memory, starting from the 24-bit addressspecified by Addr_MSB and Addr_LS. This commandcan only be used to read 24-bit data. All data returned inresponse to this command uses the packed data formatdescribed in Section 6.2.2 “Packed Data Format”.Expected Response (2 + 3 * N/2 words for N even):

0x1200

2 + 3 * N/2

Least Significant Program Memory Word 1

...

Least Significant Data Word N

Expected Response (4 + 3 * (N – 1)/2 words for N odd):

0x1200

4 + 3 * (N – 1)/2

Least Significant Program Memory Word 1

...

MSB of Program Memory Word N (zero-padded)

15 12 11 8 7 0Opcode Length

N Addr_MSBAddr_LS

Field Description

Opcode 0x1Length 0x3N Number of 8-bit Configuration registers

or Device ID registers to read (maximum of 256)

Addr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit

source address

Note: Reading unimplemented memory willcause the PE to reset. To prevent this fromoccurring, ensure that only memory loca-tions present on a particular device areaccessed.


NReserved Addr_MSB

Addr_LS

Field Description

Opcode 0x2Length 0x4N Number of 24-bit instructions to read

(maximum of 32768)Reserved 0x0Addr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit

source address

Note: Reading unimplemented memory willcause the PE to reset. To prevent this fromoccurring, ensure that only memory loca-tions present on a particular device areaccessed.



6.2.4.4 PROG2W Command

Table 6-5 shows the description for the PROG2Wcommand.


The PROG2W command instructs the PE to programtwo instruction words of code memory (6 bytes) to thespecified memory address.

After the words have been programmed to codememory, the PE verifies the programmed data againstthe data in the command.

Expected Response (2 words):0x1300

0x0002

6.2.4.5 PROGP Command

Table 6-6 shows the description for the PROGPcommand.


The PROGP command instructs the PE to program onerow of code memory (128 instruction words) to thespecified memory address. Programming begins withthe row address specified in the command. Thedestination address should be a multiple of 0x100.

The data to program the memory, located in commandwords, D_1 through D_96, must be arranged using thepacked instruction word format illustrated in Figure 6-4.

After all data has been programmed to code memory,the PE verifies the programmed data against the datain the command.


0x0002


Reserved Addr_MSBAddr_LSDataL_LS

DataH_MSB DataL_MSBDataH_LS

Field Description

Opcode 0x3Length 0x6DataL_MSB MSB of 24-bit data for low instruction

wordDataH_MSB MSB of 24-bit data for high instruction

wordAddr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit

destination addressDataL_LS Least Significant 16 bits of 24-bit data

for low instruction wordDataH_LS Least Significant 16 bits of 24-bit data

for high instruction word


Reserved Addr_MSBAddr_LS

D_1D_2...

D_N

Field Description

Opcode 0x5Length 0x63Reserved 0x0Addr_MSB MSB of 24-bit destination addressAddr_LS Least Significant 16 bits of 24-bit

destination addressD_1 16-bit Data Word 1D_2 16-bit Data Word 2... 16-bit Data Word 3 through 95D_96 16-bit Data Word 96

Note: Refer to Table 2-2 for code memory sizeinformation.



6.2.4.6 ERASEB Command

Table 6-7 shows the description for the ERASEBcommand.


The ERASEB command instructs the PE to perform aChip Erase (i.e., erase all of the primary Flash memoryand code-protect bits).


0x0002

6.2.4.7 ERASEP Command

Table 6-8 shows the description for the ERASEPcommand.


The ERASEP command instructs the PE to Page Erase[NUM_PAGES] of code memory. The code memorymust be erased at an “even” 1024 instruction wordsaddress boundary.


0x0002

6.2.4.8 QVER Command

Table 6-9 shows the description for the QVER command.


The QVER command queries the version of the PEsoftware stored in test memory. The “version.revision”information is returned in the response’s QE_Code,using a single byte with the following format: mainversion in upper nibble and revision in the lower nibble(i.e., 0x23 means Version 2.3 of PE software).

Expected Response (2 words):0x1BMN (where “MN” stands for version M.N)

0x0002


Field Description

Opcode 0x7Length 0x1

15 12 11 8 7 0

Opcode Length

NUM_PAGES Addr_MSB

Addr_LS

Field Description

Opcode 0x9Length 0x3NUM_PAGES Up to 255Addr_MSB Most Significant Byte of the 24-bit

addressAddr_LS Least Significant 16 bits of the 24-bit

address


Field Description

Opcode 0xBLength 0x1



6.2.4.9 CRCP Command

Table 6-10 shows the description for the CRCP command.


The CRCP command performs a CRC-16 on the range ofmemory specified. This command can substitute for a fullchip verify. Data is shifted in a packed method, as demon-strated in Figure 6-4, byte-wise, Least Significant Byte(LSB) first.

Example:CRC-CCITT-16 with test data of “123456789” becomes0x29B1

Expected Response (3 words):QE_Code: 0x1C00

Length: 0x0003

CRC Value: 0xXXXX

6.2.4.10 QBLANK Command

Table 6-11 shows the description for the QBLANKcommand.


The QBLANK command queries the PE to determine ifthe contents of code memory are blank (contains all‘1’s). The size of code memory to check must bespecified in the command.

The Blank Check for code memory begins at [Addr] andadvances toward larger addresses for the specifiednumber of instruction words.

QBLANK returns a QE_Code of 0xF0 if the specifiedcode memory is blank; otherwise, QBLANK returns aQE_Code of 0x0F.

Expected Response (2 words for blank device):0x1DF0

0x0002

Expected Response (2 words for non-blank device):0x1D0F

0x0002

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LSW

Reserved Size_MSB

Size_LSW

Field Description

Opcode 0xCLength 0x5Addr_MSB Most Significant Byte of 24-bit

addressAddr_LSW Least Significant 16 bits of 24-bit

addressSize Number of 24-bit locations (address

range divided by 2)


Reserved Size_MSBSize_LSW

Reserved Addr_MSBAddr_LSW

Field Description

Opcode 0xELength 0x5Size Length of program memory to check

(in 24-bit words) + Addr_MSAddr_MSB Most Significant Byte of the 24-bit

addressAddr_LSW Least Significant 16 bits of the 24-bit

address

Note: The QBLANK command does not check thesystem operation Configuration bits, sincethese bits are not set to ‘1’ when a ChipErase is performed.



6.3 Programming Executive Responses

The PE sends a response to the programmer for eachcommand that it receives. The response indicates if thecommand was processed correctly. It includes anyrequired response data or error data.

The PE response set is shown in Table 6-12. This tablecontains the opcode, mnemonic and description foreach response. The response format is described inSection 6.3.1 “Response Format”.

TABLE 6-12: PROGRAMMING EXECUTIVE RESPONSE OPCODES

6.3.1 RESPONSE FORMATAll PE responses have a general format, consisting of atwo-word header and any required data for thecommand.

Table 6-13 shows the description of the responseformat.

TABLE 6-13: RESPONSE FORMAT DESCRIPTION

6.3.1.1 Opcode FieldThe opcode is a 4-bit field in the first word of theresponse. The opcode indicates how the commandwas processed (see Table 6-12). If the command wasprocessed successfully, the response opcode is PASS.If there was an error in processing the command, theresponse opcode is FAIL and the QE_Code indicatesthe reason for the failure. If the command sent to thePE is not identified, the PE returns a NACK response.

6.3.1.2 Last_Cmd FieldThe Last_Cmd is a 4-bit field in the first word of theresponse and indicates the command that the PE pro-cessed. Since the PE can only process one commandat a time, this field is technically not required. However,it can be used to verify that the PE correctly receivedthe command that the programmer transmitted.

Opcode Mnemonic Description

0x1 PASS Command successfully processed.

0x2 FAIL Command unsuccessfully processed.

0x3 NACK Command not known.

15 12 11 8 7 0

Opcode Last_Cmd QE_Code

Length

D_1 (if applicable)

...

D_N (if applicable)

Field Description

Opcode Response opcode.Last_Cmd Programmer command that

generated the response.QE_Code Query code or error code.Length Response length in 16-bit words

(includes 2 header words).D_1 First 16-bit data word (if applicable).D_N Last 16-bit data word (if applicable).



6.3.1.3 QE_Code FieldThe QE_Code is a byte in the first word of theresponse. This byte is used to return data for querycommands and error codes for all other commands.

When the PE processes one of the two query com-mands (QBLANK or QVER), the returned opcode isalways PASS and the QE_Code holds the queryresponse data. The format of the QE_Code for bothqueries is shown in Table 6-14.

TABLE 6-14: QE_Code FOR QUERIES

When the PE processes any command other than aquery, the QE_Code represents an error code.Supported error codes are shown in Table 6-15. If acommand is su

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PIC24FJ256GA705 Family Flash Programming Specificationww1.microchip.com/downloads/en/DeviceDoc/PIC24FJ256GA705... · 2018. 8. 15. · PIC24FJ256GA705 FAMILY DS30010102C-page 2 2015-2018