PIC18F Programming Model and Its Instruction Set

PIC18F Programming Model and Its Instruction Set

Chapter 3

Access RAMAccess RAM

Data Memory Organization

PIC16F8F2520/4520Register File Map

000h07Fh

256 Bytes

Bank 0 GPRBank 0 GPR

Bank 1GPR

Bank 1GPR

Bank 2GPR

Bank 2GPR

Bank 13GPR

Bank 13GPR

Bank 14GPR

Bank 14GPR

Bank 15 GPRBank 15 GPR

Access SFRAccess SFR

Access RAMAccess RAM

Access SFRAccess SFR

080h0FFh

100h

1FFh

200h

2FFh

D00h

DFFh

E00h

EFFh

F00h

FFFh

F7Fh

F80h

00h7Fh

80hFFh

Access Bank

Data Memory up to 4k bytes Divided into 256 byte banks Half of bank 0 and half of

bank 15 form a virtual bank that is accessible no matter which bank is selected

Remember:

Register File Concept

Data

Bus

Data

Bus

d

Decoded Instruction from Program

Memory:

Arithmetic/Logic Function to be Performed Result

Destination

Address of Second Source Operand

Register File Concept: All of data memory is part of the register file, so any location in data memory may be operated on directly

All peripherals are mapped into data memory as a series of registers

Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location

w f

w f

ALU

WREGWREG

Data Memory(Register File)

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

OpcodeOpcode dd aa AddressAddress

PIC18F Programming Model (1 of 2)

The representation of the internal architecture of a microprocessor, necessary to write assembly language programs Programming Model

Two Groups of Registers in PIC16 8-bit Programming Model ALU Arithmetic Logic Unit (ALU) Special Function Registers (SFRs) from data

memory

PIC18F Programming Model (2 of 2)

Registers WREG

8-bit Working Register (equivalent to an accumulator)

Used for arithmetic and logic operations BSR: Bank Select Register (0 to F)

4-bit Register Only low-order four bits are used to provide MSB

four bits of a12-bit address of data memory.

1111 0000 0000 0000 0000 0000 1111

Register Direct Addressing4-bits from BSR Register 8-bits Encoded in Instruction

BSR (Bank Select Register) ‘f’ Operand

00000000 0000 1111 0000 0x2820x2820x2820x282

12-bit Effective Address(Use this when coding)

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

00

Bank0

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

01

02

03

7D

7E

7F

80

81

82

FC

FD

FE

FF

Bank1 Bank2

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

Bank13 Bank14 Bank15

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

FFFF

‘a’ Bit fromInstruction

STATUS: Flag Register Flags in Status Register

C (Carry/Borrow Flag): set when an addition generates a carry and a subtraction generates a borrow

DC (Digit Carry Flag): also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an arithmetic operation Used for BCD representation

Z (Zero Flag): set when result of an operation is zero OV (Overflow Flag): set when result of an operation of signed numbers goes

beyond seven bits N (Negative Flag): set when bit B7 is one of the result of an arithmetic /logic

operation

Example: 9F+52 =F11001 11110101 0010-------------1111 0001 N=1,OV=0, Z=0, C=0, DC=1

File Select Registers (FSR) (1 of 2)

Three registers holding 12-bit address of data registers FSR0, FSR1, and FSR2

File Select Registers composed of two 8-bit registers (FSRH and FSRL)

Used as pointers for data registers for indirect addressing Associated with index (INDF) registers

Find FSR0-FSR2 in Special Function Register – page 64 What are the File addresses for each? / How many INDF do you find?

Program Counter

0123456789101112

PCLPCH

Program Counter 21-bit PC can access up to 221 = 2MB (1MWord) 22nd bit used to access configuration memory at program time or via table reads &

writes Contains address of NEXT instruction (pipelining) Lower byte accessible in data memory as PCL Upper bytes indirectly accessible via PCLATH/PCLATU Bit 0 of PC is always ‘0’ except when reading or writing program memory via

table read/write mechanism

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

131415161718192021

PCU

21-bit register functions as a pointer to program memory during program execution

Program Memory is Byte Addressable Low byte has even address, high byte has odd address Addresses of instructions are always even

16-bit Program Memory

0x000000

0x000002

0x000004

0x000006

0x000008

0x00000A

0x00000C

0x00000E

0x000001

0x000003

0x000005

0x000007

0x000009

0x00000B

0x00000D

0x00000F

High Byte Address Low Byte AddressWord Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC

File Select Registers (FSR) (2 of 2)

Table Pointer 21-bit register used as a

memory pointer to copy bytes between program memory and data registers

Stack Pointer (SP) Stack is a group of 31 word-

size registers used for temporary storage of memory address during execution

Requires 5-bit address Saved in STKPTR in SFR

Special Function Registers (SFRs): Data registers associated

with I/O ports, support devices, and processes of data transfer

Examine Table 3-1 – Page 64

Introduction to PIC18 Instruction Set Includes 77 instructions; 73 one-word (16-bit) long and

four two-words (32-bit) long Divided into seven groups

Move (Data Copy) and Load Arithmetic Logic Program Redirection (Branch/Jump) Bit Manipulation Table Read/Write Machine Control

Move and Load Instructions MOVLW 8-bit ;Load an 8-bit literal in WREG MOVLW 0 x F2

MOVWF F, a ;Copy WREG in File (Data) Reg.; If a = 0, F is in Access Bank ;If a = 1, Bank is specified by BSR

MOVWF 0x25, 0 ;Copy W in Data Reg.25H

MOVFF fs, fd ;Copy from one Data Reg. to ;another Data Reg.

MOVFF 0x20,0x30 ;Copy Data Reg. 20 into Reg.30

Arithmetic Instructions (1 of 3)

ADDLW 8-bit ;Add 8-bit number to WREG ADDLW 0x32 ;Add 32H to WREG

ADDWF F, d, a ;Add WREG to File (Data) Reg.;Save result in W if d =0;Save result in F if d = 1

ADDWF 0x20, 1 ;Add WREG to REG20 and ;save result in REG20

ADDWF 0x20, 0 ;Add WREG to REG20 and ;save result in WREG


ADDWFC F, d, a ;Add WREG to File Reg. with ;Carry and save result in W or F

SUBLW 8-bit ;Subtract WREG from literal SUBWF F, d, a ;Subtract WREG from File Reg. SUBWFB F, d, a ;Subtract WREG from File Reg.

;with Borrow INCF F, d, a ;Increment File Reg. DECF F, d, a ;Decrement File Reg. COMF F, d, a ;Complement File Reg. NEGF F, a ;Take 2’s Complement-File Reg.


MULLW 8-bit ;Multiply 8-bit and WREG ;Save result in PRODH-PRODL

MULWF F, a ;Multiply WREG and File Reg. ;Save result in PRODH-PRODL

DAW ;Decimal adjust WREG for BCD

;Operations

Logic Instructions ANDLW 8-bit ;AND literal with WREG ANDWF F, d, a ;AND WREG with File Reg. and

;save result in WREG/ File Reg.

IORLW 8-bit ;Inclusive OR literal with WREG IORWF F, d, a ;Inclusive OR WREG with File Reg.

;and save result in WREG/File Reg.

XORLW 8-bit ;Exclusive OR literal with WREG XORWF F, d, a ;Exclusive OR WREG with File Reg.

;and save result in WREG/File Reg.

Branch Instructions BC n ;Branch if C flag = 1 within + or – 64 Words BNC n ;Branch if C flag = 0 within + or – 64 Words BZ n ;Branch if Z flag = 1 within + or – 64 Words BNZ n ;Branch if Z flag = 0 within + or – 64 Words BN n ;Branch if N flag = 1 within + or – 64 Words BNN n;Branch if N flag = 0 within + or – 64 Words BOV n ;Branch if OV flag = 1 within + or – 64 Words BNOV n ;Branch if OV flag = 0 within + or – 64 Words GOTO Address: Branch to 20-bit address unconditionally

Call and Return Instructions RCALL nn ;Call subroutine within +or – 512 words

CALL 20-bit, s ;Call subroutine ;If s = 1, save W, STATUS, and BSR

RETURN, s ;Return subroutine ;If s = 1, retrieve W, STATUS, and BSR RETFIE, s ;Return from interrupt ;If s = 1, retrieve W, STATUS, and BSR

Bit Manipulation Instructions BCF F, b, a ;Clear bit b of file register. b = 0 to 7 BSF F, b, a ;Set bit b of file register. b = 0 to 7 BTG F, b, a ;Toggle bit b of file register. b = 0 to 7

RLCF F, d, a ;Rotate bits left in file register through; carry and save in W or F register

RLNCF F, d, a ;Rotate bits left in file register ; and save in W or F register

RRCF F, d, a ;Rotate bits right in file register through ; carry and save in W or F register RRNCF F, d, a ;Rotate bits right in file register

; and save in W or F register

Test and Skip Instructions BTFSC F, b, a ;Test bit b in file register and skip the

;next instruction if bit is cleared (b =0) BTFSS F, b, a ;Test bit b in file register and skip the

;next instruction if bit is set (b =1) CPFSEQ F, a ;Compare F with W, skip if F = W CPFSGT F, a ;Compare F with W, skip if F > W CPFSLT F, a ;Compare F with W, skip if F < W TSTFSZ F, a;Test F; skip if F = 0

Increment/Decrement and Skip Next Instruction

DECFSZ F, b, a ;Decrement file register and skip the ;next instruction if F = 0

DECFSNZ F, b, a ;Decrement file register and skip the ;next instruction if F ≠ 0

INCFSZ F, b, a ;Increment file register and skip the ;next instruction if F = 0

INCFSNZ F, b, a ;Increment file register and skip the ;next instruction if F ≠ 0

Table Read/Write Instructions (1 of 2)

TBLRD* ;Read Program Memory pointed by TBLPTR;into TABLAT

TBLRD*+ ;Read Program Memory pointed by TBLPTR;into TABLAT and increment TBLPTR

TBLRD*- ;Read Program Memory pointed by TBLPTR;into TABLAT and decrement TBLPTR

TBLRD+* ; Increment TBLPTR and Read Program ; Memory pointed by TBLPTR into TABLAT

Table Read/Write Instructions (2 of 2)

TBLWT* ;Write TABLAT into Program Memory pointed ;by TBLPTR

TBLWT*+ ; Write TABLAT into Program Memory pointed ;by TBLPTR and increment TBLPTR

TBLWT*- ; Write TABLAT into Program Memory pointed ;by TBLPTR and decrement TBLPTR

TBLWT+* ; Increment TBLPTR and Write TABLAT into ; Program Memory pointed by TBLPTR

Machine Control Instructions CLRWDT ;Clear Watchdog Timer

Helps recover from software malfunction Uses its own free-running on-chip RC oscillator WDT is cleared by CLRWDT instruction

RESET ;Reset all registers and flags When voltage < a particular threshold, the device is held in reset

Prevents erratic or unexpected operation

SLEEP ;Go into standby mode NOP ;No operation

Events that wake processor from sleepEvents that wake processor from sleepEvents that wake processor from sleepEvents that wake processor from sleepMCLRMCLR

WDTWDT

INTINT

TMR1TMR1

ADCADC

CMPCMP

CCPCCP

PORTBPORTB

SSPSSP

PSPPSP

Sleep Mode The processor can be put into a power-down mode by executing the SLEEP instruction

System oscillator is stopped Processor status is maintained (static design) Watchdog timer continues to run, if enabled Minimal supply current is drawn - mostly due to leakage (0.1 - 2.0A typical)

Master Clear Pin Asserted (pulled low)Master Clear Pin Asserted (pulled low)

Watchdog Timer TimeoutWatchdog Timer Timeout

INT Pin InterruptINT Pin Interrupt

Timer 1 Interrupt (or also TMR3 on PIC18)Timer 1 Interrupt (or also TMR3 on PIC18)

A/D Conversion Complete InterruptA/D Conversion Complete Interrupt

Comparator Output Change InterruptComparator Output Change Interrupt

Input Capture EventInput Capture Event

PORTB Interrupt on ChangePORTB Interrupt on Change

Synchronous Serial Port (I2C Mode) Start / Stop Bit Detect InterruptSynchronous Serial Port (I2C Mode) Start / Stop Bit Detect Interrupt

Parallel Slave Port Read or WriteParallel Slave Port Read or Write

Instruction Format (1 of 3)

The PIC18F instruction format divided into four groups Byte-Oriented operations Bit-Oriented operations Literal operations Branch operations

PIC18 Instruction Set Overview –

f f f f f f fdOpcode

07815

f f f f f f fOpcode

File Register Address

Byte Oriented Operations

ADDWF 0x25, W, A

DestinationFile Register Address

a f

fa

9

Destination (W or F) Access Bank

Use Access Bank(Optional)

OR

Instruction Set Overview

f f f f f f fbb bOpcode

078915


Bit Position (0-7)

Bit Oriented Operations

BSF 0x25, 3, A

Access Bank(Optional)


11

fa

Bit Position

f f f f f f fbb bOpcode

078915


Bit Position (0-7)

Bit Oriented Operations

BSF 0x25, 3, A

Access Bank(Optional)


11

fa

Bit Position


07815

k k k k k k kOpcode

Literal Value

Literal and Control Operations

MOVLW 0x25

Literal Value

k

Opcode

OR

Instruction Set Overview- Two-word instruction

0111215

fs fs fs fs fs fs fsfs fsOpcode fs

Source Register Address

Byte to Byte Move Operations (2 Words)

MOVFF 0x125, 0x140

Source Address

fs fs

fd fd fd fd fd fd fdfdfd fd fdfdOpcodeDestination Register Address

Destination Address


07815

n7 n6 n5 n4 n3 n2 n1Opcode

Call and Goto Operations (2 Words)

CALL 0x1125

Subroutine Address

n8

n9Opcode

11

n10n11n12n13n14n15n16n17n18n19n20

Byte Oriented OperationsByte Oriented Operations

PIC18 Instruction Set Overview – operation types: Byte-oriented, bit-oriented, literal, program redirection

addwf f,d,aaddwf f,d,a

addwfc f,d,aaddwfc f,d,a

andwf f,d,aandwf f,d,a

clrf f,aclrf f,a

comf f,d,acomf f,d,a

cpfseq f,acpfseq f,a

cpfsgt f,acpfsgt f,a

cpfslt f,acpfslt f,a

decf f,d,adecf f,d,a

decfsz f,d,adecfsz f,d,a

dcfsnz f,d,adcfsnz f,d,a

incf f,d,aincf f,d,a

incfsz f,d,aincfsz f,d,a

infsnz f,d,ainfsnz f,d,a

iorwf f,d,aiorwf f,d,a

movf f,d,amovf f,d,a

movff fs,fdmovff fs,fd

movwf f,amovwf f,a

mulwf f,amulwf f,a

negf f,anegf f,a

rlcf f,d,arlcf f,d,a

rlncf f,d,arlncf f,d,a

rrcf f,d,arrcf f,d,a

rrncf f,d,arrncf f,d,a

setf f,asetf f,a

subfwb f,d,asubfwb f,d,a

subwf f,d,asubwf f,d,a

subwfb f,d,asubwfb f,d,a

swapf f,d,aswapf f,d,a

tstfsz f,atstfsz f,a

xorwf f,d,axorwf f,d,a

Add WREG and fAdd WREG and f

Add WREG and Carry bit to fAdd WREG and Carry bit to f

AND WREG with fAND WREG with f

Clear fClear f

Complement fComplement f

Compare f with WREG, skip =Compare f with WREG, skip =

Compare f with WREG, skip >Compare f with WREG, skip >

Compare f with WREG, skip <Compare f with WREG, skip <

Decrement fDecrement f

Decrement f, Skip if 0Decrement f, Skip if 0

Decrement f, Skip if Not 0Decrement f, Skip if Not 0

Increment fIncrement f

Increment f, Skip if 0Increment f, Skip if 0

Increment f, Skip if Not 0Increment f, Skip if Not 0

Inclusive OR WREG with fInclusive OR WREG with f

Move fMove f

Move fs (src) to fd (dst)Move fs (src) to fd (dst)

Move WREG to fMove WREG to f

Multiply WREG with fMultiply WREG with f

Negate fNegate f

Rotate Left f through CarryRotate Left f through Carry

Rotate Left f (No Carry)Rotate Left f (No Carry)

Rotate Right f through CarryRotate Right f through Carry

Rotate Right f (No Carry)Rotate Right f (No Carry)

Set fSet f

Subtract f from WREG with borrowSubtract f from WREG with borrow

Subtract WREG from fSubtract WREG from f

Subtract WREG from f with borrowSubtract WREG from f with borrow

Swap nibbles in fSwap nibbles in f

Test f, skip if 0Test f, skip if 0

Exclusive OR WREG with fExclusive OR WREG with f

Bit Oriented OperationsBit Oriented Operations

bcf f,b,abcf f,b,a

bsf f,b,absf f,b,a

btfsc f,b,abtfsc f,b,a

btfss f,b,abtfss f,b,a

btg f,b,abtg f,b,a

Bit Clear fBit Clear f

Bit Set fBit Set f

Bit Test f, Skip if ClearBit Test f, Skip if Clear

Bit Test f, Skip if SetBit Test f, Skip if Set

Bit Toggle fBit Toggle f

Literal OperationsLiteral Operations

PIC18 Instruction Set OverviewControl OperationsControl Operations

bc nbc n

bn nbn n

bnc nbnc n

bnn nbnn n

bnov nbnov n

bnz nbnz n

bov nbov n

bra nbra n

bz nbz n

call n,scall n,s

clrwdtclrwdt

dawdaw

goto ngoto n

nopnop

poppop

pushpush

rcall nrcall n

resetreset

retfie sretfie s

return sreturn s

sleepsleep

addlw kaddlw k

andlw kandlw k

iorlw kiorlw k

lfsr f,klfsr f,k

movlb kmovlb k

movlw kmovlw k

mullw kmullw k

retlw kretlw k

sublw ksublw k

Branch if CarryBranch if Carry

Branch if NegativeBranch if Negative

Branch if Not CarryBranch if Not Carry

Branch if Not NegativeBranch if Not Negative

Branch if Not OverflowBranch if Not Overflow

Branch if Not ZeroBranch if Not Zero

Branch if OverflowBranch if Overflow

Branch AlwaysBranch Always

Branch if ZeroBranch if Zero

Call subroutineCall subroutine

Clear Watchdog TimerClear Watchdog Timer

Decimal Adjust WREGDecimal Adjust WREG

Go to addressGo to address

No OperationNo Operation

Pop top of return stack (TOS)Pop top of return stack (TOS)

Push top of return stack (TOS)Push top of return stack (TOS)

Relative CallRelative Call

Software device RESETSoftware device RESET

Return from interruptReturn from interrupt

Return from subroutineReturn from subroutine

Go into standby modeGo into standby mode

Add literal and WREGAdd literal and WREG

AND literal with WREGAND literal with WREG

Inclusive OR literal with WREGInclusive OR literal with WREG

Move 12-bit literal to FSRMove 12-bit literal to FSR

Move literal to BSR<3:0>Move literal to BSR<3:0>

Move literal to WREGMove literal to WREG

Multiply literal with WREGMultiply literal with WREG

Return with literal in WREGReturn with literal in WREG

Subtract WREG from literalSubtract WREG from literal

Data Memory Program Memory OperationsData Memory Program Memory Operations

tblrd*tblrd*

tblrd*+tblrd*+

tblrd*-tblrd*-

tblrd+*tblrd+*

tblwt*tblwt*

Table ReadTable Read

Table Read with post-incrementTable Read with post-increment

Table Read with post-decrementTable Read with post-decrement

Table Read with pre-incrementTable Read with pre-increment

Table WriteTable Write

xorlw kxorlw k Exclusive OR literal with WREGExclusive OR literal with WREG

tblwt*+tblwt*+ Table Write with post-incrementTable Write with post-increment

tblwt*-tblwt*- Table Write with post-decrementTable Write with post-decrement

tblwt+*tblwt+* Table Write with pre-incrementTable Write with pre-increment

Execution of an Instruction Instruction: MOVLW 0x37 ; Load 37H in W

Memory Hex Mnemonics

Address Code

000020 37 MOVLW 0x37

000021 0E

ExampleORG 0x20REG0 EQU 0x00REG1 EQU 0x01REG2 EQU 0x02

MOVLW 0x37MOVWF REG0,0MOVLW 0x92MOVWF REG1,0ADDWF REG0,0MOVWF REG2, 0SLEEP Explain what this program does,

specify PC value for each line, which flags are changed as the program is

executed.

ExampleORG 0x20REG0 EQU 0x00REG1 EQU 0x01REG2 EQU 0x02

MOVLW 0x37MOVWF REG0,0MOVLW 0x92MOVWF REG1,0ADDWF REG0,0MOVWF REG2, 0SLEEP

Instruction Pipelining

rcall SUB1

addwf REG0

movlw 0x37MAIN

movwf REG0

1

2

3

4

Example ProgramFetch Execute

T0

Flush

T1 T2 T3 T4 T5

Instruction Cycles

T6

Fetch Execute

Fetch Execute

Fetch

T7

addwf REG0

Pre-Fetched Instruction

Rcall is calling the subroutine SUB1 2 cycles

More slides ……

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PIC18F Programming Model and Its Instruction Set