pic18 interrupt 2

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The University of Texas at Arlington

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Lecture 9

Interrupts

CSE 3442/5442

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Interrupts

An asynchronous (could happen any time)signal indicating the need for immediateattention to the processor.

A way to tell the processor that a peripheralneeds attention, without the processorconstantly polling that peripheral.

The processor can elect to ignore (mask)

various interrupts or can elect to suspend itscurrent execution and jump to a ROM location toexecute an interrupt handler routine.


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Interrupts vs. Polling

We have seen before that we can wait for peripherals to finishtheir tasks by constantly polling their SFR.

When polling the microcontroller has to spend a considerableamount of time evaluating the content of a register which willpossibly keep it from doing work it needs to.

Furthermore, with polling the time when the peripherals needis realized may be too late (e.g., waiting for serial data tocome in).

When using polling and serving one peripheral, another(maybe more important) peripheral may be starved ofattention it needs promptly. We cannot assign priorities.

If we are using more than one peripheral the above problems

really show themselves and interrupts will look better andbetter to serve our purposes. If the microcontroller would have a sleep state, interrupts

would be great to wake it (and indeed).

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Interrupt Service Routines

If indeed we can have peripherals interrupting thecurrent processing, then we need programs that canhandle these interrupts.

Interrupt service routines (ISR) serve that purpose.

The processor will need to know where to jump to (in theprogram ROM) when a non-masked interrupt hits. Theselocations are known as the interrupt vector table. On some CPU-s there are more such addresses (PIC18,586)

and on others there is but a single one (PIC16).

On some CPU-s this address is reconfigurable and on some it isnot (PIC18).


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Interrupt Vectors of PIC18

The PIC18 has two (three) special locations(interrupt vectors) for interrupts (i.e., threeentries for an interrupt vector table):

1. High Priority Interrupt at address: 0008

2. Low Priority Interrupt at address: 0018

3. Power-on reset at address: 0000

As there is limited space at these addresses itis a good idea to place a GOTO instruction at

the interrupt vector jumping to a remotelocation for the ISR implementation.

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What Happens When an Interrupt Hits?

The current instructions execution is finishedand the next instructions address is pushed tothe stack. Interrupts are disabled (GIE or GIEHor GIEL cleared).

The PC is loaded with the interrupt vector (jumpto the ISR)

The instructions in the ISR are executed until aRETFIE instruction

RETFIE will cause the microcontroller to pop thePC from the stack and resume normaloperations (unless more interrupts pending).Interrupts are enabled (GIE or GIEH or GIELset).


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PIC18 Sources of Interrupts

Many peripherals can ask for the attention of the CPU: Each timer can ask for an interrupt (well cover them later)

Hardware interrupts: pins designated as INT0, INT1, and INT2(likely RB0,RB1,RB2) can function as digital inputs and if theirlevel is changing can cause an interrupt.

PORTB hardware interrupts: some other pins of PORTB cansignal interrupts but not individually (the user will need to checkwhat changed)

The serial communication peripheral if it received or transmitteda byte can interrupt.

The ADC can signal that it has finished converting

The compare/capture/PWM module can signal for attention

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Masking Interrupts

By default though, all interrupts are masked (disabled). Itis up to the user to enable them if they are needed.

Enabling/disabling interrupts is done through designatedregisters in the SFR: INTCON, INTCON2, INTCON3

RCON

PIR1, PIR2, PIR3

PIE1, PIE2, PIE3

IPR1, IPR2, IPR3

All interrupts can be masked by clearing the GIE(general Interrupt enable) bit in INTCON (default).


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Simplified View of Interrupts

We can easily think of interrupts as digital signals.

In general, each interrupt has two signals:

A flag that is set if interrupt should be invoked

A masking bit that can disable the actual interrupt from

happening

To make things confusing, some peripherals can bemasked in a group by a PEIE mask.

A very simplified view with omitting some flags and some masks

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Enabling Interrupts

GIE in INTCON has to be set(BSF INTCON, GIE)

We need to find the interrupt mask for theperipheral we want to use and set it high.

As some interrupts are designated asperipheral interrupts (IMHO a bad

nomenclature) for some interrupts thePEIE bit needs to be set(BSF INTCON, PEIE)


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Two Levels of Priorities

The PIC18 has two levels of interrupts By default (when reset) all interrupts are high priority

(compatibility) (address 00008H)

In RCON we can enable the two-level priority option by settingIPEN(SETF RCON, IPEN)

Then we can assign low or high priority to interrupts bysetting/clearing an interrupt priority bit in the IPRx SFRs. Thismeans that there really are three bits controlling each interrupt.

The INT0 (RB0) hardware interrupt can only be of high priority. If two-level priority is enabled, GIE will become GIEH (for high

priority) and PEIE will become GIEL (for low priority)

Low priority interrupts will go to a different handler (address00018H) Most importantly: When handling a low priority interrupt, high

priority interrupts can steal the processor away (thus the wordpriority).

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What Happens to Other ImportantRegisters?

As we have seen, only the PC has a real(!) stack

So, what happens to other important registers(WREG, Status, BSR) that may be impacted byan interrupt (especially as they should be found

the same way as they were left when returning!)

The solution lies in the ISR having to save these

register at the beginning and restoring at the end(order!).


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What Happens to Other ImportantRegisters? Fast Context Switching

Alternatively, the microcontroller could do this (saveregisters) for us.

There is a one-deep shadow register set for WREG,Status and BSR.

The user has no access to this fast return registerstack.

ISRs making use of this should return with RETFIE 0x01 If both high and low priority interrupts are enabled and

indeed low priority interrupts are preemptable (they donot disable GIEH right away) then this option cannot beused (as there will be an interrupt within an interrupt).

This feature can be used for regular subroutines as wellunderstanding that it is but one deep (CALL LABEL,FAST and RETURN FAST)

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Some Remarks

As interrupts are asynchronous (especially if they are external),there is a latency for handling them (CPU has to finish current task).This latency can be from two instruction cycles to four instructioncycles (especially for external interrupts).

In many cases the interrupt flag has to be cleared when handling theinterrupt to avoid the flag to recursively re-interrupt the device. Someflags are automatically cleared when reading a port.

Interrupt flags are set even if the interrupts are not enabled (they arethe way peripherals signal to polling or interrupts).

And vice versa, many of the flags can be set from code, thuscausing invocation of an interrupt.

If more interrupts are pending at RETFIE then a new interrupt will bestarted. It is customary to check at the ISR first which flag caused the

interrupt (obvious).

Dont use MOVFF insider an ISR to modify an interrupt register (whywould you?)


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Logical View of High Priority Interrupts

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Logical View of All Interrupts


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External INT Interrupts

INT0, INT1, and INT2 are all interrupts assigned todigital I/O pins. Thus, to use them the correspondingTRIS(B) bits have to be set.

INT interrupts are edge (not level) triggered, thus achange must happen on the pins to trigger an interrupt.

Whether rising (default) or falling edge triggers theinterrupt is software (INTCON2.INTEDGx bits)selectable.

When triggered (like many other flags) the ISR shouldexplicitly clear the INTxIF flag.

They can all be used to wake the processor from a sleep

mode (more later). INT0 is always of high priority, the other two can be set.

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External PORTB Interrupts

Changes on PB4:PB7 can also cause interruptsbut are on the group of the bits not individual.(This leaves PB3 as the only PORTB pin withoutinterrupt capability)

Interrupt priority can be set.

When handling interrupt, PORTB should be read

and INTCON.RBIF should be cleared. Great e.g. for keyboard interfacing.


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INTCON

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INTCON2


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INTCON3

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PIR1


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PIR2

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PIR3


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PIE1

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PIE2


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PIE3

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IPR1


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IPR2

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IPR3


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RCON

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Interrupt Programming from Assembly

It really is just a quasi tedious job of setting theright bits in the right registers and org-ing thecode at the right place.

E.g.,

ORG 0000H

GOTO MAIN

ORG 0008H

GOTO HP_ISRORG 00018H

GOTO LP_ISR

HP_ISR ORG 200H

BTFSS INTCON, INT0IF

RETFIE 0x01

BTG PORTB, 7

BCF INTCON, INT0IF

RETFIE 0x01


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Interrupt Programming from C

We need to define functions that are for highpriority and low priority ISRs.

We need to make sure that our ISRs are in theright place.

We do not need to worry about contextswitching, the C compiler is going to make sureour registers are properly handled and variablesthat need saving are saved.

Interrupt handlers should start off with an if or aswitch-case complex to identify the source ofthe interrupt

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Defining ISRs in C

Defining functions that are for high priorityand low priority ISRs:

At the beginning of the program, have aprototype of all functions (including ISRs)

Use #pragma interrupt function_nameand#pragma interruptlow function_nameto tell

compiler that a function is an interruptfunction (so it can use proper RETFIEreturns and fast context switching)


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Placing ISRs in C

Make sure that our ISRs are in the right place.

At the beginning of the code insert gotoinstructions to the interrupt vectors

#pragma code My_Hi_Priority_Int = 0x0008

void My_Hi_Priority_Int(void)

{

_asm

GOTO chk_isr

_endasm}

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Interrupt Handling All in All (in C)

#include void My_ISR_High(void);void My_ISR_Low(void);#pragma code My_Hi_Priority_Int = 0x0008void My_Hi_Priority_Int(void) {

_asmGOTO My_ISR_High

_endasm }#pragma code My_Lo_Priority_Int = 0x00018void My_Hi_Priority_Int(void) {

_asmGOTO My_ISR_Low

_endasm }#pragma interrupt My_ISR_High

void My_ISR_High(void){

interrupt handling}#pragma interruptlow My_ISR_Lowvoid My_ISR_Low(void){

interrupt handling for low}


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Summary

Interrupts are a great way to handle peripheral attentionor external happenings.

Some of the most used interrupts are timers (later),external hardware, serial communications, and ADCready.

All interrupts in the PIC18 can be masked in a group orindividually.

We can have two levels of priorities, with an almost fullyconfigurable what interrupt belong to what levelrelationship.

Programming ISRs from C requires knowledge of howthe compiler is told about ISRs. (The sample providedhere is for the C18 compiler.)

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pic18 interrupt 2