PIC16(L)F1454/5/9 14/20-Pin, 8-Bit Flash USB Microcontroller with … · 2020. 9. 30. · PIC16(L)F145X DS40001639C-page 6 2012-2020 Microchip Technology Inc. TABLE 2: 14-PIN ALLOCATION

14/20-Pin, 8-Bit Flash USB Microcontroller with XLP Technology

PIC16(L)F1454/5/9

High-Performance RISC CPU:• C Compiler Optimized Architecture• Only 49 Instructions• 14 Kbytes Linear Program Memory Addressing• 1024 Bytes Linear Data Memory Addressing• Operating Speed:

- DC – 48 MHz clock input- DC – 83 ns instruction cycle- Selectable 3x or 4x PLL for specific frequencies

• Interrupt Capability with Automatic ContextSaving

• 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:- Two full 16-bit File Select Registers (FSRs)

capable of accessing both data or program memory

- FSRs can read program and data memory

Special Microcontroller Features:• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF145X)- 2.3V to 5.5V (PIC16F145X)

• Self-Programmable under Software Control• Power-on Reset (POR)• Power-up Timer (PWRT)• Programmable Brown-Out Reset (BOR)• Low-Power BOR (LPBOR)• Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s• Programmable Code Protection• In-Circuit Serial Programming™ (ICSP™) via Two

Pins• Enhanced Low-Voltage Programming (LVP)• Power-Saving Sleep mode• 128 Bytes High-Endurance Flash

- 100,000 write Flash endurance (minimum)

Universal Serial Bus (USB) Features:• Self-Tuning from USB Host

(eliminates need for external crystal)• USB V2.0 Compliant SIE• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)• Supports Control, Interrupt, Isochronous and Bulk

Transfers• Supports up to Eight Bidirectional Endpoints • 512-Byte Dual Access RAM for USB• Interrupt-on-Change (IOC) on D+/D- for USB Host

Detection• Configurable Internal Pull-up Resistors for use

with USB

Extreme Low-Power ManagementPIC16LF145X with XLP:• Sleep mode: 25 nA @ 1.8V, typical • Watchdog Timer Current: 290 nA @ 1.8V, typical• Timer1 Oscillator: 600 nA @ 32 kHz, typical• Operating Current: 25 A/MHz @ 1.8V, typical

Flexible Oscillator Structure:• 16 MHz Internal Oscillator Block:

- Factory calibrated to ±0.25%, typical- Software selectable frequency range from

16 MHz to 31 kHz- Tunable to 0.25% across temperature range- 48 MHz with 3x PLL

• 31 kHz Low-Power Internal Oscillator• Clock Switching with run from:

- Primary Oscillator- Secondary Oscillator (SOSC)- Internal Oscillator

• Clock Reference Output:- Clock Prescaler- CLKOUT

Analog Features(1):• Analog-to-Digital Converter (ADC):

- 10-bit resolution- Up to nine external channels- Two internal channels:

- Fixed Voltage Reference channel- DAC output channel

- Auto acquisition capability- Conversion available during Sleep

• Two Comparators:- Rail-to-rail inputs- Power mode control- Software controllable hysteresis

• Voltage Reference module:- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels• Up to One Rail-to-Rail Resistive 5-Bit DAC with

Positive Reference Selection

Note 1: Analog features are not available on PIC16(L)F1454 devices.

2012-2020 Microchip Technology Inc. DS40001639C-page 1

PIC16(L)F145X

Peripheral Features:• Up to 14 I/O Pins and Three Input-only Pins:

- High current sink/source 25 mA/25 mA- Individually programmable weak pull-ups- Individually programmable

Interrupt-On-Change (IOC) pins• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler• Enhanced Timer1:

- 16-bit timer/counter with prescaler- External Gate Input mode

• Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

• Two 10-bit PWM modules• Complementary Waveform Generator (CWG)(1):

- Up to four selectable signal sources- Selectable falling and rising edge dead-band

control- Polarity control- Up to four auto-shutdown sources- Multiple input sources: PWM, Comparators

• Master Synchronous Serial Port (MSSP) with SPI and I2C with:- 7-bit address masking- SMBus/PMBus™ compatibility

• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART):- RS-232, RS-485 and LIN compatible- Auto-baud detect- Auto-wake-up on Start

PIC16(L)F145X Family Types

Note 1: Not available on PIC16(L)F1454 devices.

Device

Dat

a Sh

eet I

ndex

Prog

ram

Mem

ory

Flas

h (w

ords

)

Dat

a SR

AM

(byt

es)

I/Os(

2)

10-b

it A

DC

(ch)

Com

para

tors

DA

C

Tim

ers

(8/1

6-bi

t)

PWM

EUSA

RT

MSS

P (I2

/SPI

)

CW

G

USB

Clo

ck R

efer

ence

Deb

ug(1

)

XLP

PIC16(L)F1454 (1) 8192 1024 11 — — — 2/1 2 1 1 — 1 1 I/H YPIC16(L)F1455 (1) 8192 1024 11 5 2 1 2/1 2 1 1 1 1 1 I/H YPIC16(L)F1459 (1) 8192 1024 17 9 2 1 2/1 2 1 1 1 1 1 I/H YNote 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header;

E - Emulation, Available using Emulation Header.2: Three pins are input-only.

Data Sheet Index: 1: DS41639 PIC16(L)F1454/5/9 Data Sheet, 14/20-Pin Flash, 8-Bit USB Microcontrollers.

Note: For other small form-factor package availability and marking information, please visitwww.microchip.com/packaging or contact your local sales office.

DS40001639C-page 2 2012-2020 Microchip Technology Inc.

http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en556972http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en556972http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en556972http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en556972

PIC16(L)F145X

FIGURE 1: 14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455

FIGURE 2: 16-PIN QFN/UQFN DIAGRAM FOR PIC16(L)F1454/1455

PDIP, SOIC, TSSOP

PIC

16(L

)F14

54PI

C16

(L)F

1455

1

234

14131211

567

1098

VDDRA5RA4

MCLR/VPP/RA3RC5RC4

RC3

VSSRA0/D+/ICSPDAT(1)

RA1/D-/ICSPCLK(1)

VUSB3V3RC0/ICSPDATRC1/ICSPCLKRC2

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.2: See Table 1 and Table 2 for location of all peripheral functions.

7 8

2

3

1

11

12

5

910

13141516

6

4

RA5

RA4

MCLR/VPP/RA3

RC

4

RC

3

ICSP

CLK

/RC

1

RC

2

RC0/ICSPDAT

RA0/D+/ICSPDAT(1)

VUSB3V3RA1/D-/ICSPCLK(1)

Vss

VDD

NC

RC5

NC

QFN, UQFN (4x4)

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.2: See Table 1 and Table 2 for location of all peripheral functions.

PIC16(L)F1454PIC16(L)F1455


PIC16(L)F145X

FIGURE 3: 20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1459

FIGURE 4: 20-PIN QFN/UQFN DIAGRAM FOR PIC16(L)F1459

PIC

16(L

)F14

59

1

234

14

131211

567

1098

VDDRA5RA4

MCLR/VPP/RA3RC5RC4

VSSRA0/D+/ICSPDAT(1)

RA1/D-/ICSPCLK(1)

VUSB3V3RC0/ICSPDATRC1/ICSPCLKRC2RC3

PDIP, SOIC, SSOP

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.2: See Table 3 for location of all peripheral functions.

18171615

2019

RC6RC7RB7

RB4RB5RB6

8 9

23

11415

16

10

11

6

1213

17181920

7

54

MCLR/VPP/RA3RC5RC4RC3RC6

RC

7R

B7

RB4

RB5

RB6

RC1/ICSPCLKRC0/ICSPDATVUSB3V3RA1/D-/ICSPCLK(1)

RA0

/D+/

ICSP

DAT

(1)

Vss

V DD

RA4

RA5

RC2

QFN, UQFN (4x4)

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.2: See Table 3 for location of all peripheral functions.

PIC16(L)F1459


PIC16(L)F145X

TABLE 1: 14-PIN ALLOCATION TABLE (PIC16(L)F1454)

I/O

14-P

in P

DIP

/SO

IC/T

SSO

P

16-P

in Q

FN/U

QFN

Tim

er

USB

EUSA

RT

PWM

MSS

P

Inte

rrup

t

Bas

ic

RA0 13 12 — D+ — — — IOC ICSPDAT(3)

RA1 12 11 — D- — — — IOC ICSPCLK(3)

RA3 4 3 T1G(2) — — — SS(2) IOC MCLRVPP

RA4 3 2 SOSCOT1G(1)

— — — SDO(2) IOC CLKOUTOSC2

CLKR(1)

RA5 2 1 SOSCIT1CKI

— — PWM2(2) — IOC CLKINOSC1

RC0 10 9 — — — — SCLSCK

— ICSPDAT

RC1 9 8 — — — — SDASDI

INT ICSPCLK

RC2 8 7 — — — — SDO(1) — —RC3 7 6 — — — PWM2(1) SS(1) — CLKR(2)

RC4 6 5 — — TXCK

— — — —

RC5 5 4 T0CKI — RXDT

PWM1 — — —

VDD 1 16 — — — — — — VDDVSS 14 13 — — — — — — VSS

VUSB3V3 11 10 — VUSB3V3 — — — — —Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.

2: Alternate location for peripheral pin function selected by the APFCON register.3: LVP support for PIC18(L)F1XK50 legacy designs.


PIC16(L)F145X


I/O

14-P

in P

DIP

/SO

IC/T

SSO

P

16-P

in Q

FN/U

QFN

AD

C

Ref

eren

ce

Com

para

tor

Tim

er

CW

G

USB

EUSA

RT

PWM

MSS

P

Inte

rrup

t

Bas

ic

RA0 13 12 — — — — — D+ — — — IOC ICSPDAT(3)

RA1 12 11 — — — — — D- — — — IOC ICSPCLK(3)

RA3 4 3 — — — T1G(2) — — — — SS(2) IOC MCLRVPP

RA4 3 2 AN3 — — SOSCOT1G(1)

— — — — SDO(2) IOC CLKOUTOSC2

CLKR(1)

RA5 2 1 — — — SOSCIT1CKI

— — — PWM2(2) — IOC CLKINOSC1

RC0 10 9 AN4 VREF+ C1IN+C2IN+

— — — — — SCLSCK

— ICSPDAT

RC1 9 8 AN5 — C1IN1-C2IN1-

— CWGFLT — — — SDASDI

INT ICSPCLK

RC2 8 7 AN6 DACOUT1 C1IN2-C2IN2-

— — — — — SDO(1) — —


— — — — PWM2(1) SS(1) — CLKR(2)

RC4 6 5 — — C1OUTC2OUT

— CWG1B — TXCK

— — — —

RC5 5 4 — — — T0CKI CWG1A — RXDT

PWM1 — — —

VDD 1 16 — — — — — — — — — — VDD

VSS 14 13 — — — — — — — — — — VSS

VUSB3V3 11 10 — — — — — VUSB3V3 — — — — —

Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register.3: LVP support for PIC18(L)F1XK50 legacy designs.


PIC16(L)F145X


I/O

20-P

in P

DIP

/SO

IC/S

SOP

20-P

in Q

FN/U

QFN

AD

C

Ref

eren

ce

Com

para

tor

Tim

er

CW

G

USB

EUSA

RT

PWM

MSS

P

Inte

rrup

t

Bas

ic

RA0 19 16 — — — — — D+ — — — IOC ICSPDAT(3)

RA1 18 15 — — — — — D- — — — IOC ICSPCLK(3)

RA2 — — — — — — — — — — — — —

RA3 4 1 — — — T1G(2) — — — — SS(2) IOC MCLRVPP

RA4 3 20 AN3 — — SOSCOT1G(1)

— — — — — IOC OSC2CLKOUTCLKR(1)

RA5 2 19 — — — SOSCIT1CKI

— — — — — IOC OSC1CLKIN

RB4 13 10 AN10 — — — — — — — SDASDI

IOC —

RB5 12 9 AN11 — — — — — RXDX

— — IOC —

RB6 11 8 — — — — — — — — SCLSCK

IOC —

RB7 10 7 — — — — — — TXCK

— — IOC —

RC0 16 13 AN4 VREF+ C1IN+C2IN+

— — — — — — — ICSPDAT

RC1 15 12 AN5 — C1IN1-C2IN1-

— CWGFLT — — — — INT ICSPCLK


— — — — — — — —


— — — — — — — CLKR(2)

RC4 6 3 — — C1OUTC2OUT

— CWG1B — — — — — —

RC5 5 2 — — — T0CKI CWG1A — — PWM1 — — —

RC6 8 5 AN8 — — — — — — PWM2 SS(1) — —

RC7 9 6 AN9 — — — — — — — SDO — —

VDD 1 18 — — — — — — — — — — VDD

VSS 20 17 — — — — — — — — — — VSS

VUSB3V3 17 14 — — — — — VUSB3V3 — — — — —



PIC16(L)F145X

Table of Contents1.0 Device Overview ........................................................................................................................................................................ 102.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 193.0 Memory Organization ................................................................................................................................................................. 214.0 Device Configuration .................................................................................................................................................................. 495.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 556.0 Resets ........................................................................................................................................................................................ 777.0 Reference Clock Module ............................................................................................................................................................ 858.0 Interrupts .................................................................................................................................................................................... 889.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 9910.0 Watchdog Timer (WDT) ........................................................................................................................................................... 10311.0 Flash Program Memory Control ............................................................................................................................................... 10812.0 I/O Ports ................................................................................................................................................................................... 12513.0 Interrupt-On-Change ................................................................................................................................................................ 13814.0 Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 only)......................................................................................................... 14415.0 Temperature Indicator Module (PIC16(L)F1455/9 only)........................................................................................................... 14616.0 Analog-to-Digital Converter (ADC) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 14817.0 Digital-to-Analog Converter (DAC) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 16318.0 Comparator Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 16719.0 Timer0 Module ......................................................................................................................................................................... 17620.0 Timer1 Module with Gate Control............................................................................................................................................. 17921.0 Timer2 Module ......................................................................................................................................................................... 19022.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 19423.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 24824.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 27725.0 Complementary Waveform Generator (CWG) Module

(PIC16(L)F1455/9 only) ............................................................................................................................................................. 28326.0 Universal Serial Bus (USB) ...................................................................................................................................................... 29827.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 32628.0 Instruction Set Summary .......................................................................................................................................................... 32829.0 Electrical Specifications............................................................................................................................................................ 34230.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 37131.0 Development Support............................................................................................................................................................... 37232.0 Packaging Information.............................................................................................................................................................. 376Appendix A: Data Sheet Revision History.......................................................................................................................................... 394The Microchip Web Site ..................................................................................................................................................................... 395Customer Change Notification Service .............................................................................................................................................. 395Customer Support .............................................................................................................................................................................. 395Product Identification System............................................................................................................................................................. 396


PIC16(L)F145X

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected]. We welcome your feedback.

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ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Website; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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PIC16(L)F1454/5/9

1.0 DEVICE OVERVIEWThe PIC16(L)F1454/5/9 are described within this datasheet. They are available in 14/20-pin packages.Figure 1-1 shows a block diagram of thePIC16(L)F1454/5/9 devices. Tables 1-2, 1-3 and 1-4show the pinout descriptions.Reference Table 1-1 for peripherals available perdevice.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC

16F1

454

PIC

16LF

1454

PIC

16F1

455

PIC

16LF

1455

PIC

16F1

459

PIC

16LF

1459

Analog-to-Digital Converter (ADC) ● ●Clock Reference ● ● ●Complementary Wave Generator (CWG) ● ●Digital-to-Analog Converter (DAC) ● ●Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)

● ● ●

Fixed Voltage Reference (FVR) ● ●Temperature Indicator ● ●Universal Serial Bus (USB) ● ● ●Comparators

C1 ● ●C2 ● ●

Master Synchronous Serial PortsMSSP1 ● ● ●

PWM ModulesPWM1 ● ● ●PWM2 ● ● ●

TimersTimer0 ● ● ●Timer1 ● ● ●Timer2 ● ● ●


PIC16(L)F1454/5/9

FIGURE 1-1: PIC16(L)F1454/5/9 BLOCK DIAGRAM

PORTC

Note 1: PIC16(L)F1455/9 only.2: PIC16(L)F1459 only.

CPU

ProgramFlash Memory

RAM

TimingGeneration

INTRCOscillator

MCLR

(Figure 2-1)

Timer2Timer1Timer0

PWM1 PWM2

PORTA

CWG1(1)

ADC10-Bit(1) FVR

(1)Temp.Indicator(1)

OSC1/CLKIN

OSC2/CLKOUT

MSSP1

C2(1)C1(1)

DAC(1)

PORTB(2)

EUSART

CLKRUSB


PIC16(L)F1454/5/9

TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION

Name Function Input TypeOutput Type Description

RA0/D+/ICSPDAT(3) RA0 TTL — General purpose input.D+ USB USB USB differential plus line.

ICSPDAT ST CMOS ICSP™ Data I/O.RA1/D-/ICSPCLK(3) RA1 TTL — General purpose input.

D- USB USB USB differential minus line.ICSPCLK ST — ICSP Programming Clock.

RA3/VPP/T1G(2)/SS(2)/MCLR RA3 TTL — General purpose input with IOC and WPU.VPP HV — Programming voltage.T1G ST — Timer1 Gate input.SS ST — Slave Select input.

MCLR ST — Master Clear with internal pull-up.RA4/SOSCO/CLKOUT/T1G(1)/SDO(2)/CLKR(1)/OSC2

RA4 TTL CMOS General purpose I/O.SOSCO XTAL XTAL Secondary Oscillator Connection.CLKOUT — CMOS FOSC/4 output.

T1G ST — Timer1 Gate input.SDO — CMOS SPI data output.CLKR — CMOS Clock reference output.OSC2 XTAL XTAL Primary Oscillator connection.

RA5/CLKIN/SOSCI/T1CKI/PWM2(2)/OSC1

RA5 TTL CMOS General purpose I/O.CLKIN CMOS — External clock input (EC mode).SOSCI XTAL XTAL Secondary Oscillator Connection.T1CKI ST — Timer1 clock input.PWM2 — CMOS PWM output.OSC1 XTAL XTAL Primary Oscillator Connection.

RC0/SCL/SCK/ICSPDAT RC0 TTL CMOS General purpose I/O.SCL I2C OD I2C clock.SCK ST CMOS SPI clock.

ICSPDAT ST CMOS ICSP™ Data I/O.RC1/SDA/SDI/INT/ICSPCLK RC1 TTL CMOS General purpose I/O.

SDA I2C OD I2C data input/output.SDI CMOS — SPI data input.INT ST — External input.

ICSPCLK ST — ICSP Programming Clock.RC2/SDO(1) RC2 TTL CMOS General purpose I/O.

SDO — CMOS SPI data output.RC3/PWM2(1)/SS(1)/CLKR(2) RC3 TTL CMOS General purpose I/O.

PWM2 — CMOS PWM output.SS ST — Slave Select input.

CLKR — CMOS Clock reference output.Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levelsUSB= USB Spec. specific input buffers and output drivers



PIC16(L)F1454/5/9

RC4/TX/CK RC4 TTL CMOS General purpose I/O.TX — CMOS USART asynchronous transmit.CK ST CMOS USART synchronous clock.

RC5/T0CKI/RX/DT/PWM1 RC5 TTL CMOS General purpose I/O.T0CKI ST — Timer0 clock input.

RX ST — USART asynchronous input.DT ST CMOS USART synchronous data.

PWM1 — CMOS PWM output.VDD VDD Power — Positive supply.VSS VSS Power — Ground reference.VUSB3V3 VUSB3V3 Power Power On F devices: Output of internal LDO regulator and positive

supply for USB transceiver and core logic.On LF devices: Power supply input pin, should be connected to VDD at PCB level.

TABLE 1-2: PIC16(L)F1454 PINOUT DESCRIPTION (CONTINUED)


Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levelsUSB= USB Spec. specific input buffers and output drivers



PIC16(L)F1454/5/9







MCLR ST — Master Clear with internal pull-up.RA4/AN3/SOSCO/CLKOUT/T1G(1)/SDO(2)/CLKR(1)/OSC2

RA4 TTL CMOS General purpose I/O.AN3 AN — A/D Channel input.

SOSCO XTAL XTAL Secondary Oscillator Connection.CLKOUT — CMOS FOSC/4 output.

T1G ST — Timer1 Gate input.SDO — CMOS SPI data output.CLKR — CMOS Clock reference output.OSC2 XTAL XTAL Primary Oscillator connection.

RA5/CLKIN/SOSCI/T1CKI/PWM2(2)/OSC1

RA5 TTL CMOS General purpose I/O.CLKIN CMOS — External clock input (EC mode).SOSCI XTAL XTAL Secondary Oscillator Connection.T1CKI ST — Timer1 clock input.PWM2 — CMOS PWM output.OSC1 XTAL XTAL Primary Oscillator Connection.

RC0/AN4/VREF+/C1IN+/C2IN+/SCL/SCK/ICSPDAT

RC0 TTL CMOS General purpose I/O.AN4 AN — A/D Channel input.

VREF+ AN — Positive Voltage Reference input.C1IN+ AN — Comparator positive input.C2IN+ AN — Comparator positive input.SCL I2C OD I2C clock.SCK ST CMOS SPI clock.

ICSPDAT ST CMOS ICSP™ Data I/O.Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levelsUSB= USB Spec. specific input buffers and output drivers



PIC16(L)F1454/5/9

RC1/AN5/C1IN1-/C2IN1-/CWGFLT/SDA/SDI/INT/ICSPCLK


C1IN1- AN — Comparator negative input.C2IN1- AN — Comparator negative input.

CWGFLT ST — Complementary Waveform Generator Fault input.SDA I2C OD I2C data input/output.SDI CMOS — SPI data input.INT ST — External input.

ICSPCLK ST — ICSP™ Programming Clock.RC2/AN6/DACOUT1/C1IN2-/C2IN2-/SDO(1)


DACOUT1 — AN Digital-to-Analog Converter output.C1IN2- AN — Comparator negative input.C2IN2- AN — Comparator negative input.SDO — CMOS SPI data output.

RC3/AN7/DACOUT2/C1IN3-/C2IN3-/PWM2(1)/SS(1)/CLKR(2)


DACOUT2 — AN Digital-to-Analog Converter output.C1IN3- AN — Comparator negative input.C2IN3- AN — Comparator negative input.PWM2 — CMOS PWM output.

CLC2IN0 ST — Configurable Logic Cell source input.CLKR — CMOS Clock reference output.

RC4/C1OUT/C2OUT/CWG1B/TX/CK

RC4 TTL CMOS General purpose I/O.C1OUT — CMOS Comparator output.C2OUT — CMOS Comparator output.CWG1B — CMOS CWG complementary output.

TX — CMOS USART asynchronous transmit.CK ST CMOS USART synchronous clock.

RC5/T0CKI/CWG1A/RX/DT/PWM1

RC5 TTL CMOS General purpose I/O.T0CKI ST — Timer0 clock input.

CWG1A — CMOS CWG complementary output.RX ST — USART asynchronous input.DT ST CMOS USART synchronous data.

PWM1 — CMOS PWM output.VDD VDD Power — Positive supply.VSS VSS Power — Ground reference.VUSB3V3 VUSB3V3 Power Power On F devices: Output of internal LDO regulator and positive

supply for USB transceiver and core logic.On LF devices: Power supply input pin, should be connected to VDD at PCB level.



Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levelsUSB= USB Spec. specific input buffers and output drivers



PIC16(L)F1454/5/9







MCLR ST — Master Clear with internal pull-up.RA4/AN3/SOSCO/CLKOUT/T1G(1)/CLKR(1)/OSC2

RA4 TTL CMOS General purpose I/O.AN3 AN — A/D Channel input.

SOSCO XTAL XTAL Secondary Oscillator Connection.CLKOUT — CMOS FOSC/4 output.

T1G ST — Timer1 Gate input.CLKR — CMOS Clock reference output.OSC2 XTAL XTAL Primary Oscillator connection.

RA5/CLKIN/SOSCI/T1CKI/OSC1

RA5 TTL CMOS General purpose I/O.CLKIN CMOS — External clock input (EC mode).SOSCI XTAL XTAL Secondary Oscillator Connection.T1CKI ST — Timer1 clock input.OSC1 XTAL XTAL Primary Oscillator Connection.

RB4/AN10/SDA/SDI RB4 TTL CMOS General purpose I/O.AN10 AN — A/D Channel input.SDA I2C OD I2C data input/output.SDI CMOS — SPI data input.

RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O.AN11 AN — A/D Channel input.RX ST — USART asynchronous input.DT ST CMOS USART synchronous data.

RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.SCL I2C OD I2C clock.SCK ST CMOS SPI clock.

RB7/TX/CK RB7 TTL CMOS General purpose I/O.TX — CMOS USART asynchronous transmit.CK ST CMOS USART synchronous clock.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levelsUSB= USB Spec. specific input buffers and output drivers



PIC16(L)F1454/5/9

RC0/AN4/VREF+/C1IN+/C2IN+/ICSPDAT


VREF+ AN — Positive Voltage Reference input.C1IN+ AN — Comparator positive input.C2IN+ AN — Comparator positive input.

ICSPDAT ST CMOS ICSP™ Data I/O.RC1/AN5/C1IN1-/C2IN1-/CWGFLT/INT/ICSPCLK


C1IN1- AN — Comparator negative input.C2IN1- AN — Comparator negative input.

CWGFLT ST — Complementary Waveform Generator Fault input.INT ST — External input.

ICSPCLK ST — ICSP Programming Clock.RC2/AN6/DACOUT1/C1IN2-/C2IN2-


DACOUT1 — AN Digital-to-Analog Converter output.C1IN2- AN — Comparator negative input.C2IN2- AN — Comparator negative input.

RC3/AN7/DACOUT2/C1IN3-/C2IN3-/CLKR(2)


DACOUT2 — AN Digital-to-Analog Converter output.C1IN3- AN — Comparator negative input.C2IN3- AN — Comparator negative input.CLKR — CMOS Clock reference output.

RC4/C1OUT/C2OUT/CWG1B

RC4 TTL CMOS General purpose I/O.C1OUT — CMOS Comparator output.C2OUT — CMOS Comparator output.CWG1B — CMOS CWG complementary output.

RC5/T0CKI/CWG1A/PWM1 RC5 TTL CMOS General purpose I/O.T0CKI ST — Timer0 clock input.

CWG1A — CMOS CWG complementary output.PWM1 — CMOS PWM output.

RC6/AN8/SS(1)/PWM2 RC6 TTL CMOS General purpose I/O.AN8 AN — A/D Channel input.SS ST — Slave Select input.

PWM2 — CMOS PWM output.RC7/AN9/SDO RC7 TTL CMOS General purpose I/O.

AN9 AN — A/D Channel input.SDO — CMOS SPI data output.

VDD VDD Power — Positive supply.VSS VSS Power — Ground reference.






PIC16(L)F1454/5/9

VUSB3V3 VUSB3V3 Power Power On F devices: Output of internal LDO regulator and positive supply for USB transceiver and core logic.On LF devices: Power supply input pin, should be connected to VDD at PCB level.






PIC16(L)F1454/5/9

2.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, Indirect, and

Relative Addressing modes are available. Two FileSelect Registers (FSRs) provide the ability to readprogram and data memory.• Automatic Interrupt Context Saving• 16-level Stack with Overflow and Underflow• File Select Registers• Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

Direct Addr 7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALUInstructionDecode &

Control

TimingGeneration

OSC1/CLKIN

OSC2/CLKOUT

8

8

12

3

InternalOscillator

Block

ConfigurationData Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W Reg

InstructionDecode &

Control

TimingGeneration

8

8

3

InternalOscillator

Block

Configuration 15 Data Bus 8

14ProgramBus

Instruction Reg

Program Counter

16-Level Stack(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

IndirectAddr

FSR0 Reg

STATUS Reg

MUX

ALUInstruction

Decode andControl

TimingGeneration

8

8

3

InternalOscillator

Block

Configuration

FlashProgramMemory

RAM

FSR regFSR regFSR1 Reg15

15

MU

X

15

Program MemoryRead (PMR)

12

FSR regFSR regBSR Reg

5

Power-upTimer

Power-onReset

WatchdogTimer

VDD

Brown-outReset

VSSVDD VSSVDD VSS


PIC16(L)F1454/5/9

2.1 Automatic Interrupt Context

SavingDuring interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 8.5 “Automatic Context Saving”,for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have an external stack memory 15 bitswide and 16 words deep. A Stack Overflow or Under-flow will set the appropriate bit (STKOVF or STKUNF)in the PCON register, and if enabled will cause a soft-ware Reset. See section Section 3.5 “Stack” for moredetails.

2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one Data Pointer for all memory. When anFSR points to program memory, there is one additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.6 “Indirect Addressing” for more details.

2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. SeeSection 28.0 “Instruction Set Summary” for moredetails.


PIC16(L)F1454/5/9

3.0 MEMORY ORGANIZATIONThese devices contain the following types of memory: • Program Memory

- Configuration Words- Device ID- User ID- Flash Program Memory

• Data Memory- Core Registers- Special Function Registers- Dual-Port General Purpose RAM- General Purpose RAM- Common RAM

The following features are associated with access andcontrol of program memory and data memory:• PCL and PCLATH• Stack• Indirect Addressing

3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit programcounter capable of addressing a 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented. Accessing a location above theseboundaries will cause a wrap-around within theimplemented memory space. The Reset vector is at0000h and the interrupt vector is at 0004h (SeeFigure 3-1).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words)Last Program Memory

AddressHigh-Endurance Flash

Memory Address Range (1)

PIC16F1454PIC16LF1454 8,192 1FFFh 1F80h-1FFFh



Note 1: High-endurance Flash applies to low byte of each address in the range.


PIC16(L)F1454/5/9

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1454/5/9

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro-gram memory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.

3.1.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to cre-ate such a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim-ple to implement. If the code must remain portable withprevious generations of microcontrollers, then the BRWinstruction is not available so the older table readmethod must be used.

PC

15

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chipProgramMemory

Page 007FFh

Rollover to Page 0

0800h

0FFFh1000h

7FFFh

Page 1

Rollover to Page 3

Page 2

Page 3

17FFh1800h

1FFFh2000h

CALL, CALLW RETURN, RETLW

Interrupt, RETFIE

constantsBRW ;Add Index in W to

;program counter to;select data

RETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function;… LOTS OF CODE…MOVLW DATA_INDEXcall constants;… THE CONSTANT IS IN W


PIC16(L)F1454/5/9

3.1.1.2 Indirect Read with FSRThe program memory can be accessed as data bysetting bit 7 of the FSRxH register and reading thematching INDFx register. The MOVIW instruction willplace the lower eight bits of the addressed word in theW register. Writes to the program memory cannot beperformed via the INDF registers. Instructions thataccess the program memory via the FSR require oneextra instruction cycle to complete. Example 3-2demonstrates accessing the program memory via anFSR.The High directive will set bit if a label points to alocation in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR

constantsRETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function;… LOTS OF CODE…MOVLW LOW constantsMOVWF FSR1LMOVLW HIGH constantsMOVWF FSR1HMOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W


PIC16(L)F1454/5/9

3.2 Data Memory OrganizationThe data memory is partitioned in 32 memory bankswith 128 bytes in a bank. Each bank consists of(Figure 3-2):• 12 core registers• 20 Special Function Registers (SFR)• Up to 80 bytes of General Purpose RAM (GPR)• Up to 80 bytes of Dual-Port General Purpose

RAM (DPR)• 16 bytes of common RAMThe active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as ‘0’. All data memory can beaccessed either directly (via instructions that use thefile registers) or indirectly via the two File SelectRegisters (FSR). See Section 3.6 “IndirectAddressing” for more information.Data memory uses a 12-bit address. The upper five bitsof the address define the Bank address and the lowerseven bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation. The core registers occupythe first 12 addresses of every data memory bank(addresses x00h/x08h through x0Bh/x8Bh). Theseregisters are listed below in Table 3-2. For detailedinformation, see Table 3-11.

TABLE 3-2: CORE REGISTERS

Addresses BANKxx00h or x80h INDF0x01h or x81h INDF1x02h or x82h PCLx03h or x83h STATUSx04h or x84h FSR0Lx05h or x85h FSR0Hx06h or x86h FSR1Lx07h or x87h FSR1Hx08h or x88h BSRx09h or x89h WREGx0Ah or x8Ah PCLATHx0Bh or x8Bh INTCON


PIC16(L)F1454/5/9

3.2.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:• the arithmetic status of the ALU• the Reset statusThe STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras ‘000u u1uu’ (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits (Refer to Section 28.0“Instruction Set Summary”).

3.3 Register Definitions: Status

Note 1: The C and DC bits operate as Borrowand Digit Borrow out bits, respectively, insubtraction.

REGISTER 3-1: STATUS: STATUS REGISTERU-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u— — — TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-Down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the 4th low-order bit of the result occurred0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.


PIC16(L)F1454/5/9

3.3.1 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The Special FunctionRegisters occupy the 20 bytes after the core registers ofevery data memory bank (addresses x0Ch/x8Chthrough x1Fh/x9Fh). The registers associated with theoperation of the peripherals are described in the appro-priate peripheral chapter of this data sheet.

3.3.2 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank. The Special Function Registers occupy the 20bytes after the core registers of every data memorybank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.3.2.1 Linear Access to GPRThe general purpose RAM can be accessed in anon-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section 3.6.2“Linear Data Memory” for more information.Refer to Table 3-3 for Dual Port and USB addressinginformation.

3.3.3 DUAL-PORT RAMPart of the data memory is mapped to a special dualaccess RAM. When the USB module is disabled, theGPRs in these banks are used like any other GPR inthe data memory space.When the USB module is enabled, the memory in thesebanks is allocated as buffer RAM for USB operation.This area is shared between the microcontroller coreand the USB Serial Interface Engine (SIE) and is usedto transfer data directly between the two.It is theoretically possible to use the areas of USB RAMthat are not allocated as USB buffers for normalscratchpad memory or other variable storage. In practice,the dynamic nature of buffer allocation makes this risky atbest. Additional information on USB RAM and bufferoperation is provided in Section 26.0 “Universal SerialBus (USB)”.

3.3.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.

TABLE 3-3: DUAL PORT RAM ADDRESSINGPort 0 Port 1

CPU Banked Address CPU Linear Address USB Banked Address USB Linear Address020 - 06F 2000 - 204F 020 - 06F 2000 - 204F0A0 - 0EF 2050 - 209F 0A0 - 0EF 2050 - 209F120 - 16F 20A0 - 20EF 120 - 16F 20A0 - 20EF1A0 - 1EF 20F0 - 213F 1A0 - 1EF 20F0 - 213F220 - 26F 2140 - 218F 220 - 26F 2140 - 218F2A0 - 2EF 2190 - 21DF 2A0 - 2EF 2190 - 21DF320 - 32F 21E0 - 21EF 320 - 32F 21E0 - 21EF370 - 37F (1) 370 - 37F (1)

Note 1: Accessible from banked memory only.


PIC16(L)F1454/5/9

FIGURE 3-2: BANKED MEMORY

PARTITIONING 3.3.5 DEVICE MEMORY MAPSThe memory maps for PIC16(L)F1454/5/9 are asshown in Table 3-8 and Table 3-9.

0Bh0Ch

1Fh20h

6Fh70h

7Fh

00h

Common RAM(16 bytes)

Dual Port RAM(80 bytes maximum)

Core Registers(12 bytes)

Special Function Registers(20 bytes maximum)

Memory Region7-bit Bank Offset

(1)

General Purpose RAM(80 bytes maximum)

OR

Note 1: If the USB module is disabled, data memory is GPR. If enabled, data memory can be DPR. Refer to Memory Map for RAM type details.


PIC16(L)F1454/5/9

DS40001639C

-page 28

2012-2020 Microchip Technology Inc.

BANK 6 BANK 7300h

Core Registers (Table 3-2)

380hCore Registers

(Table 3-2)

30Bh 38Bh30Ch — 38Ch —30Dh — 38Dh —30Eh — 38Eh —30Fh — 38Fh —310h — 390h —311h — 391h IOCAP312h — 392h IOCAN313h — 393h IOCAF314h — 394h —315h — 395h —316h — 396h —317h — 397h —318h — 398h —319h — 399h —31Ah — 39Ah CLKRCON31Bh — 39Bh CRCON31Ch — 39Ch —31Dh — 39Dh —31Eh — 39Eh —31Fh — 39Fh —320h Dual-Port

GeneralPurposeRegister16Bytes

3A0h

GeneralPurposeRegister80 Bytes

32Fh330h General

PurposeRegister64 Bytes36Fh 3EFh

370hCommon RAM

(Accesses70h – 7Fh)

3F0hCommon RAM


37Fh 3FFh

TABLE 3-4: PIC16(L)F1454 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

000hCore Registers

(Table 3-2)

080hCore Registers

(Table 3-2)

100hCore Registers

(Table 3-2)

180hCore Registers

(Table 3-2)

200hCore Registers

(Table 3-2)

280hCore Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch —00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh —00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh —00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh —010h — 090h — 110h — 190h — 210h — 290h —011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSP1BUF 291h —012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSP1ADD 292h —013h — 093h — 113h — 193h PMDATL 213h SSP1MSK 293h —014h — 094h — 114h — 194h PMDATH 214h SSP1STAT 294h —015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSP1CON1 295h —016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h —017h TMR1H 097h WDTCON 117h — 197h VREGCON 217h SSP1CON3 297h —018h T1CON 098h OSCTUNE 118h — 198h — 218h — 298h —019h T1GCON 099h OSCCON 119h — 199h RCREG 219h — 299h —01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah —01Bh PR2 09Bh — 11Bh — 19Bh SPBRG 21Bh — 29Bh —01Ch T2CON 09Ch — 11Ch — 19Ch SPBRGH 21Ch — 29Ch —01Dh — 09Dh — 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh —01Eh — 09Eh — 11Eh — 19Eh TXSTA 21Eh — 29Eh —01Fh — 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh —020h

Dual-PortGeneralPurposeRegister80 Bytes

0A0h


120h


1A0h


220h


2A0h


0EFh06Fh 16Fh 1EFh 26Fh 2EFh070h

Dual-PortCommon RAM

0F0hCommon RAM


170hCommon RAM


1F0hCommon RAM


270hCommon RAM


2F0hCommon RAM


07Fh 0FFh 17Fh 1FFh 27Fh 2FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

2012-2020 M

icrochip Technology Inc.D

S40001639C-page 29

PIC16(L)F1454/5/9

TABANK 6 BANK 7

00Core Registers

(Table 3-2)

380hCore Registers

(Table 3-2)

00 38Bh00 — 38Ch —00 — 38Dh —00 — 38Eh —00 — 38Fh —01 — 390h —01 — 391h IOCAP01 — 392h IOCAN01 — 393h IOCAF01 — 394h —01 — 395h —01 — 396h —01 — 397h —01 — 398h —01 — 399h —01 — 39Ah CLKRCON01 — 39Bh CRCON01 — 39Ch —01 — 39Dh —01 — 39Eh —01 — 39Fh —02 Dual-Port


3A0h

GeneralPurposeRegister80 BytesGeneral

PurposeRegister64 Bytes06 3EFh

07Common RAM


3F0hCommon RAM


07 3FFh

Le

BLE 3-5: PIC16(L)F1455 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

0hCore Registers

(Table 3-2)

080hCore Registers

(Table 3-2)

100hCore Registers

(Table 3-2)

180hCore Registers

(Table 3-2)

200hCore Registers

(Table 3-2)

280hCore Registers

(Table 3-2)

300h

Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30BhCh PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30ChDh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30DhEh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh — 30EhFh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh0h — 090h — 110h — 190h — 210h — 290h — 310h1h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h — 311h2h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h — 312h3h — 093h — 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h — 313h4h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 314h5h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h — 315h6h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h7h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 317h8h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h — 318h9h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h — 319hAh TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah — 31AhBh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh — 29Bh — 31BhCh T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31ChDh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31DhEh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31EhFh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh0h


0A0h


120h


1A0h


220h


2A0h


320h

0EFh

32Fh330h

Fh 16Fh 1EFh 26Fh 2EFh 36Fh0h

Dual-PortCommon RAM

0F0hCommon RAM


170hCommon RAM


1F0hCommon RAM


270hCommon RAM


2F0hCommon RAM


370h

Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh

gend: = Unimplemented data memory locations, read as ‘0’.

PIC16(L)F1454/5/9

DS40001639C

-page 30


BANK 6 BANK 700h


380hCore Registers

(Table 3-2)

0Bh 38Bh0Ch — 38Ch —0Dh — 38Dh —0Eh — 38Eh —0Fh — 38Fh —10h — 390h —11h — 391h IOCAP12h — 392h IOCAN13h — 393h IOCAF14h — 394h IOCBP15h — 395h IOCBN16h — 396h IOCBF17h — 397h —18h — 398h —19h — 399h —1Ah — 39Ah CLKRCON1Bh — 39Bh CRCON1Ch — 39Ch —1Dh — 39Dh —1Eh — 39Eh —1Fh — 39Fh —20h Dual-Port


3A0h


2Fh30h General

PurposeRegister64 Bytes6Fh 3EFh

70hCommon RAM


3F0hCommon RAM


7Fh 3FFh

TABLE 3-6: PIC16(L)F1459 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

000hCore Registers

(Table 3-2)

080hCore Registers

(Table 3-2)

100hCore Registers

(Table 3-2)

180hCore Registers

(Table 3-2)

200hCore Registers

(Table 3-2)

280hCore Registers

(Table 3-2)

3

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 300Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 300Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 300Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh — 28Eh — 300Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 3010h — 090h — 110h — 190h — 210h — 290h — 3011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h — 3012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h — 3013h — 093h — 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h — 3014h — 094h — 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h — 3015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h — 3016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 3017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 3018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h — 3019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h — 301Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah — 301Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh — 29Bh — 301Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 301Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 301Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 301Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 3020h


0A0h


120h


1A0h


220h


2A0h


3

33

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 3070h

Dual-PortCommon RAM

0F0hCommon RAM


170hCommon RAM


1F0hCommon RAM


270hCommon RAM


2F0hCommon RAM


3

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 3


2012-2020 M


S40001639C-page 31

PIC16(L)F1454/5/9

TABANK 14 BANK 15

40

40


780h

78Bh


40 — 78Ch —40 — 78Dh —40 — 78Eh —40 — 78Fh —41 — 790h —41 — 791h —41 — 792h —41 — 793h —41 — 794h —41 — 795h —41 — 796h —41 — 797h —41 — 798h —41 — 799h —41 — 79Ah —41 — 79Bh —41 — 79Ch —41 — 79Dh —41 — 79Eh —41 — 79Fh —42

UnimplementedRead as ‘0’

7A0h


46 7EFh47

Common RAM(Accesses70h – 7Fh)

7F0hCommon RAM


47 7FFh

BANK 22 BANK 2380

80


B80h

B8Bh


80Unimplemented

Read as ‘0’

B8ChUnimplemented

Read as ‘0’86 BEFh87


BF0hCommon RAM


87 BFFhLe

BLE 3-7: PIC16(L)F1454 MEMORY MAP, BANK 8-23BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13

0h

Bh


480h

48Bh


500h

50Bh


580h

58Bh


600h

60Bh


680h

68Bh


700h

70BhCh — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70ChDh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70DhEh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70EhFh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh0h — 490h — 510h — 590h — 610h — 690h — 710h1h — 491h — 511h — 591h — 611h PWM1DCL 691h — 711h2h — 492h — 512h — 592h — 612h PWM1DCH 692h — 712h3h — 493h — 513h — 593h — 613h PWM1CON 693h — 713h4h — 494h — 514h — 594h — 614h PWM2DCL 694h — 714h5h — 495h — 515h — 595h — 615h PWM2DCH 695h — 715h6h — 496h — 516h — 596h — 616h PWM2CON 696h — 716h7h — 497h — 517h — 597h — 617h — 697h — 717h8h — 498h — 518h — 598h — 618h — 698h — 718h9h — 499h — 519h — 599h — 619h — 699h — 719hAh — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71AhBh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71BhCh — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71ChDh — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71DhEh — 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71EhFh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh0h


4A0h


520h


5A0h


620h GeneralPurposeRegister48 Bytes

6A0h


720h

64Fh650h Unimplemented

Read as ‘0’Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh0h


4F0hCommon RAM


570hCommon RAM


5F0hCommon RAM


670hCommon RAM


6F0hCommon RAM


770h

Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 210h

Bh

Core Registers (Table 3-2 )

880h

88Bh


900h

90Bh


980h

98Bh


A00h

A0Bh


A80h

A8Bh


B00h

B0BhCh


88ChUnimplemented

Read as ‘0’

90ChUnimplemented

Read as ‘0’

98ChUnimplemented

Read as ‘0’

A0ChUnimplemented

Read as ‘0’

A8ChUnimplemented

Read as ‘0’

B0Ch

Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh0h


8F0hCommon RAM


970hCommon RAM


9F0hCommon RAM


A70hCommon RAM


AF0hCommon RAM


B70h

Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fhgend: = Unimplemented data memory locations, read as ‘0’.

PIC16(L)F1454/5/9

DS40001639C

-page 32


BANK 14 BANK 1500h

0Bh


780h

78Bh


0Ch — 78Ch —0Dh — 78Dh —0Eh — 78Eh —0Fh — 78Fh —10h — 790h —11h — 791h —12h — 792h —13h — 793h —14h — 794h —15h — 795h —16h — 796h —17h — 797h —18h — 798h —19h — 799h —1Ah — 79Ah —1Bh — 79Bh —1Ch — 79Ch —1Dh — 79Dh —1Eh — 79Eh —1Fh — 79Fh —20h


7A0h


6Fh 7EFh70h


7F0hCommon RAM


7Fh 7FFh

BANK 22 BANK 2300h

0Bh


B80h

B8Bh


0ChUnimplemented

Read as ‘0’

B8ChUnimplemented

Read as ‘0’6Fh BEFh70h


BF0hCommon RAM


7Fh BFFh

TABLE 3-8: PIC16(L)F1455/9 MEMORY MAP, BANK 8-23BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13

400h

40Bh


480h

48Bh


500h

50Bh


580h

58Bh


600h

60Bh


680h

68Bh


7

740Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 740Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 740Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 740Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 7410h — 490h — 510h — 590h — 610h — 690h — 7411h — 491h — 511h — 591h — 611h PWM1DCL 691h CWG1DBR 7412h — 492h — 512h — 592h — 612h PWM1DCH 692h CWG1DBF 7413h — 493h — 513h — 593h — 613h PWM1CON 693h CWG1CON0 7414h — 494h — 514h — 594h — 614h PWM2DCL 694h CWG1CON1 7415h — 495h — 515h — 595h — 615h PWM2DCH 695h CWG1CON2 7416h — 496h — 516h — 596h — 616h PWM2CON 696h — 7417h — 497h — 517h — 597h — 617h — 697h — 7418h — 498h — 518h — 598h — 618h — 698h — 7419h — 499h — 519h — 599h — 619h — 699h — 741Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 741Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 741Ch — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 741Dh — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 741Eh — 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 741Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 7420h


4A0h


520h


5A0h


620h GeneralPurposeRegister48 Bytes

6A0h


7

64Fh650h Unimplemented

Read as ‘0’46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 7470h


4F0hCommon RAM


570hCommon RAM


5F0hCommon RAM


670hCommon RAM


6F0hCommon RAM


7

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 7


80Bh

Core Registers (Table 3-2 )

880h

88Bh


900h

90Bh


980h

98Bh


A00h

A0Bh


A80h

A8Bh


B

B80Ch


88ChUnimplemented

Read as ‘0’

90ChUnimplemented

Read as ‘0’

98ChUnimplemented

Read as ‘0’

A0ChUnimplemented

Read as ‘0’

A8ChUnimplemented

Read as ‘0’

B

86Fh 8EFh 96Fh 9EFh A6Fh AEFh B870h


8F0hCommon RAM


970hCommon RAM


9F0hCommon RAM


A70hCommon RAM


AF0hCommon RAM


B

87Fh 8FFh 97Fh 9FFh A7Fh AFFh BLegend: = Unimplemented data memory locations, read as ‘0’.

2012-2020 M


S40001639C-page 33

PIC16(L)F1454/5/9

TA

Le

BANK 30 BANK 31C

C

00h

Bh


F80h

F8Bh


C Ch — F8Ch

See Table 3-10 for register map-

ping details

C Dh — F8DhC Eh — F8EhC Fh — F8FhC 10h — F90hC 11h — F91hC 12h — F92hC 13h — F93hC 14h — F94hC 15h — F95hC 16h — F96hC 17h — F97hC 18h — F98hC 19h — F99hC Ah — F9AhC Bh — F9BhC Ch — F9ChC Dh — F9DhC Eh — F9EhC Fh — F9FhC 20h


FA0h

C Fh FEFhC 70h


FF0hCommon RAM


C Fh FFFh

BLE 3-9: PIC16(L)F1454/5/9 MEMORY MAP, BANK 24-31

gend: = Unimplemented data memory locations, read as ‘0’.


0Bh


C80h

C8Bh


D00h

D0Bh


D80h

D8Bh


E00h

E0Bh


E80h

E8Bh


F

F00Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F00Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F00Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh UCON F00Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh USTAT F010h — C90h — D10h — D90h — E10h — E90h UIR F11h — C91h — D11h — D91h — E11h — E91h UCFG F12h — C92h — D12h — D92h — E12h — E92h UIE F13h — C93h — D13h — D93h — E13h — E93h UEIR F14h — C94h — D14h — D94h — E14h — E94h UFRMH F15h — C95h — D15h — D95h — E15h — E95h UFRML F16h — C96h — D16h — D96h — E16h — E96h UADDR F17h — C97h — D17h — D97h — E17h — E97h UEIE F18h — C98h — D18h — D98h — E18h — E98h UEP0 F19h — C99h — D19h — D99h — E19h — E99h UEP1 F1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah UEP2 F11Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh UEP3 F11Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch UEP4 F11Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh UEP5 F11Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh UEP6 F11Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh UEP7 F120h


CA0h


D20h


DA0h


E20h


EA0h


F

6Fh CEFh D6Fh DEFh E6Fh EEFh F670h


CF0hCommon RAM


D70hCommon RAM


DF0hCommon RAM


E70hCommon RAM


EF0hCommon RAM


F

FFh CFFh D7Fh DFFh E7Fh EFFh F7

PIC16(L)F1454/5/9

TABLE 3-10: PIC16(L)F1454/5/9 MEMORY

MAP, BANK 30-31

Bank 31F8Ch

FE3h


FE4h STATUS_SHADFE5h WREG_SHADFE6h BSR_SHADFE7h PCLATH_SHADFE8h FSR0L_SHADFE9h FSR0H_SHADFEAh FSR1L_SHADFEBh FSR1H_SHADFECh —FEDh STKPTRFEEh TOSLFEFh TOSH



PIC16(L)F1454/5/9

3.3.6 CORE FUNCTION REGISTERS

SUMMARYThe Core Function registers listed in Table 3-11 can beaddressed from any Bank.

TABLE 3-11: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue on all other Resets

Bank 0-31x00h or x80h INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x01h or x81h INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x02h or x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h or x83h STATUS — — — TO PD Z DC C ---1 1000 ---q quuu

x04h or x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h or x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h or x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h or x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h or x88h BSR — — — BSR ---0 0000 ---0 0000

x09h or x89h WREG Working Register 0000 0000 uuuu uuuu

x0Ah or x8Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh or x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’.


PIC16(L)F1454/5/9

on er ts

-xx---xxx

-0000-

uuuuuuuuuu-uxuu

000111000

------111

-0000-

111quu110uuu100-qquuuuuu000-00---s ‘0’.

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value onPOR, BOR

Valueall othRese

Bank 000Ch PORTA — — RA5 RA4 RA3 — RA1 RA0 --xx x-xx --xx x00Dh PORTB(1) RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx -00Eh PORTC RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx x00Fh — Unimplemented — —

010h — Unimplemented — —

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 0000 0-00 0000 0012h PIR2 OSFIF C2IF C1IF — BCL1IF USBIF ACTIF — 000- 000- 000- 0013h — Unimplemented — —


015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu u016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu u017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu u018h T1CON TMR1CS T1CKPS T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu u019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONET1GVAL T1GSS 0000 0x00 uuuu u

01Ah TMR2 Timer2 Module Register 0000 0000 0000 001Bh PR2 Timer2 Period Register 1111 1111 1111 101Ch T2CON — T2OUTPS TMR2ON T2CKPS -000 0000 -000 001Dh — Unimplemented — —

01Eh — Unimplemented — —

01Fh — Unimplemented — —

Bank 108Ch TRISA — — TRISA5 TRISA4 —(2) — —(2) —(2) --11 ---- --11 -08Dh TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 -08Eh TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 108Fh — Unimplemented — —


091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 0000 0-00 0000 0092h PIE2 OSFIE C2IE C1IE — BCL1IE USBIE ACTIE — 000- 000- 000- 0093h — Unimplemented — —


095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 1111 1111 1111 1096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q q097h WDTCON — — WDTPS SWDTEN --01 0110 --01 0098h OSCTUNE — TUN -000 0000 -uuu u099h OSCCON SPLLEN SPLLMULT IRCF SCS 0011 1100 0011 109Ah OSCSTAT SOSCR PLLRDY OSTS HFIOFR — — LFIOFR HFIOFS 00q0 --00 qqqq -09Bh ADRESL(2) A/D Result Register Low xxxx xxxx uuuu u09Ch ADRESH(2) A/D Result Register High xxxx xxxx uuuu u09Dh ADCON0(2) — CHS GO/DONE ADON -000 0000 -000 009Eh ADCON1(2) ADFM ADCS — — ADPREF 0000 --00 0000 -09Fh ADCON2(2) — TRIGSEL — — — — -000 ---- -000 -Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read aNote 1: PIC16(L)F1459 only.

2: PIC16(L)F1455/9 only.3: Unimplemented, read as ‘1’.


PIC16(L)F1454/5/9

------uuu

100000100000-00--u0000--000

-00

------111

000000uuuuuu000000-01

00000000000000x010-00

on er ts

s ‘0’.

Bank 210Ch LATA — — LATA5 LATA4 — — — — --xx ---- --uu -10Dh LATB(1) LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu -10Eh LATC LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu u10Fh — Unimplemented — —


111h CM1CON0(2) C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -112h CM1CON1(2) C1INTP C1INTN C1PCH — C1NCH 0000 -000 0000 -113h CM2CON0(2) C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -114h CM2CON1(2) C2INTP C2INTN C2PCH — C2NCH 0000 -000 0000 -115h CMOUT(2) — — — — — — MC2OUT MC1OUT ---- --00 ---- -116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- -117h FVRCON(2) FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 0q00 0000 0q00 0118h DACCON0(2) DACEN — DACOE1 DACOE2 DACPSS — — 0-00 00-- 0-00 0119h DACCON1(2) — — — DACR ---0 0000 ---0 0

11Ahto

11Ch— Unimplemented — —

11Dh APFCON CLKRSEL SDOSEL(1) SSSEL — T1GSEL P2SEL(1)

— — 000- --00 000- -11Eh — Unimplemented — —

11Fh — Unimplemented — —

Bank 318Ch ANSELA — — — ANSA4 — — — — ---1 ---- ---1 -18Dh ANSELB(1) — — ANSB5 ANSB4 — — — — --11 ---- --11 -18Eh ANSELC ANSC7(1) ANSC6(1) — — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 118Fh — Unimplemented — —


191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0192h PMADRH —(2) Flash Program Memory Address Register High Byte 1000 0000 1000 0193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu u194h PMDATH — — Flash Program Memory Read Data Register High Byte --xx xxxx --uu u195h PMCON1 —(2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0197h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- -198h — Unimplemented — —

199h RCREG USART Receive Data Register 0000 0000 0000 019Ah TXREG USART Transmit Data Register 0000 0000 0000 019Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 019Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 019Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 019Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 019Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0

TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)


Value onPOR, BOR

Valueall othRese

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read aNote 1: PIC16(L)F1459 only.



PIC16(L)F1454/5/9

------

uuu000111000000000000

-00-00-00---------

000-0-

on er ts

s ‘0’.

Bank 420Ch WPUA — — WPUA5 WPUA4 WPUA3 — — — --11 1--- --11 120Dh WPUB(1) WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 -

20Ehto

210h— Unimplemented — —

211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu u212h SSP1ADD ADD 0000 0000 0000 0213h SSP1MSK MSK 1111 1111 1111 1214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM 0000 0000 0000 0216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0

218hto

21Fh— Unimplemented — —

Bank 528Ch

to29Fh

— Unimplemented — —

Bank 630Ch

to31Fh


Bank 738Ch

to390h


391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 — IOCAP1 IOCAP0 --00 0-00 --00 0392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 — IOCAN1 IOCAN0 --00 0-00 --00 0393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 — IOCAF1 IOCAF0 --00 0-00 --00 0394h IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 -395h IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 -396h IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 -

397hto

399h— Unimplemented — —

39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC CLKRDIV 0011 0000 0011 039Bh ACTCON ACTEN ACTUD — ACTSRC ACTLOCK — ACTORS — 00-0 0-0- 00-0 0

39Chto


Bank 840Ch

to41Fh


Bank 948Ch

to49Fh




Value onPOR, BOR

Valueall othRese




PIC16(L)F1454/5/9

---uuu------uuu---

000xxx--0-0000-

on er ts

s ‘0’.

Bank 1050Ch

to51Fh


Bank 1158Ch

to59Fh


Bank 1260Ch

to610h


611h PWM1DCL PWM1DCL — — — — — — 00-- ---- 00-- -612h PWM1DCH PWM1DCH xxxx xxxx uuuu u613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 0000 ---- 0000 -614h PWM2DCL PWM2DCL — — — — — — 00-- ---- 00-- -615h PWM2DCH PWM2DCH xxxx xxxx uuuu u616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 0000 ---- 0000 -

617hto


Bank 1368Ch

to690h


691h CWG1DBR(2) — — CWG1DBR --00 0000 --00 0692h CWG1DBF(2) — — CWG1DBF --xx xxxx --xx x693h CWG1CON0(2) G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 0000 0--0 0000 0694h CWG1CON1(2) G1ASDLB G1ASDLA — — G1IS 0000 --00 0000 -695h CWG1CON2(2) G1ASE G1ARSEN — — G1ASDC2 G1ASDC1 G1ASDSFLT — 00-- 0001 00-- 0

696hto


Banks 14-28x0Ch/x8Ch —x1Fh/x9Fh




Value onPOR, BOR

Valueall othRese




PIC16(L)F1454/5/9

00-uu-000000000000uuuuuu000000000000000000000000000000

on er ts

s ‘0’.

Bank 29E8Ch — Unimplemented — —

E8Dh — Unimplemented — —

E8Eh UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- -0u0 0E8Fh USTAT — ENDP DIR PPBI — -xxx xxx- -uuu uE90h UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 -000 0E91h UCFG UTEYE Reserved — UPUEN Reserved FSEN PPB 00-0 -000 00-0 -E92h UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 -000 0E93h UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 -000 0--0 -E94h UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx ---- -E95h UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx uuuu uE96h UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 -000 0E97h UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 0--0 0E98h UEP7 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E99h UEP6 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E9Ah UEP5 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E9Bh UEP4 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E9Ch UEP3 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E9Dh UEP2 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E9Eh UEP1 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0E9Fh UEP0 – – – EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0 Bank 30F0Ch —F1Fh




Value onPOR, BOR

Val

Documents

PIC16(L)F1454/5/9 14/20-Pin, 8-Bit Flash USB Microcontroller with … · 2020. 9. 30. · PIC16(L)F145X DS40001639C-page 6 2012-2020 Microchip Technology Inc. TABLE 2: 14-PIN ALLOCATION