Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors.pdf

7Photonic Network-on-Chip Architectures Using Multilayer DepositedSilicon Materials for High-Performance Chip Multiprocessors

ALEKSANDR BIBERMAN, Columbia UniversityKYLE PRESTON, Cornell UniversityGILBERT HENDRY, Columbia UniversityNICOL AS SHERWOOD-DROZ, Cornell UniversityJOHNNIE CHAN, Columbia UniversityJACOB S. LEVY and MICHAL LIPSON, Cornell UniversityKEREN BERGMAN, Columbia University

Integrated photonics has been slated as a revolutionary technology with the potential to mitigate the manychallenges associated with on- and off-chip electrical interconnection networks. To date, all proposed chip-scale photonic interconnects have been based on the crystalline silicon platform for CMOS-compatible fab-rication. However, maintaining CMOS compatibility does not preclude the use of other CMOS-compatiblesilicon materials such as silicon nitride and polycrystalline silicon. In this work, we investigate utilizingdevices based on these deposited materials to design photonic networks with multiple layers of photonicdevices. We apply rigorous device optimization and insertion loss analysis on various network architec-tures, demonstrating that multilayer photonic networks can exhibit dramatically lower total insertion loss,enabling unprecedented bandwidth scalability. We show that significant improvements in waveguide propa-gation and waveguide crossing insertion losses resulting from using these materials enables the realizationof topologies that were previously not feasible using only the single-layer crystalline silicon approaches.

Categories and Subject Descriptors: B.4.3 [Input/Output and Data Communications]: Interconnections(Subsystems)Topology; C.2.1 [Computer-Communication Networks]: Network Architecture and De-signNetwork topology; Circuit-switching networks; C.4 [Performance of Systems]: design studies

General Terms: Design, Measurement, Performance

ACM Reference Format:Biberman, A., Preston, K., Hendry, G., Sherwood-Droz, N., Chan, J., Levy, J. S., Lipson, M., andBergman, K. 2011. Photonic network-on-chip architectures using multilayer deposited silicon materialsfor high-performance chip multiprocessors. ACM J. Emerg. Technol. Comput. Syst. 7, 2, Article 7 (June2011), 25 pages.DOI = 10.1145/1970406.1970409 http://doi.acm.org/10.1145/1970406.1970409

A. Biberman, G. Hendry, and K. Preston contributed equally to this work.We acknowledge support from the National Science Foundation and Semiconductor Research Corporationunder grant ECCS-0903406 SRCTask 2001. This workwas part of theNational Science Foundation CAREERProgram under grant 0446571, and Air Force Office of Scientific Research under grant FA9550-07-1-0200under the supervision of Dr. Gernot Pomrenke. K. Preston acknowledges partial support from the IBM Ph.D.Fellowship. This work was performed in part at the Cornell NanoScale Facility, a member of the NationalNanotechnology Infrastructure Network, which is supported by the National Science Foundation undergrant ECS-0335765.Authors addresses: A. Biberman, G. Hendry, J. Chan, and K. Bergman, Department of Electrical Engi-neering, Columbia University, 1300 Seeley W. Mudd, 500 West 120th St, New York, NY 10027; email:{biberman, gilbert, johnnie, bergman}@ee.columbia.edu; K. Preston, N. Sherwood-Droz, J. S. Levy, and M.Lipson, School of Electrical and Computer Engineering, Cornell University, 428 Phillips Hall, Ithaca, NY14853; email: {kjp32,nrs35.jsl77.ml292}@cornell.edu.Permission to make digital or hard copies of part or all of this work for personal or classroom use is grantedwithout fee provided that copies are not made or distributed for profit or commercial advantage and thatcopies show this notice on the first page or initial screen of a display alongwith the full citation. Copyrights forcomponents of this work owned by others than ACM must be honored. Abstracting with credit is permitted.To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of thiswork in other works requires prior specific permission and/or a fee. Permissions may be requested fromPublications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212)869-0481, or [email protected] 2011 ACM 1550-4832/2011/06-ART7 $10.00DOI 10.1145/1970406.1970409 http://doi.acm.org/10.1145/1970406.1970409

ACM Journal on Emerging Technologies in Computing Systems, Vol. 7, No. 2, Article 7, Pub. date: June 2011.

7:2 A. Biberman et al.

1. INTRODUCTIONPerformance scalability of the chip multiprocessor (CMP) is becoming increasingly con-strained by limitations in power dissipation, chip packaging, and the data throughputachievable by the on-chip interconnection networks. The interconnection networks ofthe CMP have become a substantial determinant to overall system performance, sincethey serve as the communication links between pairs of cores, and provide the means toconnect cores to off-chip inputs/outputs (I/O) andmemory. Interconnection networks arebeing designed with larger datapath widths and higher signaling frequencies to meetthe requirements of certain communication-bound applications; however, the powerdissipation of electronic links tends to scale with throughput performance, causing aremarkable increase in overall chip power dissipation. Past studies have indicated thatover half the dynamic power in some high-performance microprocessors is dissipatedby the interconnects [Magen et al. 2004]. These performance trends, combined with thethermal limitations of current chip-packaging technologies, have created the challengeof finding new solutions that can supply enough bandwidth to all the processing coreswhile maintaining a sustainable power dissipation level.One highly attractive solution for solving the power and performance bottlenecks of

on-chip interconnects is silicon photonics, for its many performance and economic ad-vantages. Photonic systems can achieve extremely high bandwidth densities throughwavelength division multiplexing (WDM), where multiple wavelength-parallel opticaldata streams are transmitted in a single optical waveguide. Additionally, photonicswitches and waveguides do not consume power per bit or per distance because, incontrast with electronics, they are bit-rate transparent. The current scope of siliconphotonic interconnect designs proposed by the research community use a single layerof crystalline silicon for all optical waveguides and devices to maintain CMOS com-patibility [Vantrease et al. 2008; Joshi et al. 2009; Shacham et al. 2007; Pan et al.2009; Petracca et al. 2008; Cianchetti et al. 2009]. While many of these designs showedthat optical data transmission can substantially enhance overall system performance,there are several challenges inherent to this platform including insertion loss fromwaveguide propagation and waveguide crossings, and optical nonlinearities such astwo-photon absorption (TPA), and the resulting free-carrier absorption (FCA) and free-carrier dispersion (FCD) [Liang and Tsang 2004].To date, no proposed designs have included the use of other optical materials that

exist in the CMOS process, such as silicon nitride and polycrystalline silicon. Thesematerials offer unique optical properties that could potentially improve the perfor-mance of photonic interconnect designs. Because these materials can be deposited,they are able to be monolithically stacked into multiple photonic layers analogous tometal wiring. This extra dimension of design freedom was previously unavailable tochip-scale photonic interconnect designs based on single-layer crystalline silicon. Addi-tionally silicon nitride as a waveguiding material can exhibit lower linear propagationloss and nonlinear loss mechanisms than crystalline silicon.This work discusses the background and steps required for multilayer architectures,

frommaterials to devices and topologies.We begin in Section 2 by discussing the variousCMOS silicon materials available for photonic interconnect design, and identify theirstrengths and weaknesses compared to the traditional crystalline silicon-on-insulatorplatform. In Section 2, we describe the various improved devices that can be realized bycombining different materials, and how they can be connected to produce fundamentalnetwork functionalities such as modulation, switching, and photodetection. Section 3investigates the impact of using multilayer devices on wavelength-routed architecturesusing insertion loss analysis. Section 4 applies a similar analysis to broadband-switchedarchitectures, with switch optimization for minimizing insertion loss. The results indi-cate that using multilayer networks reduces the insertion loss and the required laser


Photonic Network-on-Chip Architectures for High-Performance Chip Multiprocessors 7:3

power, which in turn enables both the use of more wavelength channels for highernetwork bandwidth, and the realization of topologies previously not feasible using thesingle-layer networks. We summarize our work in Section 5.

2. SILICON PHOTONICS2.1. Materials for Silicon PhotonicsSilicon (Si) can be considered the workhorse of the semiconductor industry. Given itsabundance and versatility, silicon has become the dominant platform for microelec-tronic fabrication. As such, any improvements to CMOS microelectronic chips mustbe compatible with the silicon materials, devices, and processing. We discuss here themain CMOS materials with potential applications for integrated photonics.

2.1.1. Crystalline Silicon. Single-crystalline silicon (c-Si) consists of a perfect lattice ofsilicon atoms, and offers the best set of electrical and optical properties for siliconintegrated photonics. Silicon is transparent at the standard telecommunication wave-lengths around = 1.55m, and has a high refractive index of 3.5 that allows sub-micron-scale waveguides with very tight bending radii when paired with a silicondioxide (SiO2) cladding. The fundamental optical losses in bulk crystalline silicon at = 1.55m are dominated by free-carrier absorption [Soref and Bennett 1987]. Typ-ical p-doped silicon-on-insulator (SOI) wafers have a concentration of 1015cm3 holes,generating a fundamental material propagation loss of 0.026dB/cm from this effect.Experimentally, the waveguide propagation loss is higher due to scattering and ab-sorption at the waveguide sidewalls, though insertion loss values as low as 1.7dB/cmhave been demonstrated [Xia et al. 2007]. Electrons and holes also induce a smallchange in the refractive index of silicon, which can be harnessed as an efficient andeffective way to modulate and route light on chip [Manipatruni et al. 2007; Lira et al.2009].Unfortunately crystalline silicon can only be grown from another silicon crystal,

making it impossible to deposit in this state, and typically limiting the optical devicesto a single layer. Most research in the area of silicon photonics thus relies on a customversion of SOI where a 0.25m crystalline silicon device layer is transferred onto athick buried silicon dioxide optical buffering layer on top of a bulk silicon substrate.The SOI process typically raises the cost of a wafer by at least an order of magnitude,and limits the architecture to a single optical layer of waveguides and other devices.

2.1.2. Polycrystalline Silicon. Polycrystalline silicon (polysilicon, or poly-Si) is commonlyfound in CMOS fabrication as a gatematerial for transistors. However, it is also capableof being deposited as an electrically-conductive light-guiding material. Polycrystallinesilicon does not have a homogeneous crystalline structure, but instead consists of crys-talline grains separated by thin disordered grain boundaries. The size of the crystallinegrains and the nature of the grain boundaries have a significant effect on the opticaland electrical material properties, and are controllable by the fabrication conditions.Optically, the grain boundaries scatter and absorb light and cause propagation losses.Electrically, the grain boundaries impede the flow of electrons and holes. Hence, havinglarger grains (fewer grain boundaries) in the material optimizes both the optical andelectrical properties. Experimentally, the minimum demonstrated waveguide propaga-tion loss is 6.45dB/cm [Fang et al. 2008].Although for many applications the electrical properties of polycrystalline silicon

are inferior to crystalline silicon, the grain boundaries reduce the free-carrier lifetime,which can be advantageous for some devices. The effective free-carrier recombinationtime has been demonstrated to be Carrier 100ps [Preston et al. 2009], or approxi-mately four times faster than comparable devices in crystalline silicon. Additionally,



it has been shown the polycrystalline silicon can be used as a moderately absorbingmaterial for photodetectors [Preston et al. 2011].

2.1.3. Silicon Nitride. Although polycrystalline silicon may be used for electrically ac-tive devices, the propagation losses are intolerable over centimeter-scale distances.Alternatively, we consider silicon nitride (Si3N4), another CMOS-compatible materialcapable of being deposited, with a refractive index near 2 at = 1.55m. Microelec-tronic processing typically uses silicon nitride as a masking layer. Although siliconnitride is not useful for making electrically active devices, its high refractive index,compared to silicon dioxide, still allows for high confinement sub-micron waveguides.More importantly, silicon nitride waveguides have been demonstrated with 0.1dB/cmpropagation loss around = 1.55m (in loosely confined [Shaw et al. 2005] or multi-mode [Gondarenko et al. 2009] waveguides). This represents approximately an order ofmagnitude lower propagation loss compared to crystalline silicon waveguides, makingit an ideal candidate for waveguides using a deposited material.

2.1.4. Amorphous Silicon. Hydrogenated amorphous silicon (a-Si:H) is another de-posited material that can be used for waveguides. The refractive index (3.5) andwaveguide propagation loss (23dB/cm) are comparable to crystalline silicon, but thepropagation loss can increase dramatically with time and/or temperature if hydrogendiffuses out [Zhu et al. 2010], making it a less stable material than silicon nitride.

2.1.5. Germanium. Photodetectors require a material that absorbs light at the wave-length of interest. Germanium (Ge) is an available CMOS material used to createstrained silicon transistors and SiGe alloy heterojunction bipolar transistors. Ger-manium is an indirect-bandgap material whose 0.8eV direct-band transition enablesstrong absorption for 1.55m, and strain can be used to extend absorption to longerwavelengths. The primary challenge for germanium integration is the 4% lattice mis-match with silicon, which makes it difficult to grow high-quality germanium material[Michel et al. 2010]. Polycrystalline germanium can also be used as a lower-qualityphotodetector material that is easier to integrate [Colace et al. 2006].

2.1.6. 3D Material Stack. An optical layer consists of a high-refractive-index core mate-rial sandwiched between lower-index cladding layers. The cladding provides a bufferto keep the light confined to the waveguide core. Multiple optical layers can be stackedwith a buffer layer of cladding material in between them. The thickness of the buffercontrols the optical coupling between the layers, in the same way a horizontal gap isused between a single-layer waveguide coupling to a microring resonator. One ben-efit of multi-layer integration is that deposition of these materials can be controlledaccurately to the nanometer scale, which is prohibitively difficult and expensive forlithographically defined single-layer gaps.Thematerial stack considered in this work (Figure 1) contains three optical layers: an

active polycrystalline silicon layer sandwiched between two silicon nitride waveguidinglayers, with silicon dioxide cladding in between the layers. This approach providesan active layer (used for switching, photodetection, and modulation) coupled to twobus waveguide layers which do not interact with each other. There is no fundamentallimitation on howmany layers one could use, given an architectural need for them, sinceeach layer is deposited and each buffer layer is flattened using chemical mechanicalpolishing.

2.2. Silicon Photonic Devices2.2.1. Waveguides. The waveguide is the most basic silicon photonic component, used

to carry high-speed optical data from one point to another [Lee et al. 2008a; Lipson2005]. Silicon photonic waveguides are capable of transporting wavelength-parallel



Fig. 1. Cross-sectional view of vertically-stacked optical link. Two orthogonal silicon nitride bus waveg-uides are shown above and below of an electrically-active region which consists of polycrystalline silicon orgermanium.

optical data with terabit-per-second data rates across the entire chip [Lee et al. 2008a].Moreover, these waveguides can be crossed [Bogaerts et al. 2007; Popovic et al. 2007; Xuand Poon 2008], and coupled [Lipson 2005], creating regions where the optical signalcan be passed from one waveguide to another.In recent years, crystalline silicon waveguides with submicron dimensions have been

almost the exclusive choice for photonic links. However, physical crossings of waveg-uides result in significant insertion losses when considering a full-scale interconnectionnetwork [Chan et al. 2010a]. Research efforts have been targeted at minimizing theselosses [Bogaerts et al. 2007; Popovic et al. 2007; Xu and Poon 2008], but even a 0.045dBloss will add significant power limitations when multiplied by tens, hundreds, or eventhousands of waveguide crossings.In contrast, deposited silicon nitride waveguides introduce myriad potential advan-

tages for integrated photonics, many of which are yet to be explored. Recent effortshave placed silicon nitride waveguides as the carrier medium in high-speed commu-nication links, with the vision of monolithic integration of high-performance photonicand electrical elements using standard CMOS processes [Young et al. 2010]. Unlikecrystalline silicon, silicon nitride can be deposited in multiple layers, analogous toelectronic wiring. This multilayer integration has the potential to eliminate in-planewaveguide crossing losses, as waveguide crossings may now be performed entirely outof plane, as depicted in Figure 2(a). In this work, we propose the use of silicon nitridewaveguides as the primary transport layer in our multilayer photonic networks, mov-ing wavelength-parallel terabit-per-second optical data with low propagation loss andno waveguide crossings.

2.2.2. Modulators. The electro-optic modulator is a critical device that enables high-speed conversion from an electrical signal to an optical signal, typically encoding dataon a single wavelength channel that can be combined with other optical signals throughWDM, forming a cohesive wavelength-parallel optical signal. A key contribution ofpower consumption in the modulator is the serialization/deserialization (SERDES),which are used to convert data rates from the chip clock rate to higher modulationrates.Due to their compact size, high speed, and low energy dissipation, the crys-

talline silicon microring resonator electro-optic modulators have been the primaryconsiderations in most recent efforts proposing chip-scale photonic interconnectionnetworks [Krishnamoorthy et al. 2009; Batten et al. 2009; Beausoleil et al. 2008;



Fig. 2. Silicon photonic devices for both single-layer and 3D-integrated approaches.



Shacham et al. 2007; Kirman et al. 2006]. Recent experimental validations have pro-duced these devices with microring resonator diameters as low as 3m [Xu et al. 2008],modulation rates as high as 18Gb/s [Manipatruni et al. 2007], driving voltages as lowas 150mVPP [Manipatruni et al. 2010], and in the microdisk resonator configuration,energy dissipation as low as 3fJ/bit [Zortman et al. 2010]. This crystalline siliconsingle-layer approach for the modulator is depicted in Figure 2(b).The electro-optic modulator has also been demonstrated in polycrystalline silicon

[Preston et al. 2008]. The grain boundaries inherent in the material result in increasedoptical loss due to scattering and absorption, but also faster electron-hole recombina-tion, which decreases the free-carrier lifetime and can increase the intrinsic speed ofthe modulator [Preston et al. 2008]. Furthermore, unlike crystalline silicon, polycrys-talline silicon is also capable of being deposited and stacked with other silicon photonicmaterials for multilayer integration.In this work, we explore the use ofmicroring resonator electro-opticmodulators based

on polycrystalline silicon for multilayer photonic interconnection networks, coupled toone of the silicon nitride waveguide layers, as depicted in Figure 2(b). The effectiveindex of the microring resonator and waveguide must be matched to efficiently transferoptical power; therefore, we assume each modulator is coupled to a local polycrystallinesilicon bus waveguide, which is then coupled to a silicon nitride waveguide with abroadband vertical coupler [Sun et al. 2008], assuming a 0.1dB optical loss per coupling.In this work, we assume a quality factor of 15,000 for the microring resonator of

the modulator, a 10Gb/s data rate per wavelength channel, and a 1.5m microringresonator radius, corresponding to a free spectral range (FSR) of about 60.7nm. TheFSR represents the maximum bandwidth available for WDM, and the maximum num-ber of utilized wavelength channels is determined by dividing this bandwidth by thewavelength channel spacing.

2.2.3. Switches. Microring resonator electro-optic broadband switches are consideredin some photonic interconnection networks for their ultrahigh bandwidth and lowenergy dissipation [Dong et al. 2007]. By leveraging comb-switching with wavelength-parallel optical message encoding, aligningmany high-speedwavelength channels withunique resonances of the microring resonator, we have experimentally verified the po-tential these silicon photonic devices have for routing ultrahigh bandwidth signals [Leeet al. 2010]. We have recently demonstrated broadband wavelength-parallel operationof switches in 1 2 [Lee et al. 2008b], 2 2 [Lee et al. 2009], and 4 4 configura-tions [Biberman et al. 2010a], routing optical data with up to 12.5Gb/s data rates perwavelength channel and 250Gb/s aggregate data rates. Furthermore, by utilizing aconfiguration with a second-order microring resonator, we have recently demonstratedsub-nanosecond electro-optic switching of optical data with up to 40Gb/s data rates perwavelength channel, observing 12-dB extinction ratios with 1.3VPP driving voltages[Biberman et al. 2010b]. An example crystalline silicon single-layer 1 2 switch witha first-order microring resonator is depicted in Figure 2(c).Within the platform of deposited materials, polycrystalline silicon is capable of

enabling electrically-active microring resonators [Preston et al. 2008] for multilayersilicon photonic integration [Preston et al. 2007]. Excess propagation loss and reducedfree-carrier lifetime will impact the insertion loss and power consumption, respectively.We propose the use of ultrahigh-channel-density microring resonator electro-optic

switches in order to route wavelength-parallel signals. These switches are located inthe electrically-active polycrystalline silicon layer, coupled between two silicon nitridewaveguides at opposing layers, as depicted in Figure 2(c). The electro-optic switcheswill route high-speed optical data between the two perpendicularly-routed layers tocreate an optical 90-degree turn. We assume a polycrystalline silicon propagation loss



of 5dB/cm, and a 350nm 150nm cross section to closely match the polycrystallinesilicon microring resonator mode to the silicon nitride waveguide mode. For crystallinesilicon, we assume a 450nm 250nm cross section and propagation loss of 2dB/cm.In both cases, we design the switch (Section 4.1) to have a maximum quality factor of15,000 in order to match the modulator.

2.2.4. Photodetectors. Located at the end of the optical communication link, the pho-todetector translates an incoming high-speed optical signal into the electrical domain.This is accomplished by absorbing the light to generate an electrical current. In manyphotonic interconnection network designs, crystalline siliconmicroring resonator filtersare used to demultiplex wavelength-parallel optical data into spatially-parallel opticaldata, placing each wavelength channel on a unique waveguide. Once each wavelengthchannel is isolated, it can be detected using a high-speed photodetector.Since crystalline silicon does not exhibit linear absorption in the telecommunica-

tion wavelength bands, photonic interconnection networks have leveraged germaniumas the absorbing material for photodetection [Michel et al. 2010]. Recent efforts inintegrating germaniumphotodetectors with crystalline siliconwaveguides have yieldedmany high-performance CMOS-compatible devices targeting high bandwidth, high re-sponsivity, high quantum efficiency, low dark current, and low capacitance. Leveragingthis material system, bandwidths exceeding 40GHz [Vivien et al. 2009; Assefa et al.2010; Chen and Lipson 2009], responsivities above 1A/W [Vivien et al. 2009; Yin et al.2007], quantum efficiencies higher than 90% [Chen and Lipson 2009; Yin et al. 2007],dark currents below 200nA [Yin et al. 2007], and capacitances around 2fF [Chen andLipson 2009], have all been demonstrated. This crystalline silicon and germaniumapproach for the photodetector is depicted in Figure 2(d).Another emerging method for producing photodetectors is to use silicon with crystal

defects as the absorbing material. Recent efforts have enhanced linear absorption byimplanting ions to create defects [Bradley et al. 2005], obtaining bandwidths exceed-ing 35GHz and responsivities as high as 10A/W in different devices [Geis et al. 2009].Similarly, deposited polycrystalline silicon can be used as the absorbing material in amicroring resonator geometry to enhance absorption and reduce the footprint, demon-strating responsivities as high as 0.15A/W [Preston et al. 2011]. Due to the moderateoptical absorption, the absorbing polycrystalline silicon material can serve as boththe demultiplexing filter and the photodetector. We explore the use of microring res-onator photodetectors based on polycrystalline silicon in the electrically active layer,as depicted in Figure 2(d).We build a photodetector array by linking several photodetectors, each tuned to

a unique wavelength channel. This technique is similar to what has recently beendemonstrated with four cascaded crystalline silicon microring resonator filters de-multiplexing a wavelength-parallel optical signal into geranium photodetectors with19GHz bandwidths [Chen and Lipson 2009]. In the 3D-integrated configuration, thepolycrystalline silicon microring photodetectors are coupled to a local polycrystallinesilicon bus waveguide, which is vertically coupled to silicon nitride with a broadbandvertical coupler [Sun et al. 2008], assuming a 0.1dB optical loss per coupling.

2.2.5. Lasers. Since silicon is an indirect-bandgap material, it is not naturally capableof achieving efficient radiative recombination required for producing a high-qualitylaser. However, silicon can potentially serve as a platform for lasing by incorporatingother gain materials [Liang and Bowers 2010]. Recent efforts in epitaxial growth ofgermanium on silicon have used tensile strain and heavy doping to produce a nearlydirect bandgap, and room-temperature optically pumped lasing has been demonstrated[Liu et al. 2010]. Other promising techniques have produced electrically pumped hy-brid silicon lasers, where the optical mode is evanescently coupled to III-V compound



semiconductors [Van Campenhout et al. 2008]. Other research efforts are aimed atproducing electrically pumped rare-earth-ion lasers on silicon [Jambois et al. 2010;Yerci et al. 2010]. As these emerging technologies continue to mature, and high-qualityon-chip lasers compatible with CMOS fabrication techniques come to fruition, thesedevices will fill a critical gap that currently exists in systems based on silicon photonics.More near-term solutions leverage III-V compound semiconductors to produce effi-

cient external off-chip lasers, and couple the produced light to the silicon chip. Quan-tum dot lasers, based on III-V compound semiconductor quantum dots, are capableof producing many narrow-spectrum peaks over an entire wavelength band that canbe used for WDM applications [Livshits et al. 2010]. Coupled with broadband quan-tum dot semiconductor optical amplifiers, these lasers are capable of producing manywavelength channels, with low relative intensity noise, that may be modulated, trans-mitted, and received with error-free performance [Gubenko et al. 2007]. This approachalleviates packaging complexity of the silicon chip, while simultaneously minimizingthe overall cost and power consumption. Another potential approach is to use para-metric oscillation in silicon nitride microring resonators to convert an off-chip single-wavelength source to an on-chip multiple-wavelength WDM comb [Levy et al. 2010].

2.2.6. Monolithic Multilayer Silicon Device Integration. Experimental demonstrations of mul-tilayer silicon photonic systems have involved crystalline silicon waveguides on onephotonic plane vertically coupled to polycrystalline silicon microring resonators on an-other photonic plane [Preston et al. 2007], and crystalline silicon waveguides verticallycoupled to amorphous silicon waveguides in a low-loss and compact coupler [Sun et al.2008]. These are critical experimental validations of deposited silicon photonic devicesthat are monolithically integrated with low-loss silicon photonic waveguides.A further demonstration of silicon photonic systemswithmultiplematerials included

low-loss silicon nitride waveguides, polymer-based electro-optic modulators, and poly-crystalline germanium photodetectors, also fabricated using CMOS-compatible pro-cesses [Young et al. 2010]. Additional demonstrations have included monolithic inte-gration of silicon nitride waveguides with germanium photodetectors [Ahn et al. 2007].

2.3. Modeling of Microring Resonator DevicesThe microring resonator is a critical building block for compact and scalable siliconphotonic systems. As shown in Section 2.2, the microring resonator forms the basis ofmodulators, single-channel demultiplexing filters and switches, and multiple-channelWDM comb switches. Here we briefly describe the physical modeling that is applicableto all types of microring resonator devices.For a microring resonator coupled to two waveguides as shown in Figure 3, equations

for the through port and drop port responses can be written down by inspection byconsidering the phase and amplitude of the optical mode as it propagates throughthe device [Yariv 2000]. The important parameters set by material properties andwaveguide cross-section are the propagation loss and the effective index nef f (). Thedesign parameters are the microring resonator radius r and the field transmission andcoupling coefficients t and . A lossless coupler has t2+2 = 1, which we will assume forthe remainder of the paper, and the coupling strength is determined by the separationbetween the waveguide and the microring resonator (horizontal gap for single-layerdevices, or vertical gap for multilayer devices).The quality factor, or spectral width, of the resonance is determined by the propaga-

tion loss and coupling. Similarly, the extinction ratio of the resonance is determined bythe ratio of propagation loss to coupling, with critical coupling occurring for t1 = t2.Tuning the filter wavelength (or modulating the optical transmission) is accom-

plished by changing the material refractive index n of the microring, which changes



Fig. 3. Schematic of a microring resonator coupled to a through waveguide and a drop waveguide, whichcan be used as a WDM broadband switch, with close-up views of the electric field coupling for universaldirectional couplers. In a single pass, the transmitted component of the electric field is multiplied by t andthe coupled component is multiplied by i. This universal description is independent of the material systemused.

the effective index nef f of the optical mode, which shifts the resonant wavelength. Therelationship between material and effective index is given by nef f = n, where = nef f

n is the silicon confinement factor of the optical mode [Robinson et al. 2008],which depends on the cross-sectional dimensions. Refractive index tuning can be accom-plished onmicrosecond time scales by changing the temperature, or on sub-nanosecondtime scales by changing the electron and hole concentration using free-carrier disper-sion (FCD) [Soref and Bennett 1987] using an integrated electrical diode. Fast tuningby FCD is accompanied by loss from free-carrier absorption (FCA), which broadensthe resonance and changes the critical coupling condition for the maximum extinctionratio.The free spectral range (FSR) of a microring resonator is approximated by FSR

202rng

. For amicroring resonator around = 1.55mwith ng = 4.2 and rMin = 1.5m, wehave FSRMax = 60.7nm, which is the maximum bandwidth available. The wavelengthchannel spacing then determines the number of available wavelength channels. Forinstance, given a channel spacing of 1.2 nm, there can be a maximum of 50 wavelengthchannels. The broadband switch would then require a microring resonator radiusr = 75.87m to match this channel spacing.

3. EVALUATION OF WAVELENGTH-ROUTED ARCHITECTURESUsing deposited silicon materials for guiding and switching light can have a significantimpact on optical signal integrity, depending on the network architecture or topology.In this work, we analyze how deposited materials affect the optical power budget andthe insertion loss for a variety of proposed photonic network architectures. Though wedo not compare these architectures to each other, which would require an in-depth andcomplex architectural study, we analyze the trade-offs and benefits of using depositedmaterials. Each network is capable of interconnecting 64 network access points, dis-regarding access point concentration. We also assume a 2cm 2cm chip to calculatepropagation distances, which constraints some of the networks.



Table I. Optical Power Budget ParametersOptical Power Limitations

Parameter Single-Layer Multi-LayerWaveguide Maximum Injected 20.6dBm (115mW) 30dBm (1000mW)Modulator Maximum Injected (On Resonance) 2dBm (0.6mW) 0 dBm (1mW)Switch Maximum Injected (On Resonance) 17dBm (50mW) 17.8dBm (60mW)Photodetector Sensitivity 20dBm (0.01mW) 17dBm (0.02mW)

We divide these architectures into two categories: wavelength-routed and broadband-switched. In this section, we examine wavelength-routed architectures. First, we de-scribe the relevant issues associated with the analysis of a photonic networks opticalpower budget.

3.1. Optical Power Budget and Insertion LossThe optical power budget determines how much laser power must be allocated to over-come insertion loss through the photonic network, ensuring that the optical signalis able to be reliably detected. The larger this value, the more insertion loss we cantolerate, and the larger we can scale the network. Table I shows the physical-layer con-straints that determine the optical power budget. The amount of optical power that wecan inject into the network is limited by the amount of optical power we can feasibly in-ject into the waveguide, modulator, and switch, which is different for each material (Ta-ble I). Here we define the limit as the power that will generate 1016cm3 electrons andholes caused by two-photon absorption (TPA) [Liang and Tsang 2004], since carrier con-centrations on the order of 1017cm3 are typically used to operate the devices. This willgenerate loss from FCA, causing propagation loss in waveguides and resonance broad-ening in microring resonators. More importantly, it will also cause instability in theresonance wavelength due to the refractive index blue shift from FCD. We factor in thefree-carrier lifetime in the different materials (500ps in crystalline silicon, 200ps inpolycrystalline silicon) and the optical power buildup in the different resonators (180in the modulator, 2 in the switch), to determine the final maximum power threshold.The photodetector sensitivity determines the optical power that must reach the

receiver, which is also different for the two material systems. For both cases, we as-sume that the receiver circuit requires a peak current 20A for error-free operation(BER < 1012) [Zheng et al. 2010]. For the single-layer germanium photodetector, weassume a responsivity of 1A/W, which then requires peak optical power 20W or av-erage received power 10W. For the polycrystalline silicon photodetector, we assumea responsivity of 0.5A/W, requiring an average received power 20W.The optical power budget is the difference between maximum power injected and the

photodetector sensitivity. Depending on the network architecture, the maximum powerinjected is constrained by the waveguide itself, the first modulator, or the first switchthat is encountered. We will describe these constraints when presenting the results ofeach network in subsequent sections.Once we establish our optical power budget, we can then determine the maximum

insertion loss through the network. If this insertion loss exceeds our optical powerbudget, we are not able to feasibly inject and extract enough optical power to properlytransmit and recover the optical data. If we allocate enough optical power budget toaccount for this insertion loss, we are able to establish a successful optical transmissionlink. If our optical power budget exceeds the maximum insertion loss through thenetwork, the excess optical power may be used to increase wavelength parallelismby increasing the number of utilized wavelength channels. This is accomplished byinjecting the minimum power required to overcome insertion loss for each wavelength



Table II. Optical Device Insertion Loss ParametersInsertion Loss

Parameter Single-Layer Multi-LayerWaveguide Propagation (Crystalline Silicon) 0.5dB/cm Waveguide Propagation (Silicon Nitride) 0.1dB/cmWaveguide Propagation (Polycrystalline Silicon) 5dB/cmWaveguide Crossing 0.05dB 0dBWaveguide Bend 0.005dB/90 0.005dB/90Modulator Through Port (Off Resonance) 1.2dB 1.2dBPhotodetector Filter Through Port (Off Resonance) 0.05dB 0.05dBPhotodetector Filter Drop Port (On Resonance) 0.5dB Vertical Coupler (Polycrystalline Silicon to Silicon Nitride) 0.1dB

channel, while keeping the total injected power below the nonlinear threshold. Theserelationships are described by:

PdBBudget = PdBmInjected PdBmExtracted (1)

PdBBudget PdBLoss + 10 log10(N). (2)In Equations (1) and (2), PdBBudget is the optical power budget, P

dBmInjected is the injected

optical power, PdBmExtracted is the extracted optical power, PdBLoss is the maximum insertion

loss, and N is the number of wavelength channels. From this, we observe that for agiven optical power budget, a network which has less insertion loss is able to use morewavelength channels in a single guiding medium, increasing the aggregate bandwidthin the optical link.The maximum insertion loss through the network is very much dependent on the

performance of individual silicon photonic devices. The insertion losses of these devicesare listed in Table II for both types of integration. This includes insertion loss associatedwith waveguide propagation, crossing, and bending, as well as insertion loss effects ofthe modulator, filter, and couplers. These parameters will be used for the remainderof the insertion loss analyses in this work, unless otherwise stated where specializeddevices are modeled as required to realize some specific functionalities.

3.2. Insertion Loss of Wavelength-Routed ArchitecturesWavelength-routed architectures use WDM for arbitrating and routing messages todifferent access points. Typically, one of twomethods is used: single-writemultiple-read(SWMR) or multiple-write single-read (MWSR). An example of a simple SWMR buswould be implemented by one access point modulating a single wavelength channel,and each other access point having a filter and photodetector for that wavelengthchannel that can be selectively activated for photodetection (arbitrated separately).An example of a simple MWSR bus would be implemented by one access point beingable to modulate any wavelength channel, each of which corresponds to a differentaccess points receiver. In this case, the access points arbitrate for write permissionto a destination. Typically, multiple waveguides are used to increase the bandwidthbetween access points, and a serpentine layout is common for avoiding waveguidecrossings while reaching every access point.

3.2.1. Corona. The Corona network [Vantrease et al. 2008] is one example of awavelength-routed architecture which uses an optical token ring to arbitrate a massiveMWSR crossbar implemented with one million rings and 256 serpentine waveguides.Because it uses MWSR buses, all modulators must have their off state (not inject-ing carriers) as off resonance, so that modulated signals from other access points can



Fig. 4. Insertion loss analysis for Coronas crossbar network. (a) Worst-case insertion loss versus modulatorresonance shift in linewidths. (b) Injected optical power required versus number of wavelength channels,limited by the nonlinear threshold.

pass by on their way to the photodetector bank. One critical design choice for thesedevices is how large the spectral shift should be between the off -state modulator res-onance and the wavelength channel. The farther away the resonant peak, the lowerthe off-resonance through port loss (from the tail of the resonance), which is criticalfor a MWSR bus, but more power is required since the resonance is shifted farther.For Corona, this modulator is slightly different than the one listed in Table II, beingoptimized for a low through port loss.Figure 4(a) shows the worst-case insertion loss along one crossbar path for different

amounts of resonant shift (in modulator response linewidths), for quality factors of15,000 for the microring resonators of the modulators. As shown by the modulatoroptical power limit, a resonant shift of at least 2 linewidths is needed for the networkto be feasible without incurring too much off-resonance insertion loss. Note that themultilayer version has slightly more insertion loss, mostly due to the propagation lossof the polycrystalline silicon waveguides when passing through the modulators, andthe coupling to the silicon nitride waveguides at each crossbar group.Adhering strictly to Coronas design with four bundled waveguides per channel and

a single power waveguide sourcing each channel, Figure 4(b) shows required injectedpower to source the entire crossbar with quality factors of 15,000 and three linewidthshift modulators. Since we chose appropriate modulators such that the insertion lossfalls under the modulator power optical limit, the total injected power in the powerwaveguide will ultimately limit the number of wavelength channels that is able tobe used in each crossbar waveguide. Because the nonlinear threshold in silicon nitridewaveguides is significantly higher than in crystalline silicon, this allows themulti-layerCorona network to use 39 wavelength channels, compared to 7 wavelength channelsusing the single-layer approach, a 457% improvement, despite the multi-layer versionexhibiting more insertion loss.

3.2.2. Firefly. The Firefly network [Pan et al. 2009] was proposed to reduce the com-plexity of a wavelength-routed architecture to save power and area by using electricallinks for local communication, and a serpentine photonic layout for global communi-cation. One important difference of Firefly from Corona is that it uses SWMR busesinstead of MWSR, arbitrated by separate reservation channels. This means that itrequires tunable filters which are off by default to save power, and can shift onto res-onance to detect a signal. Because these filters need to be as small as possible (tomaximize their FSR) with a silicon slab (for electrical actuation), these filters will have



Fig. 5. Insertion loss analysis for Fireflys network. (a) Worst-case insertion loss versus filter resonanceshift for microring resonators with different quality factors. Lines stop when the quality factor cannot bemaintained. (b) Number of wavelength channels possible in optical power budget versus resonance shift,ultimately limited by modulator power and FSR.

a relatively high amount of insertion loss (about 20dB/cm) caused by radiation. Wecan design the filter to trade-off through port loss for drop port loss by varying theamount of resonant shift from off to on state. If the resonance peak in the off stateis farther away from the wavelength of light, making the through loss lower, it willtake more injected carriers to shift it back to the on state, which incurs more insertionloss when dropping the wavelength channel. For Firefly, we investigate the design ofthis critical component instead of using the passive filter listed in Table II. Also, sincetunable filters are required, the polycrystalline silicon filter and photodetector cannotbe used, and we use the same germanium photodetector scheme for both the single-and multilayer implementations.Figure 5(a) shows the worst-case insertion loss for one assembly channel in Firefly

versus filter resonance shift for filters with different quality factor values. First, wenotice an optimal point for each curve as through port loss is traded for drop port loss.Unfortunately, even though microring resonators with large quality factors could besupported in terms of insertion loss, the optical power in a single modulator limitsthe maximum insertion loss to 18 and 17dB for single- and multilayer integration,respectively. This means that the only microring resonators that are feasible here areones with quality factors of 5,000.Though searching for the optimal lowest insertion loss point will save on laser power

by requiring less injected optical power, using higher resonant shift distances willrequire larger wavelength channel spacing. We define the required channel spacing as:

Spacing = 6 Linewidth + Shi f t. (3)This maintains six linewidths of wavelength channel spacing at all times (regardless

of the shifting), which guarantees less than 20dB of filter crosstalk. Figure 5(b) showsthe number of wavelength channels, limited by both insertion loss and wavelengthchannel spacing. However, both of these values are ultimately limited to the modulatoroptical power limit, for both single- and multilayer networks, to 27 wavelengths. Themultilayer network does have slightly lower insertion loss of 16.9dB over the single-layer network, which has 17.8dB, an 18.7% improvement in injected power.

3.2.3. Clos. A photonic Clos network can also be implemented using WDM [Joshiet al. 2009], trading off electrical hops for optical complexity. Joshi proposed using



Fig. 6. Insertion loss analysis for photonic Clos network. Multilayer devices trade lower filtering insertionloss and lower propagation loss for added coupling loss (included in propagation) to effectively even outagainst the single-layer devices.

multiple waveguides, simply laid out in a U shape to create photonic point-to-pointlinks in a three-stage Clos. Designed using standardmodulators and passive filters andphotodetectors, this design has low complexity and low insertion loss. Figure 6 showsa coarse insertion loss breakdown for both single- and multilayer implementations.The two integration methods are nearly identical because, even though silicon nitridehas lower propagation loss, there is insertion loss to couple to the local polycrystallinesilicon waveguides, which also have higher propagation loss. The multilayer networkdoes save in insertion loss because it does not have passive filters that incur a drop portloss, since it uses a single polycrystalline silicon microring resonator for filtering andphotodetecting. However, since the photodetector sensitivity of a polycrystalline siliconphotodetector is 3dB higher than a germanium photodetector, the multilayer networkwould need to inject 96%more power than the crystalline silicon version, which directlyreflects the 2 difference in photodetector responsivity.

4. EVALUATION OF BROADBAND-SWITCHED ARCHITECTURESIn this section, we investigate photonic network architectures which use broadbandcomb switches to spatially cohesively route all wavelength channels in a waveguide totheir destination. To correctly design the microring resonators used in these switches,we must consider the trade-offs between microring resonator radius (and thereforewavelength channel spacing), through and drop port insertion loss, area, and the FSRof the modulators being used. In these networks, the worst-case insertion loss of thenetwork dictates the optical power budget required by a single wavelength channel,as well as the number of wavelength channels that can be utilized. First, we willbriefly describe the design space of 12 broadband comb switches that applies to bothsingle- and multilayer approaches, which we will use later in our analysis of differentnetworks.

4.1. Switch Design and OptimizationWhen using the microring resonator (Section 2.3) as a comb switch, its qualitativeproperties can be described as follows.

The extinction ratio at the through port ERThrough is maximized at the critical cou-pling condition when t1 equals the round-trip field loss at2.



Insertion loss at the through port ILThrough, or off-resonance coupling loss, is mainlydetermined by the overlap of the Lorentzian tails for adjacent resonances, which isdetermined by the quality factor and the wavelength channel spacing.

Extinction ratio at the drop port ERDrop is similarly determined by the overlapbetween adjacent resonances.

Insertion loss at the drop port ILDrop is mainly determined by the insertion loss andthe drop-port coupling 2. Increasing the coupling 2 will improve ILDrop. However,this reduces the quality factor, which then degrades ILThrough and ERDrop.

From these arguments, we find that the switch device can be optimized for a par-ticular network architecture, and that different networks will have different optimalswitch designs. This is because ILDrop can be improved at the expense of ILThrough (andvice versa) by fine tuning the coupling parameters. The key information is the numberof through and drop ports which are encountered by the optical signal as it traversesthe longest path through the network. This ratio of the number of through ports to thenumber of drop ports gives a function that can be minimized by device design, in orderto minimize the total insertion loss through the network.Fast switching is performed by changing the electron and hole concentration inside

themicroring resonator [Soref and Bennett 1987]. This has the effect of both decreasingnef f , which blue shifts the resonant wavelength, as well as increasing the loss , whichbroadens the resonance and changes the through port extinction ratio. Electrons andholes are injected into the microring resonator by turning on an integrated diode.The carriers then recombine if the diode is turned off, or are swept out if a reversebias is applied. In the absence of free-carrier absorption losses, the insertion loss andextinction ratio would be optimized by shifting the resonance the maximum distance of12 thewavelength channel spacing (

12 the comb switch FSR) by injecting somemaximum

carrier concentration determined by the geometry. However, due to free-carrier lossesand resonance broadening, ILThrough will eventually start degrading as more carriersare added to approach a shift of 12FSR. Therefore ILThrough will be minimized for anoptimal carrier concentration that shifts the resonance less than 12FSR, as depicted inFigure 7(a).The switch can be designed to operate in one of two possible modes shown in Figure 7,

which we designate Switch Logic 1 (SL1) and Switch Logic 2 (SL2). In the SL1 scheme,as shown in Figure 7(a), the diode is off when the signal is sent to the drop port and isswitched on to change to the through port [Dong et al. 2007]. This device is easier todesign, because critical coupling is set when the diode is off and no free carriers are inthe device. However, power is consumed in any switch sending its signal to the throughport. This is detrimental in networks where the majority of switches are set to theirthrough state.In the alternate SL2 scheme, as shown in Figure 7(b), the device is normally trans-

parent to the optical signal, that is, designed to pass the signal to the through portwhen off and to the drop port when the diode is turned on. This is advantageous interms of power consumption if switches spend most of their time in the through state.However ILDrop can be degraded substantially due to free-carrier losses when the diodeis on. This type of device is more challenging to design and experimentally demonstratebecause the resonant wavelength and critical coupling condition must be determinedfor a precise carrier concentration when the diode is on.In the following sections, we optimize the switch design across a wide parameter

space. The radius r is set to place a resonance at the desired wavelength, for instance,1550nm. (For SL2 devices, the resonant wavelength must be set for a particular carrierconcentration in the device.) In all cases, we set the coupling such that Q = 15,000 to



Fig. 7. Example of WDM comb switch modeling. Here we show one wavelength channel, which is repeatedevery wavelength spacing (or switch FSR). Here FSR = 1nm, = 2dB/cm, and Q= 15000. (a) Transmissionspectra for SL1 scheme, designed for minimum ILThrough. The diode is off (not consuming power) when thesignal is passed to the drop port. Here t1 = 0.8502, t2 = 0.8786, and the charge concentration when on is3.2 1017cm3. For this design, ILThrough = 0.218dB, ILDrop = 0.992dB, and ERDrop = 16.8dB. (b)Transmission spectra for the SL2 scheme. The diode is off (not consuming power) when the signal is sent tothe through port. Here t1 = 0.8502, t2 = 0.9168, and the charge concentration when on is 1.5 1017cm3.For this design, ILThrough = 0.156dB, ILDrop = 2.729dB, and ERDrop = 15.1dB.

match the assumed modulator Q, which avoids the speed being limited by the photonlifetime for data rates up to 15Gb/s. We then sweep the parameters of the FSR, inputcoupling, output coupling, and carrier concentration in order to determine ILThrough,ILDrop, and ERDrop for each design. (Note that ERThrough can be arbitrarily high insimulation. Additionally, the switch hold power can be determined by POn = VOn IOn =VOn qCarrier where VOn is the on-state voltage, q is the charge injected to switch states,and Carrier is the free-carrier lifetime.) The insertion loss values can then be used todetermine the best device design for any given network architecture.

4.2. Insertion Loss of Broadband-Switched ArchitecturesIn the following sections, we investigate four different broadband-switched architec-tures and topologies: Phastlane, the circuit-switched mesh, the circuit-switched non-blocking torus, and finally the circuit-switched matrix crossbar.

4.2.1. Phastlane. The first broadband network we will investigate is Phastlane[Cianchetti et al. 2009], which was designed to provide in-flight routing for opticalsignals for low-latency transmission. It accomplishes this by reading off precomputedheader wavelengths in a control waveguide to route separate data channels. One issuewith this network is that the number of switch hops the data can travel optically islimited to the number of wavelengths that can be used in the control channels. Sincethe control bits are read and retransmitted every other switch, and therefore not lim-ited by insertion loss, we assume the maximum value of eight hops the authors list intheir paper.However, a more serious issue is the time it takes to set up broadband microring

resonators, and the delay along the control path. Once an optical signal arrives to aswitch, the header wavelengths are read off and set to various parts of the electroniccontrol part of the router. In the meantime, the data is propagating up along the datapath. Since there is a significant delay between when the control bits are read and thebroadband switches finish switching (on the order of 12ns for just the switch itself),the data and half of the control bits will have passed the point where they should have



Fig. 8. Phastlane insertion loss analysis versus switch size. (a) Worst-case insertion loss versus microringresonator radius of the switch. Only multilayer network is possible given modulator power limit. (b) Numberof wavelength channels possible in optical power budget versus microring resonator radius of the switch,ultimately limited by modulator optical power limit and FSR to 64, if it were possible to fit on a chip.

switched, and continued on to the next router. This will cause erroneous behavior orduplication of data inside the network, increasing contention and control overhead.Finally, given all the broadband microring resonators necessary to implement each

switch, Phastlane will barely fit on a 2cm 2cm chip. Figure 8(a) shows the inser-tion loss analysis versus switch microring resonator radius. Note that only using thesmallest rings will allow the network to fit on our normalized area of 400mm2, and thatthe single-layer network exhibits too much insertion loss to fit in a single modulatorsoptical power limit. The multi-layer network, by eliminating waveguide crossings, cansupport the network with very low insertion loss. However, if we consider microringresonators that do not use Archimedean spiralling [Xu et al. 2010], which would havehigher insertion loss, only very small microring resonators can be used for a total ofsix wavelength channels, as shown in Figure 8(b). If the chip size were increased tothe point where an 88 network would fit (about 16cm 16cm, which is unrealistic),or Archimedean microring resonators are used (analysis of which are not performedhere due to the different insertion loss characteristics), 64 wavelength channels maybe possible, limited by the FSR of the modulators and filters at the modulators opticalpower threshold. Regardless, using deposited materials results in a 52% reduction ininsertion loss at the multilayer networks modulator threshold, which translates to a96% reduction in injected power, if it were possible in the single-layer network.

4.2.2. Circuit-Switched Mesh. Circuit-switched photonic networks-on-chip were first pro-posed by Shacham et al. [2007], who use a lightweight electronic network for arbitrationand control of the photonic resources. These networks use a relatively small numberof microring resonators to implement full optical connectivity between all networkaccess points. They are also better suited to application domains which require high-bandwidth communication links between cores at very low power.The first purely circuit-switched network we will consider is a simple mesh topology

used in previous work [Hendry et al. 2010]. The topology and photonic elements canbe seen in Figure 9, which have been designed for minimal insertion loss through alow number of waveguide crossings and microring resonator drop port traversals. Thephotonic mesh uses Y-X routing, with a mirrored lightweight electronic mesh behindit for control and resource allocation.Recall that differentmicroring resonator radii of the switch exhibit different insertion

loss characteristics, which affects the insertion loss through the total network, which



Fig. 9. The photonic mesh network topology. (a) A high-level representation of a 44 photonic mesh. Parallellines indicate two unidirectional waveguides, which are paired together to form bidirectional links. Boxesrepresent higher-order photonic components, which are labeled X for 44 nonblocking switch, I for injectiongateway, and E for ejection gateway. Also shown are detail schematics of the (b) 4 4 nonblocking switch,(c) injection gateway, and (d) ejection gateway.

dictates the number of wavelength channels we are able to utilize, which finally affectsthe optimal microring resonator radius of the switch we should use. Because of this,we show the worst-case insertion loss against microring resonator radius of the switchin Figure 10(a). Notice that SL1 is superior for both single and multi layer devices,which exhibits lower through port insertion loss at lower microring resonator radiusof the switch. Also indicated on this graph is the maximum power that a modulatorcan sustain for a single wavelength channel, indicating the maximum insertion lossa network may exhibit. Figure 10(b) shows the number of wavelength channels thatthe optical power budget can support, dictated by the average optical power in theswitch and the photodetector sensitivity. However, this number must be limited to boththe FSR of the switch and the power limit of the modulators. In the end, the single-layer network can support 23 wavelength channels, where the multilayer network cansupport 45, a 95% improvement.

4.2.3. Circuit-Switched Nonblocking Torus. Because a circuit-switched mesh topology isblocking on the network scale, Petracca et al. [2008] proposed a nonblocking torustopology to decrease circuit path setup contention. This topology was later analyzed forinsertion loss [Chan et al. 2010b], and was found to be very infeasible because of theextra photonic resources necessary to implement the nonblocking routing. Modifyingthe original design to use the same injection/ejection layout as the mesh topology, weapply the same analysis, but include a multilayer version.Figure 11(a) shows the worst-case network insertion loss versus switch microring

resonator radius, again showing the modulator optical power limit. We can see thatwith our refined analysis including accurate switch through and drop insertion loss,the single-layer network is not feasible for any microring resonator radius. The mul-tilayer network becomes feasible, though referring to Figure 11(b), it can only use 29wavelengths, limited by the FSR. This network is made possible by the 44% reductionin insertion loss over the single-layer at the multilayers modulator-power limit, whichis an 89% reduction in injected power, if it were possible in the single-layer version.



Fig. 10. Circuit-switchedmesh insertion loss analysis versus switch size. (a)Worst-case insertion loss versusmicroring resonator radius of the switch. (b) Number of wavelength channels possible in optical power budgetversus microring resonator radius of the switch, ultimately limited by modulator optical power limit andFSR.

Fig. 11. Circuit-switched non-blocking torus insertion loss analysis versus switch size. (a) Worst-case in-sertion loss versus microring resonator radius of the switch. Only multi-layer is possible. (b) Number ofwavelength channels possible in optical power budget versus microring resonator radius of the switch,ultimately limited by modulator power limit and FSR.

4.2.4. Circuit-Switched Matrix Crossbar. The final topology that we explore in this workis a full crossbar made from matrix-style switches, which can be seen in Figure 12.This topology utilizes fully non-blocking switches which, when coupled with a one-hopelectrical setup network such as a flattened butterfly, can be used for both low setuplatency and high-bandwidth optical circuits. One drawback is that it utilizes a largenumber of broadband rings, O(N2), so we must make sure that they can all fit on a chipas follows:

SChip N M PWaveguide + RBend + N M (PMicroring + DMicroring) + LTaper . (4)Here, SChip is the size of the chip dimension (2cm), PWaveguide is the waveguide pitch

(20m), RBend is the bending radius for the end -waveguide (20m), PMicroring is themicroring resonator pitch (30m), DMicroring is the microring resonator diameter, andLTaper is the length of the input taper, or optical terminator. Rearranging, we get a



Fig. 12. A 4 4 example of the matrix-crossbar network topology.

maximum microring resonator size of:

DMicroring SChip RBend LTaperN M PWaveguide PMicroring. (5)

For example, for an 88 network, we would have a maximummicroring resonator di-ameter of 261m. Larger microring resonator sizes can be achieved with Archimedeanspiral rings to significantly compact the size [Xu et al. 2010].We perform the same insertion loss analysis on this new topology, resulting in

Figure 13(a). Similar to the non-blocking torus, this new topology is only made feasibleusing deposited materials, limited by modulator optical power. Figure 13(b) shows thataround 32 wavelength channels could be utilized, limited again by the FSR. Again,using deposited materials makes this topology possible by reducing the insertion lossby 58% due to the elimination of waveguide crossings over the single-layer version atthe modulator-limited threshold, which is a 99% reduction in injected power if it werepossible in the single-layer.



Fig. 13. Circuit-switched matrix crossbar insertion loss analysis versus switch size. (a) Worst-case insertionloss versus microring resonator radius of the switch. Only multilayer is possible. (b) Number of wavelengthchannels possible in power budget versus microring resonator radius of the switch, ultimately limited bymodulator power limit and FSR.

Fig. 14. Summary of improvement over single-layer integration for various multilayer network architec-tures.

5. CONCLUSIONSWe have demonstrated the significant impact that deposited silicon materials can haveon various photonic network-on-chip architectures for chip multiprocessors. We haveintroduced the novel use of two CMOS-compatible silicon photonic materials for thispurpose: polycrystalline silicon and silicon nitride. The combined use of these materialsoffers unique advantages over the more traditional crystalline silicon platform, notablylower waveguide propagation loss and the removal of waveguide crossing insertionloss. This enables the development of photonic network topologies with performancecapabilities previously not possible.Figure 14 summarizes the results for various networks by showing the percent im-

provement of the multilayer approaches over the single-layer methods. Most of these



networks exhibit at least 20% improvement in either the number of wavelength chan-nels possible, or the required injected power, and three of the networks are only madepossible with the multilayer approach using deposited materials.

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Received August 2010; revised January 2011; accepted March 2011


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