Photonic Integrated CircuitsOFC 2015 –2nd PIC Workshop 25‐mar‐15 p10 looking at other components, such as modulators and detectors, InPand Silicon Photonics can achieve fairly

2nd Workshop on Photonic Integrated CircuitsPhotonic Integrated Circuits

OFC 25 M 2015OFC, 25‐Mar‐2015

Agenda for the PIC workshop 6:00 PM – 6:10 PM: Welcome and Introduction 6:10 PM – 7:00 PM: Presentation on “Taking Advantage of Merchant Suppliers

to Create Your PIC Products Faster and Cheaper” by Twan Korthorstto C eate ou C oducts aste a d C eape by a o t o st 7:00 PM – 7:10 PM: Question & Answer Session

7:10 PM – 8:00 PM: Networking Break with Buffet and Sponsor Tabletops Enjoy the food and drinks and please roam around and talk to the individual sponsors

8:00 PM – 8:10 PM: Update by the OIDA on the Integrated Photonics Initiative Prepared by Tom Hausken from the OIDA

8:10 PM – 8:55 PM: Use Case Presentations by Pi K t f T h bi Pim Kat from Technobis

Chris Roeloffzen from Satrax Henk Bulthuis from Kaiam Chris Doerr from Acacia All presentations available on

7 i 8:55 PM – 9:00 PM: Closing

25‐mar‐15 p1OFC 2015 – 2nd PIC Workshop

www.7pennies.com

Why this workshop?

Aim is to bring together all the PIC service providers Yes, integrated optics is gaining momentum Yes, integrated optics is gaining momentum So where do you go, if you need to develop a PIC? If you are fabless, then you need at least an (MPW) foundry Also, design S/W, packaging, and/or a turn‐key design house Workshop brings all of these together We do so independent of material system

Adopt a unique format Introductory presentation detailing the PIC ecosystem Include an extended break for networking with providers

h h Have use case presentations who share experiences


Sponsoring PIC service providers Foundries

InP

Silicon Photonics

TriPleX TriPleX

Design software

Packaging

Turn key design houses

Organizers Organizers


Taking Advantage g gof Merchant Suppliers to Create

Your PIC Products Faster and CheaperYour PIC Products Faster and Cheaper

Presented by Twan Korthorst (CEO PhoeniX Software)Presented by Twan Korthorst (CEO PhoeniX Software)on Behalf of All Sponsoring Companies

Agenda for this presentation Why are PICs gaining momentum?

100G coherent and 100G datacom are leading the way But other areas are picking up (sensing, lifesciences, military…)

Introduction to foundry servicesy This includes generic processes and the pros & cons of MPW

Design softwareg Electronic and Photonic Design Automation (EDA & PDA) Specific attention to PDK (process design kit)

Overview of packaging services

Benefits of using a turn‐key PIC design house Benefits of using a turn key PIC design house


What is a photonic IC?(de)multiplexers × 11

PIN × 100 Single Photonic Integrated Circuit

and routing

6 mm × 8 mmFBG sensor unit

A PIC combines several components within a single chip

Benefits are smaller size, lower cost, better manufacturability


Some of the cons can be a trade off in performance and/or yield

So why are PICs gaining momentum? In the past, most of fiberoptics consisted of a LD, a fiber, and a PD

So there simply was little that could be integrated

WDM did not help because transmit lasers were all on different linecardsWDM did not help because transmit lasers were all on different linecards

But 100G telecom/datacom have completely changed the situation Now there is plenty optics in a small formfactor & size constraints require integration

Source: Jon Anderson (Opnext) , Nov.1, 2011 Lightwave


PICs now also picking up in sensing, lifesciences, military, etc

So if you need a PIC, where do you go? You need an application specific PIC

Fiber to the Home Medical Datacom Sensor Wireless Bio‐imaging Switching Readouts

You need to decide on material and foundry You need to decide on material and foundry Options are InP, Silicon Photonics, or TriPleX (leaving PLC & LN)

l d d d Also need to decide on MPW vs. a custom run MPW reduces costs, but custom runs may be needed in the

d (f l f i f )end anyway (for volume or for unique performance)


Deciding between material systems…Passives possible in InP, Silicon, and TriPlex

Switches & modulators possible in InP & Silicon

Active materials (lasers…) only possible in InP

MMI‐couplersMMI reflectorsPhase modulator

SOA

Phase modulator

A li d d l

Fabry‐Perot lasers

Tunable DBR lasers

AWG‐demuxAmplitude modulator

Ring filters

Thermo optic

WDM crossconnectWDM add‐drop

Multiwavelength lasers

OFC 2015 – 2nd PIC Workshop 25‐mar‐15 p9

Thermo optic phase modulatorPicosecond pulse laser

Comparison of MPW processes

Broker Process

Lasers

SOAs

TDBR

Modulators / Phase shifters Detectors Proploss

m)

Pp dB)

Hz) W)

Hz) nA)

mL S T

L (m

m

Vp‐P

Loss (d

B (GH

R(A/

W

B (GH

I dark(n

dB/c

JePPIX Oclaro TxRx 10G YES YES YES 1 3.5 < 2 > 10 0.8 10 2‐3JePPIX HHI Rx 40G 0 5 (25 mW) < 2 (kHz) 0 8 40 < 10 1‐2JePPIX HHI Rx 40G 0.5 (25 mW) < 2 (kHz) 0.8 40 < 10 1‐2JePPIX SMART TxRx 10G YES YES 2 7 < 2 10 0.8 10 < 20 3‐4JePPIX TriPleX (DS‐500‐170) 1‐2 (500 mW) < 0.1 (kHz) < 0.5ePIXfab VTT 3 µm SOI 1 < 0.1 (kHz) 0.1‐0.15PIXf b i ISIPP25G 1 5 8 5 5 11 0 5 50 50 1 5 2 5ePIXfab imec ISIPP25G 1.5 8.5 5 11 0.5 > 50 < 50 1.5‐2.5ePIXfab CEA‐LETI Full Platform 1‐4.7 10 10

TriPleX and VTT 3 µm SOI have the lowest losses. TriPleX is also suitable for i ibl li htvisible light apps

For active components with gain, only InP can be used

When looking at other components, such as modulators and detectors, InP and


When looking at other components, such as modulators and detectors, InP and Silicon Photonics can achieve fairly comparable performance

One can also combine two materials

carrier substrateTriPleX chip

TEC

For exampleLow‐loss waveguides & spot‐size

Vi ibl & NIRfiber feed through

InP Chip

convertersVisible & NIR ranges

InP ChipActive devicesLasers, SOAs, fast modulators + PDs

fiber array

wire bondselectricalconnections

Combine the best of both worlds


Deciding on MPW or custom runs… Multi Project Wafer (MPW) shares cost between users

Photonics MOSIS started MPW now by JePPIX, ePIXfab, and

MOSIS started MPW in Electronics ICs in 1981

Lower cost is ideal for prototyping

b k id l

LioniXin 1981

MPW broker provides complete ecosystem

MPW uses a generic platform

C b b fi i l i l Custom runs may be beneficial in volume Can run more frequently

Can optimize process for better yield or unique performance


MPW relies on generic foundry model MPW users all leverage the same process

This leads to the concept of a generic process Comes with a library of well documented building blocks

“Lego” building blocks allow for virtually all chips >350 PICs developed in generic fabs via MPW runs

There are 3 main MPW brokers: JePPIX for InP: Smart Photonics , Oclaro, and HHI, , ePIXfab for Silicon Photonics: IMEC, LETI, VTT, and IHP LioniX for TriPleX material (Si3N4/SiO2)


3 4 2

Each MPW broker brings its own solution ecosystem

InP PICs: JePPIX MPW ecosystemDesign Fabrication Packaging

UsersApplications

BROKER

FoundriesPackaging

Photonic IC DesignDesign Tools


MPW or custom runs in InP: JePPIX

l d Pure Play III‐V Foundry

Independent

10G Tx/Rx Platform 10G Tx/Rx Platform

SOAs, PIN detectors

Metal interconnects

SOAs

Metal interconnects

Electro‐optic phase shifters

Various passives, AWGs, MMIs

EOPMs

p , ,

C‐band wavelength range

L‐band on requestTunable laser: gas sensing


g g


PDs

40G Receiver Platform (3”, C‐band)

S i i l ti b t t

AWGs

Semi‐insulating substrates

40G pin‐PDs and balanced PDs

Thermo optic phase shifters Thermo‐optic phase shifters

Low‐loss passives, AWGs, MMIs

SSCs up to 10 μmSSCs up to 10 μm Tx/Rx platform (SOA, DFB, DBR,

EAM) under test


100‐channel spectrometer : sensing


12.5G Tx/Rx Platform

SOA t bl DBREOPMs

SOAs

SOAs, tunable DBRs

PIN detectors


EOPMs


Various passives, AWGs, MMIs

SSCs up to 3.5 μmp μ

C‐band wavelength range


Pulse compressor: bioimaging

ePIXfab Silicon Photonics MPW EcosystemCETC38, China

S d D i

USERS, TECH SUPPORT CENTERSDESIGN HOUSES

ACCESS PARTNERS

Mask

Send Design

UsersMask

Integration

WaferDistribution

Fabrication

Optional PackagingFABRICATIONPOST FAB

p g gFABRICATIONPOST FAB

SERVICE


Silicon Photonics @ LetiPassivesSi waveguidesLarge rib waveguides ~ 0.5 dB/cmSingle mode rib waveguides ~ 2 dB/cmg g /

Surface grating couplers 1D & 2D~ 2.5 to 3dB & 3.5 to 4 dB (resp. 1D & 2D) @ 1310 nm~ 3.5 & 5 dB (resp. 1D & 2D) @ 1550 nm

WDMMux & Dmux (4 channels)Actives

Si modulators PN junction‐waveguide in Ring Resonating or MZ structures:

e.g. 2.6V.cm & ‐1.6dB/mm @‐1V3 3V @ 4V & >25GH BW f 2

WDMMux & Dmux (4 channels)IL ~ 3.5dB & X‐Talk < ‐20dB

3.3V.cm@‐4V & >25GHz‐BW for 2mm

Ge on Si‐ photodetectors Surface‐illuminated or Waveguide‐coupled

Responsivity ~ 0.8 A/W, Dark current < 100nA @ 20°C & < 1µA @100°CBW up to 40GHzBW up to 40GHz

Heterogeneous III‐V on Si lasers (*) Tune‐able DBR, DFB, racetracks lasers

DFB @ 1310nm: P Si‐wg > 20mW@20°C, SMSR > 50dBDBR @ 1550nm: P Si‐wg > 20mW@20°C, SMSR > 30dB


@ g @ ,

*Not available yet on MPW

Silicon Photonics @ IMEC

Based on imec 130nm CMOS technology (200mm wafers)

GS

GS

G

25Gb/s, Vpp = 3.5V, Vbias=‐1.75V,

ER = 3.7dB( i l d d d i )

Electro‐Optical Bandwidth >50GHz @‐2.0VDark current <10@‐1 0V RT


(single ended drive) Dark current <10@‐1.0V, RTResponsivity 0.7‐0.9A/W @‐1.0V

VTT’s 3 µm SOI platform Extremely high mode confinement into the Si core

→ Very dense integration (bend radius down to 1 µm)Low propagation loss (0 1 dB/cm)

2x2MMI

220 µmSpiral MZI

→ Low propagation loss (0.1 dB/cm)→ Small polarization and wavelength dependency

SM and low loss operation from 1.2 to 4 µm wavelength End fire coupling to lasers fibers etc with low loss

MMI

End‐fire coupling to lasers, fibers etc. with low loss Interposers and spot‐size converters Hybrid integration with excellent heat sinking

Modulators and PDs to be introduced soon5x10 mm

Modulators and PDs to be introduced soon... MPW runs and dedicated R&D runs in own fab Scalability to low‐cost mass production at VTT

1. Metal mirror2. Rib waveguide3. TIR mirror4 Rib‐strip4. Rib strip

converter5. Vertical taper


MPW or custom runs in TriPleX Photonic ASIC prototypes in TriPleX MPW fab (typically a

run every 4 months)

Low‐loss dielectric waveguides :– silicon nitride– silicon oxide

High Quality Passives (AWG, MZ, ring, ..) Low‐loss waveguides ≤ 0.5 dB/cmLow loss waveguides ≤ 0.5 dB/cm Bend radii 125 µm allow real VLSI Spotsize converters for low coupling loss Thermo Optic Phase modulators

Visible light to IR transparency (405 to 2350 nm) Packaging services for prototypes available via XiO Photonics


Comparison of costs for MPW PICsBroker Process MPW die

size mm2Price EUR

MPWcost/mm2

Chips per wafer

Material

JePPIX SMART TxRx 10 2 x 4.6 4500 500 8 InP

JePPIX HHI Rx 40 3 x 6 5500 300 8 InP

JePPIX Oclaro TxRx 10 2 x 6 12000 1000 8 InP

JePPIX TriPleX 16 x 16 16000* 63 4 Si N /SiOJePPIX TriPleX 16 x 16 16000 63 4 Si3N4/SiO2

ePIXfab VTT 3 µm SOI 5 x 10 8000 160 8 Si

ePIXfab Imec ISIPP25G 2.5 x 2.5 10000 1600 10 Si

ePIXfab CEAL‐LETI Full 3.4 x 3.7 21750 1700 50 Si

InP MPWs: 2”‐ 3” wafers, 50 – 200 chips per waferSili Ph t i MPW 6” 8” f 300 5000 hi f

* 8500 for academia

Silicon Photonics MPWs: 6”‐8” wafers, 300 – 5000 chips per wafer Perception is that Silicon Photonics is more cost effective at high volume (e.g. datacom)

Table shows that InP is cost effective relative to Silicon Photonics


Question is what the high volume is at which cost metrics changes

Design Software and PDKs

PIC Design Software Fortunately, these days really good S/W is available

It goes w/o saying that EDA tools has been made for Electronic ICs Likewise Photonic Design S/W has been created for PICs

But there are in between situations: What if your chip has optical as well as electrical components? What if you plan to do the photonic simulations in PDA, but then use

EDA for the mask layout?EDA for the mask layout? Also, there are ongoing efforts between EDA and PDA providers to

make their S/W interoperable and support the industry to scale from R&D to (volume) manufacturing

Even though some functions (such as layout) can be done using both PDA as well as EDA, some care is needed…


EDA and PDA: Photonics ≠ CMOS Integrated Photonics has “RF‐like” or “analog” behavior, which requires: Accurate and flexible definition of all angle shapes Control of phase (differences)

d d h l Dedicated photonics simulation routines Libraries with parametric photonics building blocks

Special features for verification (DRC LVS) Special features for verification (DRC, LVS)


Why are PDKs so important? When working with a foundry (or your own fab), you do not

want to reinvent the wheel nor make unnecessary mistakesy So all relevant knowledge should be available when designing a PIC And the PDK should be automated (rather than in the form of docs) Without a PDK there are simply too many unneeded iterations Without a PDK, there are simply too many unneeded iterations

What does a PDK include?Design rules and mask layer information Design rules and mask layer information

Library of validated building blocks Simulation models and settings Die and package templates

Photonics PDK standardization by PDAFlow foundation Open standard for all players

25‐mar‐15OFC 2015 – 2nd PIC Workshop p27

A wide variety of PDKs are available Foundries:

Silicon: IMEC, CEA‐Leti, VTT, IHP and IME

InP: FhG/HHI, Oclaro and SMART Photonics

TriPleX (the silicon nitride platform): LioniX

Packaging: Technobis ipps, Chiral Photonics, Gooch and Housego, Linkra, XiO Photonics and Tyndall

Vendors of design S/W have PDKs available to a varying degree

PDKs are typically made available through MPW brokersyp y g


PDKs support design at circuit level Photonic and electrical connections automatically detected

PDK supplied schematic checks for photonic connections PDK supplied schematic checks for photonic connections

Schematic connectivity drives layout directly


PDKs support circuit simulations Bidirectional, multimode and multichannel optical circuits

Frequency domain: scattering data analysisFrequency domain: scattering data analysis

Time domain: transient analysis


PDKs support mask layout generation Design S/W can translate design intent into layout

Design S/W can automatically correct for process deviation Design S/W can automatically correct for process deviation

Use technology information to obtain design intent after fabrication

“ Photonics Synthesis” translates design intent into

DRC clean layout information

Simulating lithographyinfluence on design intent


PDKs can allow for simple portability


PDKs support design verification Functional verification, Design Rule Checking

(DRC) and Layout vs Schematic (LVS)

Built‐in photonics relevant design checks(like minimum bend radius)

Design rules targeting CMOS processes will Design rules targeting CMOS processes will flag thousands of false errors in photonic structures, Photonic specific DRC rules can i i i f lminimize false errors

Integrated design flows enable LVS


PDK development @ IMEC

Device Models

Electrical

EM simulation

Electro‐Optical simulationExtractions:

Schematic / Parasitic

Schematic Driven Layout

Electrical simulation

Process variation simulation

Schematic / Parasitic

LayoutLVS LFD

GDSGDSDRCOptical

proximity correction

Available todayUnder Development

In collaboration with: Courtesy: Imec PDK roadmap


Copyrights reserved

Luceda Design S/W


Why Mentor Graphics Pyxis

No OA database angle restrictionsSt i t ti t C lib Strong integration to Calibre

Flexible framework enables new design methodologiesExcellent custom design assembly Excellent custom design assembly capabilities

C lib Calibre Market and industry standard Equation DRC handles complex curves LVS of arbitrary devices and shapes Calibre LFD enables “short loop”

component analysis


Why PhoeniX Software PhoeniX Software

Has a history going back to 1991 in integrated photonicsy g g g p Focus on software solutions for manufacturability

OptoDesigner Is the dominant tool for photonics layout generation Provides simulations and layout in one user friendly environment to

enable real ‘photonics synthesis’p y Includes photonics verification Interfaces with world‐class 3rd party circuit simulators

Gives access to 8 photonic foundry PDKs Gives access to 8 photonic foundry PDKs


Why Lumerical Lumerical

Photonic design tool provider with 1,110 patent, publication & p ppresentation citations in 2014

INTERCONNECT PIC design environment for

l d l h lmultimode, multichannel bidirectional circuits and systems

Supports time and frequency‐domain circuit analysis 16QAM Transmitter

Extensive library of compact model circuit elements

Component modeling tools FDTD MODE d DEVICEFDTD, MODE and DEVICE Parameter extraction from

photonic component models support compact model generation


PDKs support integration of design flows


Photonics “Unified Design Flow”


Packaging

Packaging and Hybrid integration Packaging needs vary

For some R&D needs, PICs can be tested at the die level And for volume applications, the investment to start in

h k bl ( l k b ld f b)house packaging is manageable (unlike building a fab) But for many users, a good packaging facility is essential

Both optical and electrical (RF) connectionsp ( )

PDKs can also include packaging design rules

MPW foundries offer prototype packagingp yp p g g JePPIX => Linkra, G&H and Technobis ePIXfab => Tyndall LioniX => XiO Photonics Xio

In addition, several dedicated packaging services are available such as Chiral and Technobis

G ll it i iti l t thi k b t k i l Generally, it is critical to think about packaging early


Packaging and Hybrid integration Heterogeneous integration is not simple

But chips for hybrid integration are easily accessible via MPWs

New applications will emerge based on hybrid combinations of platforms. Use the best of all worlds.

E.g. Create active functionality in low loss TriPleX platform => New FP7 initiative PHASTFlex (http://www.phastflex.eu)


Chiral Photonics’ couplers and packaging/ h l h l bl k dminimize I/O chip real estate within scalable, packaging production processes

Single‐ and multi‐channel, high density, fiber array, optical couplers for die edge or surface probing and packagingp g p g p g g Up to 6 channels with spot size conversion to 2µm MFD for edge

coupling Up to 61 channels in single I/O port for surface coupling to VGCs,

VCSELs, PDs Accommodate different design/form factor needs, including:

– Integrated pigtails: SM (edge and surface coupling) or PM (edge coupling)– Pluggable: fiber stub

Packaging Services Packaging Services Development packages: open design for electrical probing Production packages: modified butterfly or other designs Full optoelectronics packaging with microelectronic partners

Ongoing Developments Working with design software houses and foundries: canned edge and

surface I/O fiber array solutions Multicore fiber I/O solutions with Chiral’s commercial fanouts


Multicore fiber I/O solutions with Chiral s commercial fanouts

Technobis’ packaging services High‐end packaging solutions for

stability, reliability and performance, Technobis specializes in:Technobis specializes in: Thermal Management Low‐Noise front‐end electronics Low and medium volumes Low and medium volumes

Generic Test Package Easy accessibility, fast assessment, small pre‐series Few to many electrical and optical I/O (incl RF) Few‐to‐many electrical and optical I/O (incl.RF)

Custom Packaging Extreme performances, in‐package electronics

O ti i d i t f i fib li th l t bilit Optimized interfacing, fiber coupling, thermal stability, costs efficiency

Design rules are published on our website and integrated within the PhoeniX PDKs


within the PhoeniX PDKs

Scaling to Full Production andIntellectual PropertyIntellectual Property

Scaling production beyond prototypes For initial prototyping, MPWs are low cost For volume/optimized performance, custom runs may be best Sticking to the MPW process improves predictability MPW foundries also offer dedicated runs and they have

ti h t l t d tiexpertise how to scale to production Production

phaseRealization

phaseStabilization

phaseOptimization

phaseDemonstration

phaseKnow-how

phase

LioniX BV Strategy scheme © copyright 2002

* Fabrication monitoring

* Yield analysis* Process flow* Manufacturable design* Technical specifications

* Product design* Fabrication plan* Product specs* Quality criteria

* Feasibility* Preliminary design* Preliminary process* Shortloops

* Idea* Market Study* Preliminary product specs* Proof of principle

MASSFABRICATION

FABRICATIONPRODUCTDEVELOPMENT

RUNS

PRODUCTDEVELOPMENT

RUNSTESTRUNS

demonstrator prototype B product‘0' seriesprototype Aconcept


Dealing with intellectual property

Processes are typically owned by the foundry

Chip design/layout is typically owned by the customerp g / y yp y y

Specific foundry design IP is shielded in confidential private building blocks (owned by the foundry)

Process validation is not done on specific device performance: building block validation only

IP rules are similar to electronics industry25‐mar‐15 p48OFC 2015 – 2nd PIC Workshop

Turn‐Key PIC Design HousesTurn‐Key PIC Design Houses

From application idea to PIC prototype

Analyze &

Select

Design & Fab

Test &

PackageSelect Fab Package

Turn‐key PIC design houses can be ideal: if you need specific design support or if you do not have the design capabilities yourself

In addition, they can provide a complete service This includes testing, packaging, and system level evaluation


Design house support 3 phases in 7 steps

Analysis:A t PIC

Circuit & BB

Maskl t

Waferf b TestingSelect

S l ti Packaging

1 2 3 4 5 6 7I II III

App to PIC & BB design

layout fab gSolutions g g

1 2 43

specs

package SoI

5 6 7

InP


Bright Photonics’ design services

25‐mar‐15OFC 2015 – 2nd PIC Workshop 25‐mar‐15OFC 2015 – 2nd PIC Workshop p52

Standard design servicesFabless design house, 12+ years designing PICs

lExcel in design to optimize and reduce risk of failure after fablFast times in consultancy and design turn-aroundlProtect results by confidentiality and IP transferlFull value-chain support: design services, turn-key projects, OEM chip supply

CUSTOMDESIGN

STANDARDDESIGN

DESIGNSUPPORT

lCreation of new IPlRedesign of existing building blockslVery large or complex

lUse only the foundry's PDKlSelect, adapt and layout ~50 standard building blocks

lPhotonic & design consultancylDRC & layout validation over customer's design

layouts

Fab & design prices on line @ www vlcphotonics com/mpw


OFC2015 promo code for 10% discount 25% extra discount for academics

Fab & design prices on-line @ www.vlcphotonics.com/mpw


In conclusionIn conclusion

Summary Integrated optics is gaining momentum

Especially for 100Gbps and above, but also in many other areas

l ll b Developing a PIC can still be expensive… MPW brings down the costs & simplifies the process to create a PIC

Use a detailed automated PDK plus the right design S/W Use a detailed automated PDK plus the right design S/W Choosing the right material is tricky, but MPW services are

available for the most important material systemsavailable for the most important material systems All MPW foundries can seamlessly scale from prototype to

dedicated (custom) production runs. There are a good number of packaging options And with all these efforts together, the field of integrated

optics will gain even more momentum25‐mar‐15 p55OFC 2015 – 2nd PIC Workshop

Agenda for the PIC workshop 6:00 PM – 6:10 PM: Welcome and Introduction 6:10 PM – 7:00 PM: Presentation on “Taking Advantage of Merchant Suppliers

to Create Your PIC Products Faster and Cheaper”to C eate ou C oducts aste a d C eape 7:00 PM – 7:10 PM: Question & Answer Session

7:10 PM – 8:00 PM: Networking Break with Buffet and Sponsor Tabletops Enjoy the food and drinks and please roam around and talk to the individual sponsors

8:00 PM – 8:10 PM: Update on the Integrated Photonics Initiative Tom Hausken from the OIDA

8:10 PM – 8:55 PM: Use Case Presentations by Pi K t f T h bi Pim Kat from Technobis

Chris Roeloffzen from Satrax Henk Bulthuis from Kaiam Chris Doerr from Acacia

8:55 PM – 9:00 PM: Closing


h k !Thanks!www.7pennies.com

Documents

Photonic Integrated CircuitsOFC 2015 –2nd PIC Workshop 25‐mar‐15 p10 looking at other components, such as modulators and detectors, InPand Silicon Photonics can achieve fairly