[email protected] to Electronics Summer 2009 Introduction to Electronics in HEP Experiments Philippe Farthouat CERN

[email protected] to Electronics Summer 2009

Introduction to Electronics in HEP Experiments

Philippe FarthouatCERN


Outline

2

Detector

AnalogTo

DigitalConversion

Data Acquisition &

Processing

AnalogProcessing

On-detectorOn-detector

OrOff-detector

Off-detector

Analog processingAnalog to digital conversionTechnology evolutionOff-detector digital electronics


Analog to Digital ConversionData from a detector needed in digital form for additional

processing, storage and later analysis Analog to Digital

Three type of data Signal higher than a given threshold

1-bit ADC or discriminator Amplitude measurement

e.g. what is the value of a signal after the preamplifier and shaperN-bit ADC

Time measurementWhat is the time between two signals (e.g. time of flight)What is the arrival time of a signal (e.g. drift time in a chamber)What is the duration of a signal (e.g. how long time is a signal above the

threshold [TOT|)Time to digital conversion (TDC)

3


Time to Digital Conversion

IntroductionDiscriminator

DefinitionTime walk Slewing timeDouble-threshold discriminatorConstant fraction discriminator

Different typesTime to Amplitude Converter (TAC)Wilkinson “Direct” measurement

Tests

4


What is to be measured?

Time difference between physics signalsTime of flight between two scintillator hodoscopes

Time difference between a physics signal and a logic signalTime difference between a wire chamber signal and the beam

crossing signalBefore feeding a TDC, a physics signal must be transformed in a

logic signal in phase with it Using normalised electrical levels (e.g. NIM, TTL, ECL, LVDS)

This is the role of the discriminator

5


Discriminator

Input = analog signalOutput = digital signal

After a fixe delay if possible If the signal exceeds a threshold

A discriminator high gain amplifier

6


Example

7


Time walk

Often homothetic signals (e.g PM outputs): constant rise time variable amplitude

The phase of the output signal of a discriminator will depends on the signal amplitude Time walk

Example 10 ns rise time, 10-1000 mV input, 50 mV threshold Time walk about 10 ns

8

Time Walk

-600

-500

-400

-300

-200

-100

0

100

200

0 10 20 30 40 50

Time

Am

pli

tud

e

Input

Output


Slewing time

Assuming a “zero” rise time signalTime walk = 0

Still an effect of amplitude because:The discriminator requires a minimum overdriveThe transit time changes for small overdrives

9

AD 8611

CMP401


Double threshold

Low threshold to give the timing informationMinimise time walkNoise

10

-

+

-

+

Input

High-Thr

Low-Thr

Clk

DReset

Q

Delay

Del

ay

Output

-20

-15

-10

-5

0

5

0 5 10 15 20 25 30 35

Time

Inputs

Comparators Outputs

Thresholds


Constant fraction (1)

Homothetic signal V(t) = A * F(t)

k * V(t) - (t-t0) V(t-t0)Null for t, independent of A

11

-20

-15

-10

-5

0

5

10

15

0 5 10 15 20 25 30 35

Crossing point independant of amplitude


Constant fraction (2)

Timing given by the crossing point k * V(t) = (t-delay) V(t-delay) k is the fraction

Very good performances: no time walk 50mV-1V Limitations

Offset of the comparator Noise Slewing time of the comparator

12

-

+

-

+

Input

High-Thr

Clk

DReset

Q

Delay

Del

ay

OutputDelay

Fraction


Time to amplitude converter

Very good resolution can be achieved (a few ps)

13

Start Set

Reset

Q

StopC

I

ADC

-

+

C

I ) t- (t V stopstart


Wilkinson encoder

Resolution and conversion time function of the clock frequencyOld modules: 25 ps resolution for 100 ns dynamic range

14

-+

0

2

4

6

8

10

12

0 20 40 60 80 100 120 140

Time

Am

pli

tud

e

V


Direct measurementCount number of clock cycles between 2 signalsRequires high speed clock to obtain good resolution

Possible with the new technologies Is even implemented in FPGA (Programmable logic)

Requires some additional interpolation techniques to get high precision

Presentation of a CERN designHigh Precision General Purpose TDC (HPTDC) (J. Christiansen

etal)32-channel TDC

Bin 100, 200, 400 or 800 psDynamic range about 100 ms

15


HPTDC

Based on a 40 MHz Clock Measurement relative to the clock

16


PLL and DLL

Phase Lock Loop (PLL) provides clock multiplication and maintain the phases of the clocks

Delay Lock Loop (DLL) provides 32 clocks delayed by a constant amount Delay: 780 ps, 390 ps, 195 ps, 100 ps depending on the used clock Used to interpolate between two main clock hits (vernier)

17

[email protected] to Electronics Summer 2009 18

Coarse time count

A 15-bit counter gives the coarse timing of the hit with respect to a RESET signal (which could be the START in a start-stop configuration)

Two counters are implemented to take into account the asynchronous nature of the signalThe position of the hit within the clock period is used to select the

good one

[email protected] to Electronics Summer 2009 19

Tests and measurementsTiming resolution

Start-Stop without jitter Integral Linearity

Delay scanningDifferential Linearity

Non-correlated Start-Stop Hit frequency histogramming

Differential non-linearity

98.5

99

99.5

100

100.5

101

101.5

0 20 40 60 80

TDC count

Fre

qu

en

cy

Ideal Frequency

Measured frequency


Introduction to Analog to Digital Conversion

IntroductionConversion errorsDifferent types of A-to-D convertersTrends in our applications

20



Alterations of the signal: Signal is sampled at given instants (sampling time)Continuous amplitude is encoded in a limited number of binary

word, i.e. a binary word represents an interval of amplitude (quantization)

21

Time

Binary code

0000100010

000110010000101

…..



Restitution of the signal with a DAC (Digital-to-Analogue Converter)

Both aspects of the digitisation (Time Sampling and Amplitude Quantization) have to be considered

22

Time

Amplitude


ResolutionRelationship between quantization error, number of bits,

resolution:

23

Binary code

…00000

…00001

…00010

…00011

…00100

…..

Amplitude interval : LSB=A/2n

Ex : 8 bits ADC, 1V Full Scale AmplitudeResolution (LSB) = 1/28 = 3.9 mV (0.39%)

A = maximum amplituden = number of bits

Max Quantization error : Q = +/- LSB/2 (ideal)

Quantization noise : 12LSB

…11111


Dynamic rangeRatio between the minimum and the maximum amplitude to be

measured e.g. calorimeter signal 10 MeV to 2 TeV gives a 2 106 dynamic range

In case of a linear system the dynamic range is related to the number of bits (and hence the resolution) an 8-bit linear ADC has a 256 dynamic range

In case of large dynamic range, linear systems cannot be used: A calorimeter signal in HEP for which the dynamic range could be as high as

2 106 would require a 21-bit linear ADC Some non-linearity is then introduced and there is distinction between

dynamic range and resolution. Do not confuse them!n-bit resolutionN-bit dynamic range (N>n)

example:12-bit resolution for a 16-bit dynamic range means that a signal in the range 1-65000 is

measured with a resolution of 0.02%

24


Resolution & Speed

There is a trade-off between sampling rate and number of bitsThe choice of an ADC architecture is driven by the application

25

Speed (sampling rate)

FlashSub-Ranging

PipelineSuccessive Approximation

RampSigma-Delta

GHz

Hz6 22

bipolar

CMOS

Discrete

Power

>W

<mWNumber of bits


ADC transfer curve

Ideal ADCErrors

Offset Integral non-linearityDifferential non-linearity

26

-2

0

2

4

6

8

10

12

0 2 4 6 8 10 12

Vin

AD

C c

ou

nt


Integral linearity

Non linearity: maximum difference between the best linear fit and the ideal curve

27

0

2

4

6

8

10

12

0 5 10 15

Vin

AD

C c

ou

nt

Vout

Ideal

Linear (Vout)

Non Linearity

0

20

40

60

80

100

120

0 20 40 60 80 100 120


Analog Input

Code

+0.5LSB DNL

-0.6LSB DNL


Least Significant Bit (LSB) value should be constant but is not

28


98.5

99

99.5

100

100.5

101

101.5

0 20 40 60 80

ADC count

Fre

qu

en

cy

Ideal Frequency

Measured frequencyADCbitn2

V LSB 1

n

max

Easy way of seeing the effectRandom input covering the full range Frequency histogram should be flatDifferential non-linearity introduces structures


ADC errors : Missing code, monotonicity

Other conversion errors : non-monotonic ADCMissing code

29

Missing code

Non-monotonic


Effective number of bits

Effective number of bit of an n-bit ADC n’ giving the correct SNR

Example: AD9235 12-bit 20 to 65 MHz SNR = 70 dB Effective number of bits = 11.4

30

0

0.5

1

1.5

2

2.5

3

3.5

0 0.5 1 1.5 2 2.5 3 3.5

(x)q

dxxq

1

2

q

2

q

2

q

2

q22

12

q

€

2 =q2

12=

A2

12× 22n

dB8.1n6

212

A8

A

log10x

log10SNR

n2

2

2

2

2

An n-bit ADC introduces a quantization error

Encoding a signal x= (A/2) sinwt with A being the full scale will give an error

Signal to Noise Ratio


Types of ADC

Flash ADC & Subranging Flash ADCPipeline ADCSuccessive Approximation ADCRamp ADCSigma-Delta

31


Flash ADC

Signal amplitude is compared to the set of 2n referencesDirect “thermometric” measurement with 2n-1 comparatorsTypical performance:

4 to 10 bits (12 bits rare)Up to GHz (extreme case)High power (2n comparators) typ. Watts

32

Sampling


Sub-ranging Flash ADC

Typical performance: 4 to 10 bits Up to 100 MHz Less power, but difficult analogue functions

(sample and hold, subtraction, DAC)

33

4-bits + 4-bits sub-ranging flash needs 30 comparators(instead of 255 for 8-bits flash)

Required

Half-Flash ADC 2-step Flash ADC technique

1st flash conversion with 1/2 the precision Residue calculation (1st flash conversion result reconstructed with a DAC and

subtracted from signal) Residue flash conversion


Pipeline ADC

Pipeline ADC Input-to-output delay = n clocks for n stagesOne output every clock cycle (as for Flash)Saves power (N comparators)Typ. 12 bits 40MHz 200mW

34

S&H

Comparator 1-bit DAC

-X 2

1-bit

S&H Stage 1 Stage 2 Stage 3 Stage N

Time Adjustment & Digital Error Correction

1-bit 1-bit 1-bit 1-bit

N-bit

Input

…………

Sampling


Successive approximation

Compare the signal with an n-bit DAC outputChange the code until

DAC output = ADC inputAn n-bit conversion requires n stepsRequires a Start and an End signalsTypical conversion time

1 to 50 µsTypical resolution

8 to 12 bitsOne comparatorPower

10 mW

35

S&H

Sampling

Input


Ramp ADC Start to charge a capacitor at

constant current Count clock ticks during this time Stop when the capacitor voltage

reaches the input Very slow, can reach very high

resolution (1s, 18 bits) with some further tricks (dual slope conversion)

36

02468

101214161820

0 2 4 6 8 10 12 14 16

Time

Vo

lta

ge

acc

ross

th

e c

ap

aci

tor

Vin

Counting time

(What’s used in digital multimeter)

S&HInput


Over-sampling ADC

Assuming the error is a white noise, its power spectral density is flat within the range [–fs/2,fs/2] (fs being the sampling frequency)

If fs/2 is higher than the maximum frequency f0 of the signal, then after filtering the quantization noise left in the signal frequency band (<f0) is :

37

0

0.5

1

1.5

2

2.5

3

3.5

0 0.5 1 1.5 2 2.5 3 3.5

(x)q

12

qdxx

q

1

2

q

2

q

2

2

q

2

q22

bitsofnumberthenandscalefullthebeingAwithf

fA

f

f

sn

s

00 2

12

1

2

2

-fs/2 +fs/2f

|(f)|

sf

1

12

q

fs/2fs/2


Over-sampling ADC (cont)The signal to noise ratio when encoding a signal with maximum

frequency f0 with sampling at fs

Hence it is possible to increase the resolution by increasing the sampling frequency and doing the proper filtering

Example :an 8-bit ADC would become a 12-bit ADC with an over-sampling

factor of 250 (!)But it is not an effective mean of increasing the resolution, because

the 8-bit ADC must meet the linearity requirements of a 12-bit ADC

38

bitsofnumbereffectivethebeingnnSNR

dBf

fnSNR s

''68.1

2log1068.1

0


Sigma-Delta ADC

Over-sampling ADC using a feedback loop to further reduce noise in the low-frequency range have been developed : the most common today is the Sigma-Delta Converter

The feedback loop provides a further “noise shape” with effective noise reduction in the signal frequency band

39

1-bit ADC

1-bit DAC

-Input Output

1rst Order Sigma-Delta Modulator


Sigma-Delta ADC

This architecture is highly tolerant to components imperfectionsWith strong Noise shaping and high linearity capability, Sigma-

Delta modulators are capable of very high resolution (up to 24 bits)

However some other limitations may appear and several complex architectures are derived from the “basic” schema

40

1-bit ADC

1-bit DAC

-Input Output



Sigma-Delta ADC

The output of this modulator is a digital stream, whose average value is an approximation of the input signal.

Quantization error in case of a first-order S-D converter:

41

1-bit ADC

1-bit DAC

-Input Output


36 OSR

A (Over-sampling ratio OSR=fs/2f0)


Sigma-Delta ADC (cont)

The signal to noise ratio when encoding a signal (A/2) sinwt, with A being the full scale, will be

Gain of 1.5 bits per each doubling of OSROSR = 2400 to have a 16-bit ADC

Higher orders sigma-delta are implemented to reduce OSR

Examples (Analog Devices)16-bit, 2.5 MHz24-bit, 1kHz

42

€

SNR=10logx 2

ε 2

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟=10log

A2

8π 2

36

A2

OSR3

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟=10log

36OSR3

8π 2

⎛

⎝ ⎜

⎞

⎠ ⎟= 30logOSR−3.4 dB

SNR=1.8+6n' n' being theeffectivenumberof bits


Shannon Theorem

A signal x(t) has a spectral representation |X(f)|; X(f) = Fourrier transform of x(t)

A signal x(t) after having been digitised at the frequency fs, has a spectral representation equal to the spectral representation of x(t) shifted every fs

If X(f) is not equal to zero when f > fs/2, there is spectrum overlapping Shannon theorem says that x(t) can be reconstructed after digitisation if the

digitising frequency is at least twice the maximum frequency in x(t) spectral representation

This is mathematical only as it supposes perfect filtering

43

-150 -100 -50 0 50 100 150

|X(f)|

Fre

qu

ency

[M

Hz]


Example (1)

“Typical” physics pulse100 ns rising and falling edge

Effect of a digitisation at 10 MHz and 20 MHz 44

X(f)

-20

0

20

40

60

80

100

120

-60 -40 -20 0 20 40 60

Frequency (MHz)

x(t)

-2

0

2

4

6

8

10

12

-30 -20 -10 0 10 20 30

Time (*10 ns)

Digitisation at 10 MHz

-20

0

20

40

60

80

100

120

-60 -40 -20 0 20 40 60

Frequency (MHz)


-20

0

20

40

60

80

100

120

-60 -40 -20 0 20 40 60

Frequency (MHz)


Example(2)

100 ns square pulseDigitisation at 10 MHz and 20 MHz

45

0

2

4

6

8

10

12

-30 -20 -10 0 10 20 30

time (*10 ns)

x(t)

-40

-20

0

20

40

60

80

100

120

-50 -40 -30 -20 -10 0 10 20 30 40 50

Frequency (MHz)

X(f

)


-40

-20

0

20

40

60

80

100

120

-60 -40 -20 0 20 40 60

Frequency (MHz)

X(f

)


-40

-20

0

20

40

60

80

100

120

-60 -40 -20 0 20 40 60

Frequency (MHz)

X(f

)


Using sampling ADC

Don’t forget to make a frequency analysis of the signal Any spectrum overlapping introduces noiseTake into account the effective number of bits

Filtering is necessaryBefore digitisation (analog) to cut the input signal frequency

spectrumAfter digitisation (digital) to extract the signal frequency

spectrum and to compensate the effect of digitisation over a finite time window

46

0

2

4

6

8

10

12

-30 -20 -10 0 10 20 30

Measurement window (-T0, +T0)

x(t)

-T0 +T0

-40

-20

0

20

40

60

80

100

120

-50 -40 -30 -20 -10 0 10 20 30 40 50

Frequency

1/2*T0


Trends in digitisation

We see more and more the digitisation happening “as soon as possible” in the readout chainMinimises the difficult problems of handling analog data

NoiseNeeds for keeping data for a while before a trigger decision arrives

e.g. in LHC experiments, data stored every 25ns (Bunch crossing period) and trigger decision after sevral µs

Complex filtering for noise optimisation, tails cancelation, … can be done in a digital way in a very efficient and flexible way

47


Examples of early digitisation

ALICE TPC readout chip (ALTRO) 16 ADC 10-bit 20MHz

digitised the preamplifier-shaper output

Digital filtering implemented in the chip

CMS electromagnetic calorimeter 12-bit 40MHz ADC Dynamic range extended

with a 4-gain shaper4 ADC per channel

48

AD

Selection logic

AD

AD

AD

AD41240Quad 12-bit converter

Shapers

Low noise preamp

Quad Preamp-Shaper

DigitalLogicAndSerial TX

14

CMS Calorimeter


Future projects with early digitisation

Super ALTRO for reading out a Linear Collider TPC32 or 64 complete channels including the preamplifiers, the 10-

bit 10MHz ADC and the digital data processingUpgrade of the ATLAS calorimeters for sLHC

Coding at 40 MHz, 14–16-bitAbout 200000 channels

For all these applications, very low power ADC are needed

That’s now possible thanks to the evolution of technologies

49

Documents

[email protected] to Electronics Summer 2009 Introduction to Electronics in HEP Experiments Philippe Farthouat CERN