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Dissertation Huai Wang
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CITY UNIVERSITY OF HONG KONG 香港城市大學
New Energy-efficient High-voltage
DC-DC Power Conversion Technology
新型高效能高電壓直流功率變換技術
Submitted to Department of Electronic Engineering
電子工程學系 in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy 哲學博士學位
by
Wang Huai 王懷
March 2012 二零一二年三月
Copyright 2012 by Huai Wang All Rights Reserved
Abstract- i
ABSTRACT
This thesis presents the findings of research on new high-voltage medium-power
dc-dc conversion technologies. A current-fed full-bridge step-up high output voltage
converter and two multi-level step-down high input voltage converters have been
investigated. A switched-capacitor snubber is proposed for zero-current-switching (ZCS)
of the four IGBTs in the full-bridge converter. The ZCS can be achieved with minimum
circulating current under different loading condition due to the self-adaptable resonant
energy in the snubber. Two kinds of energy-efficient solutions are presented to perform the
conversion from high input voltage to low output voltage. One is by using a multi-level
multi-phase topology with zero-voltage-switching (ZVS) to reduce the voltage stress on the
primary-side switches and improve the output current capacity. The other is by employing
a three-level converter featured with different voltage stresses on the two series-connected
switch pairs, allowing optimal selection of switching devices and wide soft-switching load
range. In practice, the low output voltages of the high-voltage converters are usually used
to supply various low-voltage converters which are exposure to momentary loads. To
improve the dynamic response, a generalized fast transient controller is proposed for
different type of low-voltage converters based on the derivation of a uniform second-order
switching surface. The considerable power loss and short lifetime of aluminum electrolytic
capacitors in power converters impose massive challenges to push up efficiency and
lifetime. Therefore, a novel concept to reduce the dc-link capacitance by introducing a
voltage compensator connecting in series with the dc bus line is proposed and studied. It
explores the possibilities to replace the electrolytic dc-link capacitors in high-voltage power
converters by long lifetime low power loss film capacitors without sacrificing power
Abstract- ii
density and cost effectiveness.
The contents of this thesis are as follows:
In Chapter 1, the motivation of the research on high-voltage medium-power dc-dc
converters will be discussed. Prior-art approaches to improve the efficiency of power
converters will be reviewed from component level, circuit level to system level. The
principle and associated application limitation of switching surface control for dc-dc
converters will be illustrated. Available concepts and solutions to reduce dc-link capacitors
in power electronic systems will be presented.
In Chapter 2, the concept of adaptive snubber energy for ZCS will be presented.
The operating principles of the proposed current-fed full-bridge converter will be described.
The trade-off design and small-signal model will be given. Implementations and
evaluations of a 530 V / 15 kV 5 kW experimental prototype will be discussed.
In Chapter 3, a solution for high-to-low voltage conversion based on a generalized
multi-level multi-phase topology will be discussed. The switching mechanism and
operation of a typical switch pair will be analyzed. A dc analysis will be carried out to
determine the dc conversion ratio and the ZVS conditions in an analytical form. The self-
balance property of the voltages across the input capacitors will be described. A 1500 V /
48 V, 2 kW prototype with four switch pairs in the primary-side is designed, implemented,
and evaluated.
In Chapter 4, another solution to convert 1500 V dc to 48 V dc will be presented
based on a novel concept, by which the voltage stresses on the series-connected two switch
pairs are asymmetric. The advantages of a three-level converter adopted the proposed
concept will be illustrated in terms of utilization of switching devices and load range for
Abstract- iii
soft-switching. A new concept of hybrid ZVS-ZCS scheme will be proposed. The
evaluations on a 2 kW prototype will be given to verify the theoretical predictions.
In Chapter 5, a uniform second-order switching surface for a fast transient controller
of dc-dc converters will be derived. Stability analysis and controller implementation will
be discussed. Simulation results on four kinds of dc-dc converters (i.e., boost converter,
buck-boost converter, Ćuk converter and SEPIC) will be presented to verify the universal
applicability of the proposed control method. Experimental results on a 48 V/48 V buck-
boost converter prototype will be also analyzed to exhibit the performance of the controller.
In Chapter 6, a patent-pending technology for reducing dc-link capacitance in
capacitor-supported power electronic systems will be presented. The operation principle
and implementation of the proposed voltage compensator will be discussed. Simulation
and experimental results will be provided to verify the theoretical analysis.
In Chapter 7, conclusions and suggestions for future research on this topic will be
given.
ACKNOWLEDGEMENT
I would like to thank many people who made the work described here possible.
First of all, my gratitude is due to my supervisor Prof. Henry S. H. Chung, for his
choice to recruit me as a research student in 2007, for his sparkling ideas that brought me
into the world of power electronics and for his kind guidance and support during my study
at the City University of Hong Kong. The philosophy he embraces will continue to benefit
me both in research and life.
I am also deeply grateful to Prof. Adrian Ioinovici at Holon Institute of Technology,
for his critical questions in every single discussion, for his patient instructions from a single
word to a full research paper and for his encouragement during my research and life.
I would like to thank Prof. Ron S. Y. Hui, Dr. Wei Yan, Dr. Ricky W. H. Lau, Dr.
Norman C. F. Tse and Dr. K. F. Tsang, for their kind help during my study. I would like to
thank all of other research students and staff at the Centre for Power Electronics for their
help and friendship every single day. I am grateful to Dr. Carl Ho and Dr. Francisco
Canales for their professional supervision during my internship at ABB Corporate Research
Center, Switzerland.
I would also like to thank Prof. Jason Lai from Virginia Tech, USA, Prof. Ashoka K.
S. Bhat from University of Victoria, Canada and Dr. L. F. Yeung from City University of
Hong Kong, Hong Kong, for serving on my Ph.D. oral examination committee.
Finally, my heartfelt appreciation goes toward all of my family members, who are
always there for me with their support and encouragement throughout my education.
TABLE OF CONTENTS
ABSTRACT
ACKNOWLEDGEMENT
TABLE OF CONTENTS
CHAPTER 1 OVERVIEW AND BACKGROUND OF RESEARCH ...................... 1
1.1. INTRODUCTION ................................................................................................... 1
1.2. COMPONENT LEVEL ........................................................................................... 3
1.2.1. MOSFET and IGBT .................................................................................... 3
1.2.2. Aluminum Electrolytic Capacitor and Power Film Capacitor .................. 6
1.3. CIRCUIT LEVEL .................................................................................................. 7
1.3.1. Switch Pairs and Their Combinations ....................................................... 7
1.3.2. Soft-Switching Technology ....................................................................... 10
1.3.3. Selection of Topology ............................................................................... 12
1.4. SYSTEM LEVEL ................................................................................................ 14
1.4.1. Single-Step Conversion Concept .............................................................. 14
1.4.2. Fast Transient Control Methods for Load Converters ............................. 16
1.4.3. E-Cap Reduction Technology ................................................................... 20
1.5. ORGANIZATION OF THE THESIS ......................................................................... 24
CHAPTER 2 HIGH OUTPUT VOLTAGE ZCS CURRENT-FED FULL-BRIDGE
CONVERTER WITH SELF-ADAPTABLE SOFT-SWITCHING
SNUBBER ENERGY ............................................................................... 26
2.1. INTRODUCTION ................................................................................................. 26
2.2. CURRENT-FED ZCS FB CONVERTER AND ITS OPERATION PRINCIPLE .............. 27
2.2.1. Circuit Structure ....................................................................................... 27
2.2.2. Steady-State Operation Modes ................................................................. 28
2.3. STEADY-STATE ANALYSIS ................................................................................ 35
2.3.1. ZCS Conditions ........................................................................................ 35
2.3.2. DC Conversion Ratio ............................................................................... 35
2.3.3. Maximum Voltage across the Snubber Capacitor Cr ............................... 38
2.3.4. Duration of the Snubber Capacitor Charging / Discharging Intervals ... 39
2.3.5. Regulation and Soft-Switching Boundaries ............................................. 39
2.4. SMALL-SIGNAL ANALYSIS AND CONTROLLER DESIGN ..................................... 42
2.4.1. Small-Signal Model and Open Loop Transfer Functions ........................ 42
2.4.2. Controller Design ..................................................................................... 44
2.5. DESIGN PROCEDURE AND EXPERIMENTAL VERIFICATION ................................. 47
2.6. CHAPTER SUMMARY ........................................................................................ 59
CHAPTER 3 HIGH INPUT VOLTAGE MULTI-LEVEL MULTI-PHASE DC-DC
CONVERTER .......................................................................................... 60
3.1. INTRODUCTION ................................................................................................. 60
3.2. GENERALIZED CIRCUIT STRUCTURE AND ITS OPERATION PRINCIPLE ............... 61
3.2.1. Circuit Structure ....................................................................................... 61
3.2.2. Operation Principle ................................................................................. 62
3.3. STEADY-STATE ANALYSIS ................................................................................ 72
3.3.1. DC Voltage Conversion Ratio and Duty Cycle Loss ................................ 72
3.3.2. ZVS Load Range ....................................................................................... 73
3.3.3. Self-Balancing Mechanism of Switch-Pair Voltage ................................. 73
3.3.4. Steady-State Current Distribution in the Transformer Windings ............. 76
3.4. DESIGN CONSIDERATIONS ................................................................................ 78
3.4.1. Design Specifications ............................................................................... 78
3.4.2. Turns Ratio of the Isolation Transformer (m) .......................................... 79
3.4.3. Design of the Value of the Leakage Inductance (Llk) ............................... 79
3.4.4. Design of Output Inductors (Lf) ............................................................... 81
3.4.5. Design of Output Capacitor (Co) ............................................................. 82
3.4.6. Design of Input Capacitors and DC-Blocking Capacitors ...................... 82
3.4.7. Selection of MOSFETs and Diodes .......................................................... 84
3.5. EXPERIMENTAL VERIFICATIONS ....................................................................... 85
3.6. CHAPTER SUMMARY ........................................................................................ 92
CHAPTER 4 HIGH INPUT VOLTAGE THREE-LEVEL DC-DC CONVERTER
WITH ASYMMETRIC VOLTAGE DISTRIBUTION ON SWITCH
PAIRS ........................................................................................................ 93
4.1. INTRODUCTION ................................................................................................. 93
4.2. CONVERTER WITH ASYMMETRIC VOLTAGE DISTRIBUTION............................... 94
4.2.1. Circuit Structure ....................................................................................... 94
4.2.2. Conversion Concept with Asymmetric Voltage Distribution .................... 95
4.3. OPERATION PRINCIPLE OF THE PROPOSED CONVERTER .................................... 96
4.4. STEADY-STATE ANALYSIS .............................................................................. 120
4.4.1. Steady-State Voltage Stress on Cb .......................................................... 120
4.4.2. Voltage Conversion Ratio ....................................................................... 120
4.4.3. Voltage Distribution across Switch Pairs ............................................... 122
4.5. DESIGN GUIDELINES ...................................................................................... 123
4.5.1. Design Issues .......................................................................................... 123
4.5.2. Boundaries of the Design Parameters ................................................... 128
4.5.3. Optimal Design ...................................................................................... 130
4.6. PROTOTYPE AND EXPERIMENTAL VERIFICATIONS .......................................... 134
4.7. CHAPTER SUMMARY ...................................................................................... 144
CHAPTER 5 A UNIFORM FAST TRANSIENT CONTROLLER FOR DC-DC
CONVERTERS ...................................................................................... 145
5. 1 INTRODUCTION ............................................................................................... 145
5. 2 UNIFORM SECOND-ORDER SWITCHING SURFACE ........................................... 146
5.2.1. Derivation of Uniform Second-Order Switching Surface ...................... 146
5.2.2. Stability Analysis .................................................................................... 157
5.3. DERIVATION AND IMPLEMENTATION (FOR BUCK-BOOST CONVERTER) ........... 162
5.4. STEADY-STATE CHARACTERISTICS (FOR BUCK-BOOST CONVERTER) ............ 165
5.4.1. Switching Frequency .............................................................................. 165
5.4.2. Output Voltage ........................................................................................ 169
5.5. EXPERIMENTAL VERIFICATIONS ..................................................................... 171
5.6. CHAPTER SUMMARY ...................................................................................... 178
CHAPTER 6 A DC-LINK MODULE FOR REDUCING DC-LINK CAPACITANCE
.................................................................................................................. 179
6.1 INTRODUCTION ............................................................................................... 179
6.2 BASIC CONCEPT OF THE PROPOSED DC-LINK MODULE ................................. 180
6.3 STEADY-STATE DC AND AC ANALYSIS .......................................................... 181
6. 4 SERIES-CONNECTED VOLTAGE COMPENSATOR .............................................. 183
6.4.1 Impementation ........................................................................................ 183
6.4.2 Analysis of the Voltage Compensator ..................................................... 184
6. 5 DESIGN OF CAPACITORS FOR DC-LINK AND THE VOLTAGE COMPENSATOR .... 188
6.5.1 Design of the DC-Link Capacitor .......................................................... 188
6.5.2 Design of the Input Capacitor of the Voltage Compensator .................. 189
6. 6 SIMULATION AND EXPERIMENTAL VERIFICATIONS ......................................... 190
6.6.1 Simulations ............................................................................................. 190
6.6.2 Experimental Verifications ..................................................................... 194
6. 7 CHAPTER SUMMARY ...................................................................................... 197
CHAPTER 7 CONCLUSIONS AND SUGGESTIONS FOR FURTHER RESEARCH
.................................................................................................................. 198
7.1. SUMMARY OF THE THESIS .............................................................................. 198
7.2. MAJOR CONTRIBUTIONS ................................................................................ 199
7.3. SUGGESTIONS FOR FURTHER RESEARCH ........................................................ 200
APPENDIX A .............................................................................................................. 201
A.1 DERIVATION OF Eq. (4.34) .............................................................................. 201
A.2 DERIVATION OF Eq. (4.37) AND Eq. (4.39) ...................................................... 202
A.3 DERIVATION OF Eq. (4.38) AND Eq. (4.40) ...................................................... 204
PUBLICATIONS FROM THIS THESIS ................................................................. 205
REFERENCES ............................................................................................................ 208
Chapter 1-1
CHAPTER 1
OVERVIEW AND BACKGROUND OF RESEARCH
1.1. Introduction
The objective of this work is to provide essential basis for achieving energy-efficient
and environmental-friendly high-voltage dc-dc converters. Specifically, research on circuit
topology, soft-switching scheme, fast transient control method and electrolytic capacitor
reduction technology has been carried out.
The evolution of modern power electronics has witnessed its fast expanding in
emerging applications and its indispensable role in processing electric energy [1]-[4].
Extensive technological advancement in power electronic converters has significantly
improved the conversion efficiency and quality of electric power. Many efforts have been
made to the research on low-voltage power converters (below 1000 V) to push up the
efficiency, power density or switching frequency [5]-[15]. However, the research pace on
high-voltage power converters, especially on the high-voltage dc-dc converters, is much
less notable. High-voltage dc-dc converters are crucial parts in systems such as medical X-
ray diagnostic equipment [16], traveling wave tube amplifiers [17], electric railway [18]-
[19], etc.
One of the key challenges in high-voltage dc-dc converters is that the advancement
of high-voltage switching devices is less impressive than that of low voltage ones in terms
of power loss, switching speed, reliability, availability and cost. Therefore, the circuit level
performance is limited due to the relatively low allowable switching frequency and high
power loss of high-voltage switching devices.
Chapter 1-2
Fig. 1.1 shows the block diagram of a typical switched-mode power converter.
Various topologies are formed by combining five different types of components in different
ways. The performance of the converter depends on the selected components and topology
and the applied control scheme. When a power conversion system consisting of more than
one converter is considered, the system performance depends on both the converters and
the electrical architecture of the system. Therefore, it is necessary to investigate into the
suitability of devices, corresponding topologies as well as specific power conversion
systems to tackle the challenges in high-voltage dc-dc power conversions.
Fig. 1.1 Block diagram of a typical switched-mode power converter.
In the following three sections, the challenges and opportunities in the research on
high-voltage medium-power dc-dc converters are analyzed at component level, circuit level
and system level, respectively.
Chapter 1-3
1.2. Component Level
The evolution of power electronics lies heavily in the advancement of the
components used, especially the power semiconductor devices, capacitors and high
frequency magnetic elements. This section gives a brief introduction of some aspects of
the components which are critical to the circuit level performance in this research work.
1.2.1. MOSFET and IGBT
Among various types of switching devices, the power metal-oxide-semiconductor
field effect transistor (MOSFET) and insulated gate bipolar transistor (IGBT) are widely
used in the modern power converters.
1) On-state characteristics
During the on-state interval, the on-state resistance (i.e., rDS_on) of MOSFET and on-
state saturation voltage (i.e., VCE, sat) of IGBT induce forward voltage and thus conduction
losses. Fig. 1.2 represents the on-state characteristics of typical MOSFET and IGBT
graphically shown in [21]. The power density limit of 100 W/cm2 is constrained by the
power dissipation and thermal management. According to Fig. 1.2, it can be noted that
a) The on-state current density is compromised by the on-state voltage drop.
b) For a given high on-state current density, IGBT has superior performance than
MOSFET in terms of on-state voltage drop, therefore, conduction loss is lower.
c) For a given current density, the on-state voltage drop VDS_on, thus the on-state
resistance rDS_on, increases significantly with the blocking voltage rating. As
discussed in [22], for high-voltage N channel MOSFET, rDS_on is approximately
given by
Chapter 1-4
7 2.5
_
6.0 10( )b
DS on
Vr
A
(1.1)
where Vb is the rating of blocking voltage in volts and A is the die area in mm2. It should be
noted that with the introduction of vertical super-junction MOSFET [22] and CoolMOS
technology [23], rDS_on can be reduced significantly, however, only for MOSFET with
voltage ratings up to 800 V. From this perspective, high-voltage MOSFET is unsuitable
for high voltage applications due to the high rDS_on.
Fig. 1.2 Comparison of the on-state characteristics of IGBT and MOSFET structures with
different blocking voltage ratings [21].
Chapter 1-5
2) Switching characteristics
According to the above analysis, IGBT has better performance than MOSFET
regarding the on-state characteristics for high voltage applications. However, the switching
speed of IGBT is normally slower than that of MOSFET, which is mainly due to their turn-
off switching characteristics. Fig. 1.3 shows the simplified model of IGBT. It can be
considered as the combination of MOSFET and BJT. A tail current [24] appears during
turn off transition as shown in Fig. 1.4 due to this structure. Therefore, MOSFET is
superior to IGBT in terms of switching speed and turn-off switching loss. It is more
suitable for high frequency operation, which is crucial to achieve high power density
converters.
Fig. 1.3 Simplified IGBT model.
Chapter 1-6
Fig. 1.4 Typical turn-off transitions of MOSFET and IGBT with inductive load.
It imposes the specific challenge to select proper switching devices in high-voltage
medium-power converters as the compromised performance between the on-state
characteristics and switching characteristics of both MOSFET and IGBT.
1.2.2. Aluminum Electrolytic Capacitor and Power Film Capacitor
A typical power conditioning system consists of multiple power converters
interconnected by a dc-link capacitor bank. Among different types of capacitor, aluminum
electrolytic capacitors are widely chosen for the capacitor bank because of their high
volumetric efficiency and low cost.
Advances in film capacitor technology in the last two decades are emerging to be
applied for dc-link filtering [26]-[27]. Table 1.1 shows a comparison between the
aluminum electrolytic capacitor and power film capacitor for the dc-link. Power film
Chapter 1-7
capacitors outperform aluminum electrolytic capacitors counterparts in terms of ESR,
tolerance, self-healing capability, life expectancy, environmental performance, dc-blocking
capability, ripple current capability and reliability. However, the capacitance of the high-
voltage film capacitors still cannot compete with electrolytic capacitors, due to their
relatively low volumetric efficiency and high cost. Therefore, it imposes obstacles to offer
high power density, high reliability and cost-effective solutions.
Table 1.1 Comparisons between aluminum electrolytic capacitors and film capacitors.
Aluminum electrolytic
capacitors Power film capacitors
volumetric efficiency 5-10 times (typical) relatively low
voltage ratings from low to 700 V [25] from low to 100 kV
capacitance tolerance ±20% (typical) ±5%, ±10% (typical)
ripple current 20 mA/ μF (typical) 1 A/ μF (typical)
ESR** 60 times (typical) [25] Low
lifetime 2,000 hours * (typical) 100, 000 hours* (typical)
cost relatively low 5-10 times (typical)
*Under rated conditions. ** Equivalent series resistance.
1.3. Circuit Level
In this section, switch pairs, topologies and associated soft-switching schemes for
high voltage applications are evaluated.
1.3.1. Switch Pairs and Their Combinations
A switch pair is composed of two switches connected in series and driven by
complementary gate signals. Fig. 1.5 shows three possible switch pairs using MOSFETs
and IGBTs.
Chapter 1-8
Fig. 1.5 Three types of switch pair (MOS: MOSFET).
For medium to high power applications requiring input-output electrical isolation,
converters containing switch pairs are usually adopted. The most popular structure is the
full-bridge (FB) converter [28]-[29] with two switch pairs connected in parallel as shown in
Fig. 1.6(a). Several FB converters can be connected in input-series-output-parallel (ISOP)
to obtain a modular-based converter [30]-[33]. Another one is the three-level (TL)
converter [34]-[43] with two switch pairs connected in series so as to withstand high input
voltage as shown in Fig. 1.6(b). The two switch pairs in Fig. 1.6(b) can be extended to
multiple ones to form multilevel converters [44]-[47].
(a) Full-bridge converter.
Chapter 1-9
(b) Three-level converter.
Fig. 1.6 Topologies with switch pairs connected in parallel and in series.
Table 1.2 tabulates the possible combinations of the switch pairs in the FB, TL and
multilevel converters. For switch pair formed by two different types of switches, for
examples, in Cases 2 and 5 listed in Table 1.2, the maximum operating voltage is
determined by the switch with the lower voltage rating in the switch pair. The maximum
limit of the input voltage and the optimal soft-switching scheme for each case are provided.
Table 1.2 Analysis of different combinations of switch pairs.
Combination of switch pairs
(Voltage ratings: MOS-V1, IGBT-V2)
(Assume V1 < V2)
Input voltage limitations
Optimal soft-switching scheme*
Voltage distribution
between switch pairs
In parallel
(FB)
Case 1 Two MOS-MOS V1 ZVS
Symmetric
Case 2 Two MOS-IGBT V1 ZVZCS
Case 3 Two IGBT-IGBT V2 ZCS
In series
(TL)
Case 4 Two MOS-MOS 2V1 ZVS
Case 5 Two MOS-IGBT 2V1 ZVZCS
Case 6 Two IGBT-IGBT 2V2 ZCS
Case 7 IGBT-IGBT
+MOS-MOS V1+ V2
Hybrid
ZVS-ZCS Asymmetric
* Refer to Section 1.3.2.
Chapter 1-10
1.3.2. Soft-Switching Technology
The concept of soft-switching is dated back to 1920s in the application of vibrator
converters [48]. The latest round of interest in soft-switching technology starts around
1980s [49]-[52] from the resonant converters to reduce the switching loss and EMI [53]-
[54], allowing the increase of switching frequency [55]. There are three types of soft-
switching: zero-voltage-switching (ZVS), zero-voltage-zero-current-switching (ZVZCS)
and zero-current-switching (ZCS).
The principle of ZVS is to provide energy to completely discharge and charge the
output parasitic capacitors of switches during commutation transitions. The energy for
achieving ZVS of the lagging switches in phase-shift FB converters is provided by the
leakage inductance of isolation transformer. Therefore, ZVS is only guaranteed above a
certain pre-designed load level. To extend the soft-switching range, additional energy
sources for achieving ZVS of the lagging switches are fulfilled by either linear inductor
[52], saturable inductor [28], coupled inductor [56]-[57], magnetizing inductor [58]-[59] or
output inductor [60]. To reduce parasitic ringing, auxiliary circuits are added in secondary-
side [50], [61] or primary-side [52], [62]-[65]. These approaches increase the circuit
complexity, induce additional duty cycle loss and cause undesirable secondary-side ringing.
The magnetizing current of the transformer flows at its maximum value through the
primary switches during freewheeling mode, increasing the conduction loss.
In an isolated ZVZCS phase-shift FB converter, the ZVS of the leading switches is
ensured by energy stored in the output inductor. The ZCS of the lagging switches is
fulfilled by resetting the primary winding current during freewheeling mode. Accordingly,
various kinds of passive circuits or active circuits are proposed in [66]-[76] to assist ZCS, at
Chapter 1-11
the expense of either increasing circuit complexity and/or overvoltage across the
secondary-side rectifier.
Very little research has been devoted to FB ZCS converters: in [77] and [78], ZCS
is obtained in current-driven converters, by using a passive snubber [77], or an active
snubber [78]. With these methods, ZCS is achieved by utilizing a resonance process in a
snubber formed by a resonant inductance Lr (with the inclusion of the leakage inductance of
the transformer) and a resonant capacitor Cr (with the inclusion of the reflected winding
capacitance). However, ZCS is lost at high input current. In order to extend the ZCS
range, the characteristic impedance of the resonant tank has to be decreased, either by
decreasing Lr or increasing Cr. The former way leads to an increase in the current stress on
the primary switches, and the latter one results in an increase of the time duration for
discharging Cr, therefore, the loss of duty-cycle. Voltage-driven FB ZCS converters are
proposed in [79]-[83] by using snubbers in the primary side [79], [81]-[82] or in the
secondary side [80], [83]. In all of the available solutions, the energy used for achieving
soft-switching is not optimized. A trade-off among the ZCS range, duty-cycle loss and
circulating current has to be accomplished.
In the presented research work, a snubbering technology having an adaptive snubber
energy control for ZCS of a current-fed dc-dc converter will be discussed in Chapter 2. It
achieves minimum resonant energy provided for ZCS at different load values. Moreover, a
new type of soft-switching scheme, called hybrid zero-voltage-switching and zero-current-
switching (hybrid ZVS-ZCS) will be presented in Chapter 4.
Chapter 1-12
1.3.3. Selection of Topology
1) Topologies for high output voltage application
The research in resonant converters reveals their suitability for high output voltage
applications, especially the series-parallel one [84]-[87]. It shows better output voltage
regulation ability under light loading condition compared to series type resonant converter
and smaller circulating current than that of parallel one. However, a large variation of the
switching frequency is required from full load to no load when operating above the
resonant frequency. There is still a trade-off between the upper switching frequency and
the circulating current [16] at light loads. Moreover, turn-off loss is not eliminated in
series-resonant converters, which is not desirable for converters employing IGBT with turn
off tail current.
Therefore, ZVS current-fed converters [88]-[91] and ZCS current-fed converters
[77] and [92] with capacitive output filter are proposed as an alternative solution for high
output voltage application. ZCS is preferable for converters employed IGBTs. However,
as discussed in Section 1.3.2, the ZCS load range is compromised by the light load
circulating current, thus, conduction loss in [77] and [92]. In Chapter 2, a current-fed ZCS
FB PWM converter is chosen for converting a 530 V to 15 kV with an adaptive resonant
snubber.
2) Topologies for high input voltage and low output voltage application
The high input voltage to low load voltage application discussed here is specifically
referred to the on-board applications in railway systems as presented in Section 1.4. The
Chapter 1-13
target input voltage of the prototypes designed is 1500 V. Fig. 1.7 shows the available
choices for dc-dc converters in terms of the circuit topology, single switch [93]-[94] or
combination of switch pair and soft-switching scheme with respect to various input voltage
and power levels.
In particular, there are two available solutions to convert the 1500 V line to low load
voltages in a single step as presented in the chart of Fig. 1.7. The first one is a FB
converter [82]-[83] and [95], in which high-voltage devices are necessary. Switches with
voltage rating of 1.7 kV or 2.5 kV should be used on the primary side. In [82], a
secondary-side snubber, with one active switch turned on and off twice in one cycle, is
added to assist ZCS of the IGBTs. If the full-wave rectifier is replaced by a current
doubler rectifier, two active snubbers are needed for ZCS of all four IGBTs [96]. In [83],
two primary-side active snubbers are used to ensure ZCS of the four IGBTs, the auxiliary
switches in the snubber are submitted the same voltage stress as the main switches. The
second solution is a TL converter [97]-[98]. Four IGBTs with voltage rating of 1.2 kV can
be used for the above specific application. Although ZCS is preferable for IGBTs as stated
above, these TL converters are implemented with ZVS.
In Chapter 3 and Chapter 4, two novel solutions are proposed with multi-level and
three-level (with asymmetric voltage stresses on the two switch pairs) circuit structures,
respectively. Current multiplier and current doubler [99] rectification circuits are applied
respectively to enhance the output current capacity.
Chapter 1-14
Fig. 1.7 Available options on topology, combination of switch pair and soft-switching
scheme for dc-dc power converters with different input voltages and output power levels.
1.4. System Level
1.4.1. Single-Step Conversion Concept
Typical railway systems are powered by dc transmission lines with voltage levels of
600 V, 750 V, 1500 V or 3000 V [100]. This voltage is then inverted into a 3-phase ac
voltage of 400 V, 60 Hz, and further rectified into a dc voltage of 110 V for charging of
backup batteries. The 110 V voltage is further converted to lower voltages for supplying
the low-voltage equipment (which requires input of 24 V, 32 V, 48 V or 64 V [101]). Fig.
1.8 shows the conventional architecture of the electrical system on metro trains. As
illustrated, the energy supplied to the low voltage equipment goes through multiple power
conversion stages for converting the high voltage of several kilovolts into low voltages,
implying low overall power conversion efficiency. An alternative energy-efficient
approach would be to perform the high-voltage to low-voltage dc-dc conversion in a single-
Chapter 1-15
step and at high switching frequency as shown in Fig. 1.9. Based on the innovation in
system level, it is possible to significantly improve the power conversion efficiency and
power density for converters used for on-board low voltage applications.
Fig. 1.8 Typical block diagram of the electrical network on metro trains.
Fig. 1.9 Proposed block diagram of the electrical network on metro trains.
Chapter 1-16
1.4.2. Fast Transient Control Methods for Load Converters
The low output voltages of the high-voltage converters are usually used to supply
various low-voltage converters which are exposure to momentary loads. Therefore, it is
crucial to improve the dynamic response of those low-voltage converters.
Much effort has been made in developing various control schemes for switched-
mode dc-dc converters to achieve good output regulation and dynamic response. The
controller is designed dominantly with small-signal linearization techniques in frequency
domain [102]. However, switching converters are highly nonlinear dynamic systems and
their large-signal characteristics will behave differently from that predicted by the small-
signal design approaches. Furthermore, some converter circuits like boost- and buck-
boost-derived converters are non-minimum phase systems, having a right-half-plane zero in
the linearized control-to-output transfer function. They are slow in responding because of
larger phase lag between input and output signals, resulting in faulty behavior at the start of
a response. This property makes the controller impossible to be designed with classical
control theories to achieve fast dynamic response over wide bandwidth of supply and load
disturbances.
To overcome the limitations of conventional small-signal-based controllers, an
alternative concept is to design controllers directly in time domain to achieve fast dynamic
responses. One major class of them is switching surface control. The concept is to
determine the time sequences to turn on/off switches according to certain constrains,
namely, switching surfaces [103]-[106]. Typical switching surface control methods are
hysteretic control with zero-order switching surface as shown in Fig. 1.10(a)-(b) or sliding-
mode control (SMC) with first-order switching surface [107]-[116] shown in Fig. 1.10(c).
Chapter 1-17
(a) Voltage hysteresis control (i.e., bang-bang control).
(b) Current hysteresis control.
Chapter 1-18
(c) Sliding mode control.
(d) Boundary control with second/high -order switching surface
Fig. 1.10 Switching surface control methods with different switching surfaces.
Chapter 1-19
The hysteretic controller tightly regulates the inductor current at the current
reference. With further extension on regulating the output voltage, the SMC is the popular
choice in boundary control. However, the optimal sliding surface and the stability for fast
dynamic response depend on the supply and load characteristics. It is thus difficult to
design a set of well-defined control parameters for the sliding surface at all operating
points. The control parameters such as the slope of the switching function are sometimes
designed by trial-and-error, start-up profile, switching frequency, etc. In general, the
converter requires taking several switching actions before settling to the steady-state. The
SMC is sometimes applied to the fast control loop and the output is regulated by a
proportional-integral (PI) controller. The PI controller is designed by classical control
theory or sophisticated design method, like the fuzzy controller.
Instead of a linear switching surface, second-order and high-order switching
surfaces are proposed for buck converter [117]-[120] as shown in Fig. 1.10(d). These
nonlinear switching surfaces are approximately or ideally follow the on/off state trajectories
of buck converter. Therefore, the parameters used in the control law are well-defined and
the converter can revert to steady-state after two switching actions. A single control law is
applicable for buck converter operating in both continuous conduction mode (CCM) and
discontinuous conduction mode (DCM). The control methods are named as boundary
control with second/high -order switching surface. Apart from the aforementioned merits,
there are several practical issues to apply boundary control with second/high -order
switching surface, as well as other switching surface control methods, for dc-dc converters.
For example, the switching frequency is varying, the controller performance is sensitive to
parameters of the output filter and the inductor is suffered from high peak current. To
Chapter 1-20
handle these issues, several techniques have been proposed for buck-converter [121]-[123]
to achieve fixed frequency, parameter independent solution or programmed inductor
current. However, one remaining fundamental issue which poses great challenges is that
the same concept cannot be easily applied to converters with non-minimum-phase
characteristics [20]. It is difficult to formulate a simple switching surface on the state-plane
for a converter with state trajectories in spiral shape, such as the boost converter discussed
in [124].
Part of the objective of this research work is to tackle the above mentioned
fundamental issue in switching surface control, therefore, to apply the concept of boundary
control with second-order switching surface to all of basic dc-dc converters and make it
possible to apply the associated developed control techniques for buck converter to other
kind of converters. Accordingly, a uniform second-order switching surface σ2 on a
Cartesian x-y plane rather than the state plane is proposed and discussed in Chapter 5.
1.4.3. E-Cap Reduction Technology
The considerable power loss of aluminum electrolytic capacitors (E-Caps) observed
in the research of high-voltage converters inspires the investigations into capacitors used in
capacitor-supported power electronic systems. Meanwhile, from system level perspective,
the high input voltage of the converters discussed in Chapter 3 and Chapter 4 is obtained
from ac-dc front-end stage. Therefore, low frequency ripples appear in the input capacitors
and therefore large electrolytic capacitors are normally required to limit the input voltage
variations. As discussed in Section 1.2.2, the widely used E-Caps suffer from short
lifetime, which will in turn affect the overall reliability of the system. The replacement of
Chapter 1-21
E-Caps by power film capacitors can reduce the power loss and extend the lifetime,
however, at expense of considerable increase of cost and volume.
Therefore, a practical and feasible approach to deal with the above described issues
is to reduce the required capacitance. There are many prior-art methods, which are
classified as follows:
1) Performance tradeoff - This simple method allows the dc-link voltage to have large
variation with smaller capacitance. However, such approach is practically less
impressive as the system performance is degraded. It is only suitable for certain
applications, like the ones discussed in [125] and [126]. In [127], a set of procedure
for designing an optimal value of the capacitor bank is discussed.
2) Reduction of the dc-link capacitor current with sophisticated control. Different
control methods are proposed in [128]-[133]. As shown in Fig. 1.11(a), their
methodology is based on rendering the current iDC1 to iDC2 so as to minimize the
ripple current iC flowing through the capacitor. The first converter is an active
rectifier in [128]-[131], and a step-up dc-dc converter in [132]-[133], while the
second converter is an inverter. The advantage of this approach lies in that no
auxiliary active switch is needed. However, those control methods cannot be
applied to systems with front-end diode-bridge rectifier. Moreover, apart from
requiring a sophisticated controller, some of them also rely on specific relationship
in the operating frequency between the first and second converters [128], [131], and
[132]. The method described in [129] is limited to three-phase systems. The
controller described in [128] is based on assuming ideal, lossless energy conversion.
Thus, the input current could be distorted unless multiple cell load inverters are
Chapter 1-22
applied. The performance of these controllers is highly dependent on the accuracy
of the calculations [130], [133] and affected by the overall time delays within the
control loops.
3) Increase in the frequency of dc-link voltage ripple. A double frequency front-end
converter that utilizes the multi-phase concept is proposed in [134], resulting in
reduced voltage ripple. However, the approach cannot significantly reduce the dc-
link capacitance.
4) Ripple cancellation circuit with coupled magnetic device. In [135], a coupled
inductor is applied to cancel the voltage ripple of the dc input, dc output or dc-link
of a power converter. The concept is based on the assumptions that the capacitance
is infinite and the turns ratio of the coupled inductor is ideally 1:1. With finite
capacitance, the coupled inductor filter and the capacitor becomes a low pass filter.
To avoid large size of the coupled windings, the technique is unsuitable for filtering
low-frequency voltage ripples, such as those in dc-link capacitors. Moreover, the
dynamic response of the capacitor may be degraded due to the series-connected
coupled winding.
Besides the aforementioned methods, active power filters can also be used for
reduction of the dc-link capacitance. They have been traditionally proposed on the ac side
for current harmonic reduction in distribution systems or power electronic converters [136]-
[147]. There are shunt active filters [140]-[144], series active filters [145]-[147] and hybrid
ones [145]. In [148]-[155], active power filters are applied in high-voltage direct-current
(HVDC) transmission line and other dc distribution systems for harmonic reduction and dc
voltage stabilization. They require an external power source connecting to the input of the
Chapter 1-23
active filters to assist the active power control between the source and load. For the
application of reducing dc-link capacitance in power electronic conversion systems, the
concept of active filters is adopted in [156]-[170]. It is based on connecting an auxiliary
circuit in parallel with the dc-link capacitor as shown in Fig. 1.11(b). The added circuit
serves as an active impedance or energy source. Different methods of implementing the
auxiliary circuit are given. In [157], the auxiliary circuit has a single switch with
dissipative resistor. In [161], a relay is placed at the input line and is activated, depending
on the dc-link voltage level, resulting in a stable dc-link voltage, but at the expense of
reducing the input power factor of the entire system. In [156], [160] and [163], an H-bridge
circuit with a current source (inductor) is used to minimize the ripple current of the dc-link
capacitor. However, the high inductor current stress and high switching frequency
requirement in [163] are the major practical challenges of the method. A current injection
method was applied in [159]-[160], [162] and [164] by a half-bridge structure. In [165]-
[166], a two-switch converter that can operate bi-directionally in both buck and boost
modes is used for the H-bridge front-end and dc current electrical load application. In
[167], series-connected dual boost converter is as the shunt active filter for a three-phase
diode rectifier front-end conversion system. In [168], the ripple reduction circuit allows an
additional power port for enhancing the dynamic response of the whole system. The
common challenge of all these methods is that the components used in the auxiliary circuit
are under a high voltage stress, which could be as high as the dc-link voltage.
Chapter 1-24
Fig. 1.11 Prior-art concepts for reducing dc-link capacitors.
1.5. Organization of the Thesis
This thesis contains seven chapters. In Chapter 2, the concept of adaptive snubber
energy for ZCS will be presented. The operating principles of the proposed current-fed FB
converter will be described. The trade-off design and small-signal model will be given.
Implementations and evaluations of a 530 V / 15 kV 5 kW experimental prototype will be
discussed.
In Chapter 3, a solution for high-to-low voltage conversion based on a generalized
multi-level multi-phase topology will be discussed. The switching mechanism and
operation of a typical switch pair will be analyzed. A dc analysis will be carried out to
determine the dc conversion ratio and the ZVS conditions in an analytical form. The self-
balance property of the voltages across the input capacitors will be described. A 1500 V /
48 V, 2 kW prototype with four switch pairs in the primary-side is designed, implemented,
and evaluated.
In Chapter 4, another solution to convert 1500 V dc to 48 V dc will be presented
Chapter 1-25
based on a novel concept, by which the voltage stresses on the series-connected two switch
pairs are asymmetric. The advantages of a TL converter adopted the proposed concept will
be illustrated in terms of utilization of switching devices and load range for soft-switching.
A new concept of hybrid ZVS-ZCS scheme will be proposed. The evaluations on a 2 kW
prototype will be given to verify the theoretical predictions.
In Chapter 5, a uniform second-order switching surface for a fast transient
controller of dc-dc converters will be derived. Stability analysis and controller
implementation will be discussed. Simulation results on four kinds of dc-dc converters
(i.e., boost converter, buck-boost converter, Ćuk converter and SEPIC) will be presented to
verify the universal applicability of the proposed control method. Experimental results on
a 48 V/48 V buck-boost converter prototype will be also analyzed to exhibit the
performance of the controller.
In Chapter 6, a patent-pending technology for reducing dc-link capacitance in
capacitor-supported power electronic systems will be presented. The operation principle
and implementation of the proposed voltage compensator will be discussed. Simulation
and experimental results will be provided to verify the theoretical analysis.
In Chapter 7, conclusions and suggestions for future research on this topic will be
given.
Chapter 2-26
CHAPTER 2
HIGH OUTPUT VOLTAGE ZCS CURRENT-FED FULL-BRIDGE CONVERTER
WITH SELF-ADAPTABLE SOFT-SWITCHING SNUBBER ENERGY
2.1. Introduction
This chapter proposes a snubbering technology having an adaptive snubber energy
control for ZCS of current-fed dc-dc converters. The snubber is implemented with a
switched-capacitor circuit in which the charging and discharging processes of the capacitor
are controlled, depending on the loading condition. Therefore, the resonant energy
provided for ZCS is self-adaptable and is minimized at different load values. The
conduction losses of switching devices are kept minimal while achieving soft-switching.
Based on the concept, a novel soft-switched, current-driven FB converter is
presented. An adaptive ZCS snubber is connected in series with the primary windings of
the isolation transformer. All primary switches are operated with ZCS and the snubber
switches are operated with ZVS. For a given input current, the snubber capacitor is
charged up to the minimum required energy for ZCS of the switches. Thus, less resonant
energy is needed and the currents following through the primary switches never exceed the
input current. High efficiencies are expected to be obtained at wide load range.
A 5 kW prototype converting 530 V dc to 15 kV dc has been built and the controller
is implemented with a digital signal processor (DSP). The testing results confirm the
theoretical predictions.
Chapter 2-27
2.2. Current-Fed ZCS FB Converter and Its Operation Principle
2.2.1. Circuit Structure
Fig. 2.1 Proposed current-fed full-bridge converter with adaptive ZCS snubber.
The proposed current-fed FB converter is shown in Fig. 2.1. L is the input inductor
to provide an input current source. Four IGBTs S1-S4 are used in the primary-side FB
circuit and driven by phase-shift PWM signals. Np and Ns are the number of turns of the
primary windings and secondary windings of the transformer Tr, respectively. Llk is the
leakage inductance of Tr. A ZCS snubber realized by a switched-capacitor circuit is
connected in series with the primary windings of the isolation transformer. The snubber is
composed of two unidirectional transistors Sa1, Sa2, and one capacitor Cr. A diode bridge
formed by D1-D4 is used for the ac-dc rectification. A capacitive filter is applied in the
output side, which is preferable in high output voltage application. As defined in Fig. 2.1,
Vo is the output voltage, ip is the primary current of Tr, io is the rectified secondary current
before the output capacitor and vCr is the voltage across the snubber capacitor Cr.
Chapter 2-28
2.2.2. Steady-State Operation Modes
Fig. 2.2 Timing diagram for analysis of the current-fed FB converter.
Chapter 2-29
Fig. 2.2 shows the timing diagram of the proposed converter in one switching cycle.
The upper two switches (S1 and S2) and the lower two switches (S3 and S4) are driven
complementarily, respectively. The driving signals for S1 and S4 have a phase difference of
180°. The steady-state operations are cyclically divided into 12 modes and are symmetric
in the first and the second half cycles. Therefore, the following analysis is given for the
first half cycle. For the sake of simplicity, the effect of the magnetizing inductance (3.9
mH in the experimental prototype) of the transformer is neglected. It has been verified by
simulation that the soft-switching function and converter operations are not affected by the
magnetizing inductance. Fig. 2.3 shows the corresponding equivalent circuits.
(a) Mode 0 [before t0]
(b) Mode 1 [t0, t1]
Chapter 2-30
(c) Mode 2 [t1, t2]
(d) Mode 3
(e) Mode 4
Chapter 2-31
(f) Mode 5
(g) Mode 6
Fig. 2.3 Operation modes of the current-fed FB converter (first half cycle).
Mode 1 [t0, t1] [Fig. 2.3(b)]: Before t0, the circuit topology is shown in Fig. 2.3(a).
The input energy is transferred to the load via diodes D2 and D3. At t0, a new cycle begins
with Sa1 turning off with ZVS. The energy transfer continues. Cr is being charged
( ) inpi t I (2.1a)
0( ) inCr
r
Iv t t t
C (2.1b)
The duration of this stage is
Chapter 2-32
01 r Cr int C V I (2.1c) where CrV is defined as
1 1 0( ) inCr Cr
r
IV v t t t
C (2.1d)
As will be explained in Section 2.3.1, the duration of this interval is determined to
give the minimum capacitor voltage 1( )Crv t necessary to achieve ZCS of the switches for
each value of the line and load currents. ZCS can be achieved at high input current
without increasing unnecessarily the capacitor’s accumulated energy at a lower input
current. That is, the snubber energy is self-adjustable depending on the value of the input
(and implicitly the load) current.
Mode 2 [t1, t2] [Fig. 2.3(c)]: At t1, S3 turns on with ZCS, the primary current starts
reducing. Thus, the current ip flowing through the primary side of Tr is
1 1( ) cos sinCr op
pin
V nVi t t t t t
ZI
＝ (2.2a)
where p lk rZ L C , 1 lk rL C and n is the primary-to-secondary turns ratio of the
transformer.
The snubber capacitor voltage vCr is given by
1 1( ) sin cosCr Cr oin p ov t t t V nV t tI Z nV (2.2b)
The topology ends when the primary current drops to zero, giving the duration of
this stage
112
1tan in p
Cr o
I Z
V nVt
(2.2c)
Chapter 2-33
22
2( )Cr Cr o in p ov t V nV I Z nV (2.2d)
According to (2.2a), with a higher Iin, one needs a larger CrV to bring the primary
current to zero. When Iin is low, the required value of CrV is also low. Consequently, the
durations of the first and second switching intervals are only slightly dependent on the
value of Iin, no loss of duty-cycle arises from getting such a large ZCS range.
Mode 3 [t2, t3] [Fig. 2.3(d)]: At t2, ip reaches zero, S4 is switched off with ZCS. As
a result, the secondary current reaches zero, and the rectifier diodes turn-off naturally
(ZCS). The load voltage is assured by the output capacitor (freewheeling stage)
( ) 0pi t (2.3a)
2( ) ( )Cr Crv t v t= (2.3b)
3 2( ) ( )Cr Crv t v t= (2.3c)
Mode 4 [t3, t4] [Fig. 2.3(e)]: The PWM dictates the instant t3 when S2 is turned on
with ZCS. The energy stored in Cr is transferred to the load. ip goes negative and
increases in absolute value, the presence of Llk in the ip path assures that the rectifier diodes
D1 and D4 are turned on with ZCS. The current through S1, 1( ) ( )S in pi t I i t , decreases
33
( )( ) sinCr o
pp
v t nVi t t t
Z
(2.4a)
3( ) cosCr o Cr ov t V nV t tnV (2.4b)
The stage ends when the primary current in absolute value reaches the input current,
giving the duration of this topology
Chapter 2-34
134 22
1sin
2
in p
Cr o in p o
I Zt
V nV I Z nV(2.4c)
4 34( ) cosCr o Cr ov t V nV tnV (2.4d)
Mode 5 [t4, t5] [Fig. 2.3(f)]: At t4, ip reaches -Iin, the current through S1 drops to zero,
so S1 can be turned-off with ZCS. The energy is transferred from the line to the load. Cr is
discharged to the load, thus recuperating its energy.
( )p ini t I (2.5a)
4( ) inCr o
r
Iv t nV t t
C(2.5b)
This mode ends when is completely discharged.
45r o
in
C nV
It (2.5c)
Mode 6 [t5, t6] [Fig. 2.3(g)]: At t5, Sa2 turns on with ZVS, and the circuit operates in
this transfer-energy mode until a new half-cycle is commenced by turning off Sa2.
( )p ini t I (2.6a)
( ) 0Crv t (2.6a)
It can be noted that, in neither stage, the primary current overpasses the input
current, keeping thus the conduction losses in the primary switches at their minimum value.
S1 is turned on with ZCS at t9 and is turned off with both ZCS and ZVS at t4. S3 is turned
on and off with ZCS at t1 and t8, respectively. The operations of S2 and S4 are the same as
those of S1 and S3, respectively. Thus, all of the four switches S1- S4 are switched with ZCS.
rC
Chapter 2-35
2.3. Steady-State Analysis
2.3.1. ZCS Conditions
In order to ensure soft-switching of the primary switches, two conditions have to be
satisfied: 1) ip has to drop to 0 in Mode 2, and 2) ip given by (2.4a) has to reach -Iin in Mode
4. By taking (2.2d) and (2.3c) into account, Eq. (2.4a) gives
2 22Cr in p o in p oV I Z nV I Z nV (2.7)
It can be noted that ip in (2.4a) has to reach -Iin. It is equivalent to satisfying the
following condition
2 23
1 1( )
2 2r Cr o lk inC v t nV L I (2.8)
That is, it requires sufficient energy in Cr for reducing the primary current from 0 to -Iin.
It can be seen from (2.7) that for a given converter (with certain values of Zp, n, Vo),
CrV depends solely on the value of Iin, i.e. the resonant energy used to achieve ZCS is self-
adaptable. As explained in Section 2.5, Iin is sensed, and the minimum necessary capacitor
voltage for ensuring ZCS at the measured value of the input current, CrV , is calculated by
(2.7). In the first stage, Cr is charged. When the sensed value of vCr reaches the calculated
value CrV , the switch S3 (respectively S4 in the second half-cycle) is turned on, marking the
end of this switching stage (i.e., determining the instant t1 in the timing diagram).
2.3.2. DC Conversion Ratio
A phase-shift control is used. The energy transfer is controlled by the delay
between S1 and S3 in the first half-cycle, and S2 and S4 in the second half-cycle. By
Chapter 2-36
assimilating the shift angle with a duty-cycle D, and operating as the boost converter where
the on-topology is characterized by the charging of the input inductor, one can define
12 23 34sDT t t t (2.9) In order to get the formula of the dc conversion ratio, an input-to-output energy
balance written for a half-cycle is obtained
6
1
1
2s in in o k
k
T V I nV IS
(2.10)
where 1
( )k
k
tk p
tIS i t dt
.
By taking into account that 23 12 34sDTt t t ＝ , 56 01 45/ 2s sT DTt t t and using
(2.1a – 2.5a), (2.1c – 2.5c), (2.7) and (2.9), one gets
1 CrrIS VC
2 in p o CrrIS I Z nV VC
3 0IS
4 r in pIS C I Z
5 r oIS C nV
6
1 2
2
s
Crin r r o
D TIS VI C C nV
By inserting the above formulas of ISk (k = 1,…,6) in (2.10), the dc conversion ratio,
M, results
Chapter 2-37
2 2
1
2 2 21 2
o
inr o in p in p o in p
sin
VM
VC nV I Z I Z nV I Z
n DI T
(2.11)
Comparing it with the conversion ratio formula for a boost hard-switching FB:
1/ [ (1 2 )]M n D it results that the intervals for forming ZCS lead to a loss of regulation
range (i.e. DTs cannot be reduced to zero, if so required for regulation purpose, but its lower
limit is t12+t34). This loss of regulation is expressed by Dloss as follows
2 22 2 2
losss
r o in p in p o in p
in
D
C nV I Z I Z nV I Z
I T
(2.12)
Fig. 2.4 Duty- cycle loss versus normalized input current under different snubber capacitor
values (Vo = 15 kV, n = 1/20, Llk = 3.6 µH and fs = 20 kHz).
Chapter 2-38
Dloss is represented versus the normalized input current in Fig. 2.4 (the input current
is normalized with respect to its nominal value Iin,rated ). It can be noted that Dloss increases
with the value of Cr, but it always has a very small value. And even when increasing the
input current, there is only a little change in the duty-cycle loss.
2.3.3. Maximum Voltage across the Snubber Capacitor Cr
In the proposed converter, the maximum voltage of the snubber capacitor is crucial
in determining the voltage stress across both the primary transistors and auxiliary switches.
Fig. 2.5 presents the maximum voltage (vCr,max = vCr(t2)) of the snubber capacitor for various
Cr and Llk calculated using (2.2d) and (2.7) for the maximum input current. Larger snubber
capacitance and lower leakage inductance are beneficial to reducing vCr,max.
Fig. 2.5 Maximum vCr versus Cr under different Llk values
(Vo = 15 kV, Vin = 0.8 Vin,rated, Io = 1.2 Io,rated, n = 1/20, and fs = 20 kHz).
Chapter 2-39
2.3.4. Duration of the Snubber Capacitor Charging / Discharging Intervals
In order to increase the soft-switching range, one is interested in keeping the soft
switching intervals short. The modes 1, 2, 4, and 5 create the ZCS and ZVS conditions for
the main and auxiliary switches, respectively. Their total duration (= t02 + t35) calculated
for the maximum input current according to (2.1c, 2.2c, 2.4c, 2.5c) versus Cr for different
values of Llk is plotted in Fig. 2.6. It can be noted that smaller values of Llk and Cr are
beneficial for reducing the duration of those intervals.
Fig. 2.6 Duration of charging and discharging intervals of the snubber capacitor versus Cr
under different Llk values (Vo = 15 kV, Vin = 0.8 Vin,rated ,and n = 1/20).
2.3.5. Regulation and Soft-Switching Boundaries
According to (2.9),
Chapter 2-40
01 45 56
1 2
2sD T
t t t
(2.13)
For ensuring the existence of the soft-switching assisting intervals (Modes 1, 2, 4, 5), the
boundary on the duty-cycle are given by the inequality
12 34 01 451
2s s
t t t tD
T T
(2.14)
By substituting (2.1c), (2.2c), (2.4c), (2.5c) and (2.7), the above inequality becomes
2 2
1
2 2
21( tan )
2 2
12
r in p o in pin p
s sinin p o in p
C I Z nV I ZI ZD
T I TI Z nV I Z
(2.15)
Fig. 2.7(a) gives the operating limits of the duty cycle versus the normalized output
current. The intersection between Dmin and Dmax represents the minimum load current for
which soft-switching is achieved. For the considered design specifications (i.e., Vo = 15 kV,
n = 1/20, Llk = 3.6 µH, Cr = 0.022 µF and fs = 20 kHz), the transistors can be soft-switched
for a load range starting from 20%. Clearly, ZCS can still be maintained at a heavy current.
In Fig. 2.7(b), the voltage on the resonant capacitor at instant t2, vCr(t2), is also given versus
the normalized load current within the designed input voltage range. It can be noticed
that, except at the maximum load current, this voltage is always smaller than vCr,max,
confirming the self-adaptable characteristics of the proposed soft-switching solution, i.e. at
each actual value of the load current, the snubber will use the minimum necessary
resonant energy to get ZCS for the primary switches.
Chapter 2-41
(a)
(b)
Fig. 2.7(a) Lower and upper boundaries of the duty-cycle for soft-switching versus
normalized load current; (b) Adaptive snubber capacitor voltage vCr(t2) versus normalized
load current (Vo = 15 kV, n = 1/20, Llk = 3.6 µH, Cr = 0.022 µF and fs = 20 kHz).
Chapter 2-42
2.4. Small-Signal Analysis and Controller Design
2.4.1. Small-Signal Model and Open Loop Transfer Functions
The effective duty cycle eff lossD D D can be written as
1 11
2 2in p
effs in p o
I ZD D
T I Z nV
(2.16)
by applying a Taylor expansion of (2.12) and retaining the first three terms.
By superposing ac small-signal perturbations inv , ini , ˆov , oi and d on the values of the
input voltage Vin, input current Iin, output voltage Vo, output current Io, and duty-cycle D,
respectively, after a few manipulations in (2.16), one can find the ac small-signal
perturbation in the effective duty-cycle as follows
2 2ˆ ˆ ˆ ˆ ˆˆ ˆ
2 2
lk o lk ineff in o i v
s o in p s o in p
nL V nL Id d i v d d d
T nV I Z T nV I Z
(2.17)
where ˆ ˆi i ind Q i and ˆ ˆv v od Q v ,
22
lk oi
s o in p
nL VQ
T nV I Z
,
22
lk inv
s o in p
nL IQ
T nV I Z
.
Consequently, an averaged linear circuit model is derived as shown in Fig. 2.8. To
simplify the analysis, the parasitic resistances of the input inductor, rL, and of the output
capacitor, rC, are neglected in the small-signal models in Fig. 2.9 used for derivation of the
associated power stage transfer functions.
Fig. 2.8 Small-signal model of the proposed converter.
Chapter 2-43
(a) Small-signal ac model with ˆ ˆ0 and 0od i
(b) Small-signal ac model with ˆˆ 0 and 0in ov i
(c) Small-signal ac model with ˆ ˆ0 and 0ind v
Fig. 2.9 Small-signal models for derivation of the power stage transfer functions.
According to Fig. 2.9, the ac small-signal transfer functions of the power stage are
derived as follows
2 2 2ˆ ˆ( ) ( ) 0
( )( )
ˆ ( ) o
o
vgin L L
d s i s
v sG s
v s LCs L R L C s R
(2.18)
2 2 2ˆ ˆ( ) ( ) 0
ˆ ( ) 1( )
ˆ ( ) o
in Lig
in L Ld s i s
i s Cs RG s
v s LCs L R L C s R
(2.19)
Chapter 2-44
2 2 2ˆ ˆ ( ) 0
2( )( )
ˆ( )
in o in o o Lid
L Lv oin i s
n CV s I V V Ri sG s
LCs L R L C s Rd s
(2.20)
2 2 2ˆˆ ( ) 0
2( )( )
ˆ( )
o in o invd
L Loinv i s
n I V LI sv sG s
LCs L R L C s Rd s
(2.21)
2 2 2ˆˆ ( ) ( ) 0
ˆ ( )( )
( ) in
ini
o L Lv s d s
i sA s
LCs L R L C s Ri s
＝ (2.22)
2 2 2ˆˆ ( ) ( ) 0
ˆ ( )( )
( ) in
oo
o L Lv s d s
v s LsZ s
LCs L R L C s Ri s
＝- (2.23)
where 2 , 2 , (1 2 ) 2 2o i in v eff in i o vnV Q nI Q n D and nI Q nV Q .
The ac open-loop transfer functions: input voltage-to-output voltage, Gvg, duty-
cycle-to- output-voltage, Gvd, and output-current-to-output-voltage (output impedance), Zo
are used in the voltage control closed-loop. The ac open-loop transfer functions: input-
voltage-to-input-current (input admittance), Gig, duty cycle-to-input current, Gid, and output
current-to-input current, Ai, are used in the current control closed loop.
2.4.2. Controller Design
A current-mode control method is used to control the proposed converter. The
equivalent small-signal ac model of the closed-loop regulator is given in Fig. 2.10, where
the following notations are used:
ˆ ( )ev s - small-signal error voltage.
vK - output voltage scaling factor.
iK - inductor current scaling factor.
Chapter 2-45
( )vcG s -transfer function of voltage loop compensator.
( )ccG s -transfer function of current loop compensator.
Fig. 2.10 Closed-loop small-signal ac equivalent model of the regulator.
Fig. 2.11 Bode diagram of Gid(s) (Vo = 15 kV, n = 1/20, Llk = 3.6 µH, Cr = 0.022 µF, RL
= 45 kΩ and fs = 20 kHz).
Chapter 2-46
Fig. 2.12 Bode diagram of voltage-loop gain ( )vT s (Vo = 15 kV, n = 1/20, Llk = 3.6 μH, Cr =
0.022 μF, RL = 45 k and fs = 20 kHz).
According to Fig. 2.10, the current loop gain, Ti (s), results in
( ) ( ) ( )i i PWM cc idT s K K G s G s (2.24) A PI controller is used for the current loop compensator. Thus, Gcc (s) can be expressed as
( ) iicc ip
KG s K
s (2.25)
Gid(s) rather than Ti(s) itself is measured in the experimental prototype to determine the
parameters Kip and Kii. Fig. 2.11 presents the Bode diagram of Gid(s) which provides the
information for the PI controller design. The values chosen for Kip and Kii are 6.29 and
1.25×104, respectively.
The voltage loop gain, Tv, results in
Chapter 2-47
( ) ( ) ( )( )1 ( )
PWM v vc vd ccv
i
K K G s G s G sT s
T s (2.26)
A PI controller is used for the voltage loop compensator. Thus, Gvc(s) can be expressed as
( ) vivc vp
KG s K
s (2.27)
with Kvp = 39.45, Kvi = 3.72×104. Fig. 2.12 shows the Bode diagram of the voltage-loop
with and without compensator Gvc. The designed controller increases the gain at low
frequencies to about 50 dB. The designed cross frequency of the voltage-loop is 842.4 Hz.
The phase margin is 65o and the gain margin is 14.5 dB.
Gvc(s) and Gcc(s) are transferred into the difference equation forms of
1 16.915( ) 1.25n n n n nv v e e e (2.28)
1 141.31( ) 3.72n n n n nv v e e e (2.29)
2.5. Design Procedure and Experimental Verification
The proposed converter is designed and implemented with Vin = 530 V±20%, Po,rated
= 5 kW, Vo = 15 kV. A switching frequency of 20 kHz is used, giving Ts /2 = 25 μs.
1) The minimum boundary on Llk is chosen for achieving a soft increase in the
primary current (i.e. of the current through S2) at t3 when S2 is turned-on. By using Fig. 2.5
and Fig. 2.6, one can choose the values of Cr and Llk, for keeping the total duration of the
resonant-purposed soft-switching intervals at 4 s (i.e. less than 20% of a half switching
period) and for limiting vCr,max at 931 V (which is the maximum capacitor voltage value
attained when the input voltage drops at its lowest value of the given range): Llk = 3.6 μH,
Cr = 0.022 μF.
Chapter 2-48
2) The ratings of the switches are chosen by considering the voltage and current
stresses. The voltage stress of the main switches is Iin,maxZp + 2nVo and that of the auxiliary
switches is Iin,maxZp + nVo. The current stress of all switches is Iin,max.
3) The value of the input inductor is chosen to limit the input current ripple Li at
2.5 % from its nominal value
1 2 s o LL nD D T V i (2.30)
4) The value of the output capacitor Co is chosen to limit the voltage ripple o
V at 0.6%
of Vo.
max2 /
o o S oC D I T V (2.31)
5) The output diodes are chosen by considering the voltage and current stresses.
The voltage stress and current stress of the diode are Vo and Po,max / Vo, respectively.
The four main switches are driven by phase-shift PWM signals with adaptable
durations of charging and discharging intervals of the snubber capacitor. The driven
signals of the two auxiliary switches are generated by detecting the zero-cross point of the
voltage of the snubber capacitor.
The component values are listed in Table 2.1. The switches used in the prototype
are IGBT modules (having anti-parallel diodes) connected in series with diodes. The
function is to perform unidirectional current flow operation. Fig. 2.13 shows the photo of
the 5 kW experimental prototype.
Chapter 2-49
Table 2.1 Component values used in the analysis and experimental prototype.
Component Value
S1 ~ S4FF150R17ME3G ) (1700 V/150 A)
(with RHRP30120
Sa1 ~ Sa2F4-50R12KS4 (1200 V/50 A)
(with RHRP30120)
IGBT driver 2SD106AI-17
D1 ~ D4 (diode bridge module) 30 kV / 3 A
Cr 0.022 F
Llk 3.6 H
Co 0.2 F / 30 kV
Transformer core Ferrite EE160
Transformer turn ratios 15: 300
Output voltage resistive divider
1:5000
Fig. 2.13 Photo of the 5 kW experimental prototype.
Chapter 2-50
Fig. 2.14 Simplified software flowchart of the proposed control strategy (ε is a small
numerical value).
The control system is implemented by a Digital Signal Processor (DSP)
TMS320F28335 with a soft-start scheme. The inductor current iL (i.e. the input current Iin)
and output voltage Vo are sampled to provide the necessary information for the current-
mode control and to calculate the minimum snubber voltage CrV for realizing ZCS using
(2.7). The instantaneous value of the snubber capacitor voltage vCr is sensed and compared
with the calculated value CrV . When the measured voltage of the resonant capacitor
reaches the calculated value, S3 (S4) is turned on, thus practically determining the instant t1
(t7) as a function of the input current/load. Consequently, the energy accumulated in the
snubber is the minimum one necessary to get ZCS for the actual input/load current. The
maximum vCr(t1) for getting ZCS is reached at the upper limit of the range of the input
Chapter 2-51
current. Fig. 2.14 presents the simplified software flowchart of the proposed control
strategy.
The experimental steady-state voltage and current waveforms of the primary
switches S1 and S3, and auxiliary switch Sa1 under full load, and at 25% loading condition,
are given in Fig. 2.15 and Fig. 2.16, respectively. One can see from the X-Y plots that the
primary switches turn-on/off with ZCS, and the auxiliary switch turns-on/off with ZVS.
At a reduced load, soft switching is still maintained. It should be noted that due to the
parasitic capacitance in parallel with the isolation transformer, the voltage acorss the
primary-side windings can not instantly increase and decrease. Therefore, the captured
waveforms of VS1 in Fig. 2.15(a) and Fig. 2.16(a) are not exactly the same as the
theorectical one during t8-t9 shown in Fig. 2.2.
(a) Waveforms of vS1 and iS1 (vS1: 500 V/div, iS1: 5 A/div and timebase: 5 µs/div).
Chapter 2-52
(b) X-Y plot of vS1 and iS1 (vS1: 500 V/div, iS1: 5 A/div and timebase: 5 µs/div).
(c) Waveforms of vS3 and iS3 (vS3: 500 V/div, iS3: 5 A/div and timebase: 5 µs/div).
Chapter 2-53
(d) X-Y plot of vS3 and iS3 (vS3: 500 V/div, iS3: 5 A/div and timebase: 5 µs/div).
(e) Waveforms of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 5 A/div and timebase: 5 µs/div).
Chapter 2-54
(f) X-Y plot of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 5 A/div and timebase: 5 µs/div).
Fig. 2.15 Switching waveforms of S1, S3, and Sa1 at full load.
(a) Waveforms of vS1 and iS1 (vS1: 500 V/div, iS1: 2.5 A/div and timebase: 5 µs/div).
Chapter 2-55
(b) X-Y plot of vS1 and iS1 (vS1: 500 V/div, iS1: 2.5 A/div and timebase: 5 µs/div).
(c) Waveforms of vS3 and iS3 (vS3: 500 V/div, iS3: 2.5 A/div and timebase: 5 µs/div).
Chapter 2-56
(d) X-Y plot of vS3 and iS3 (vS3: 500 V/div, iS3: 2.5 A/div and timebase: 5 µs/div).
(e) Waveforms of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 2.5 A/div and timebase: 5 µs/div).
Chapter 2-57
(f) X-Y plot of vSa1 and iSa1 (vSa1: 500 V/div, iSa1: 2.5 A/div and timebase: 5 µs/div).
Fig. 2.16 Switching waveforms of S1, S3, and Sa1 at 25% load.
The experimental Bode diagrams of Gid(s) and Tv(s) are given in Fig. 2.11 and Fig.
2.12, respectively, in order to compare the experimental values with the calculated ones.
The experimental results are in full agreement with the theoretical expectations. The Bode
plot of the voltage loop gain proves a good stability, and good phase and gain margins, of
62º and 17 dB, respectively.
Fig. 2.17 presents the snubber capacitor voltage vCr(t2) (in percentage of vCr,max)
under different line / loading condition (a reduced input voltage attracts an increased input
current with a constant output power). One can see that vCr(t2) is lower for all the
conditions, compared with its upper value reached at maximum input/load current. This
proves the adaptive characteristic of the soft-switching solution proposed.
Chapter 2-58
Fig. 2.17 Measured vCr(t2) (in percentage of vCr,max) under different line / loading condition.
The experimental efficiency versus the load is given in Table 2.2. The efficiencies
are 93% at full load and 90.2% at 25% load. A comparative study into the efficiencies of
the converter at the nominal power with hard-switching and with an un-optimized ZCS
scheme (i.e., the designed values of Cr and Lr are not optimized and the energy provided to
achieve the ZCS is not minimum) has been performed. With the optimized RCD snubber in
the hard-switched converter, the conversion efficiency is 83%. With the un-optimized ZCS
scheme, the conversion efficiency is 89%, which is higher than the hard-switched
converter. Nevertheless, the efficiency is less than the one with the proposed self-adaptable
soft-switching snubber energy scheme. This confirms the advantages of the proposed
method.
Chapter 2-59
Table 2.2 Experimental efficiency versus load (Vin = 530 V, Io,rated = 1/3A).
Load (percentage) Efficiency
25% 90.2%
50% 91.3%
100% 93%
2.6. Chapter Summary
In this chapter, a new soft-switched FB converter utilizing an adaptive snubber has
been proposed. It is particularly useful for high-voltage applications. The primary
switches are operated with ZCS, allowing the use of IGBT. The auxiliary switches are
operated with ZVS. The rectifier diodes are operated with ZCS naturally. The maximum
current stress on all the switches is the input current. Soft switching is achieved over a very
wide line and load range. The main characteristic of the solution is its self-adaptability: the
snubber energy necessary to get ZCS for the main switches is adaptable and is dependent
on the value of the primary current. Only at the maximum input current (reached at the
maximum load current and lower limit of input voltage range), the snubber capacitor will
be charged to the maximum level. For the other value of the input current, less snubber
energy is used. It can avoid unnecessary energy circulation, and thus reduce conduction
loss. In each cycle, all the energy accumulated in the snubber capacitor for soft switching
is recuperated to the load. A current-controlled feedback has been implemented with a
DSP. Experimental results measured on a 5 kW, 530 V/15 kV prototype confirm the
advantages of the proposed converter.
Chapter 3-60
CHAPTER 3
HIGH INPUT VOLTAGE MULTI-LEVEL MULTI-PHASE DC-DC CONVERTER
3.1. Introduction
This chapter presents a generalized multi-level multi-phase circuit structure for high
input voltage to low load voltage applications. The proposed structure is formed by n
switch pairs on the primary side, an n-phase isolation transformer with the primary
windings connected to dc-blocking capacitors, and an n-phase current multiplier on the
output side. The switching patterns applied to the switch pairs have a phase difference of
360 n , and the output inductor currents are interleaved correspondingly, making
necessary a smaller output filter. With input voltage Vin and load current Io, the converter
features Vin /n voltage stress on the primary-side switches, and Io /n current stress on the
secondary-side inductors and diodes. The primary-side switches are commutated with ZVS.
The proposed circuit structure is especially suitable for generating low voltages for
the on-board applications of metro trains from the widely used 1.5 kV or 3 kV dc line in a
single step. Moreover, as the switching devices on the primary side withstand a fraction of
the input voltage only, the most popularly chosen 500/600 V MOSFETs can be used in the
proposed circuit with several kilovolts supply voltage, allowing for a higher operation
frequency and lower conduction losses.
A 1500/48 V, 2 kW prototype with four switch pairs has been designed,
implemented and evaluated. The experimental results prove the soft-switching behavior
and low voltage stress of the primary-side switches, and low current flowing through the
rectifier’s diodes and inductors.
Chapter 3-61
3.2. Generalized Circuit Structure and Its Operation Principle
3.2.1. Circuit Structure
Fig. 3.1 General structure of the proposed multi-level multi-phase dc-dc converter.
Fig. 3.2 Circuit structure of the (k-1)-th and k-th switch pairs and rectifier branches.
The generalized structure of the proposed converter is shown in Fig. 3.1. It is
formed by n switch pairs on the primary side and an n-phase isolation transformer with
Chapter 3-62
turns-ratio m. The primary windings are connected to the switch pairs with each winding
having a series-connected dc-blocking capacitor, while the secondary windings are
connected to an n-phase rectifier. The dc-blocking capacitors have the same value. There
are n dc-link capacitors C1, C2, …, Cn of the same capacitance to split equally the input
voltage Vin. Each switch pair SPk is connected across a dc-link capacitor Ck (k = 1, 2, …, n).
The structure of the (k-1)-th and k-th switch pairs and associated rectifier branches is shown
in Fig. 3.2. The dc-blocking capacitors connected to the primary windings are CW1, CW2, …,
CWn. Each switch pair contains two switching devices, SkU and SkD (with the built-in diode-
capacitor pairs DkU-CkU and DkD-CkD) operated in anti-phase. The switching patterns applied
to the two adjacent switch pairs have a phase difference of 360 n . The output current is
shared by n identical parallel diode-inductor branches D1-Lf1, D2-Lf2, … and Dn-Lfn to reduce
the current stress of the inductors to one-nth of the load current.
3.2.2. Operation Principle
(a) Timing diagram in one steady-state cycle.
Chapter 3-63
(b) Detailed timing diagram of the k-th switch pair in the k-th interval of Ts.
Fig. 3.3 Operation timing diagram of the proposed converter.
Chapter 3-64
The output voltage is regulated by varying the duty cycle, the same in each switch
pair. Fig. 3.3(a) gives the timing diagram of the proposed converter in one switching cycle
and Fig. 3.3(b) presents the detailed operation timing diagram of the k-th switch pair in the
k-th interval Ts /n. The duty cycle D is defined by the on-time of upper switch SkU over the
total duration of the k-th interval, Ts /n. A dead time is added for soft-switching transitions.
The operation modes for the switch pair SPk are theoretically analyzed based on the
following assumptions: a) the equivalent parasitic capacitors paralleled with each MOSFET
are of the same value Cs, b) the input voltage is shared evenly by the n input capacitors (this
will be proved in Section 3.3), and c) the leakage inductances of each transformer winding
have an identical value of Llk. The status of the other switch pairs keeps unchanged during
the discussed time interval. vWx denotes the voltage on the primary winding Wx, vwx denotes
the voltage across the secondary winding wx, iWx denotes the primary current flowing
through Wx, ipx denotes the primary-side current circulating through the switches, or their
parasitic capacitances, of switch pair SPx, and iDx is the current flowing through diode Dx.
During the considered k-th interval: [tk0, tk0+Ts /n], with the exception for the switches in the
pair SPk, all the other switches do not change their status: all the upper switches are in the
off-state and all the lower switches are in the on-state. Similarly, all the rectifier diodes,
except Dk, are conducting in a freewheeling mode.
Generally, the converter transfers energy when the upper switch of the k-th switch
pair SPk is on and then enters into the freewheeling stage until another energy transfer stage
begins after the upper switch of the (k+1)-th switch pair SPk+1 is on. Therefore, the energy
transferred from primary-side to secondary-side is in a sequential manner in one steady-
state cycle, allowing for an interleaved operation of the output inductors. During the
Chapter 3-65
transition intervals, the freewheeling currents in the primary-side or output inductor
currents are used for providing the ZVS conditions for turning on MOSFETs. The detailed
analysis allowing for steady-stage analysis and design of the prototype in Section 3.3 and
Section 3.4 are given based on the following equivalent operation modes shown in Fig. 3.4.
(a) Mode k_0 [Before tk0].
(b) Mode k_1 [tk0, tk1].
Chapter 3-66
(c) Mode k_2 [tk1, tk2].
(d) Mode k_3 [tk2, tk3].
(e) Mode k_4 [tk3, tk4].
Chapter 3-67
(f) Mode k_5 [tk4, tk5].
Fig. 3.4 Operation modes of the k-th switch pair in the k-th interval of a switching cycle.
Mode k_1 [tk0, tk1]: Before tk0, as shown in Fig. 3.4 (a), the upper switches S(k-1)U and
SkU are off and the lower switches S(k-1)D and SkD are on. Capacitor CkU is charged at Vin /n.
The converter is in a freewheeling mode. The values of the currents before tk0 will be
proven in Section 3.3.4. They are iW(k-1)(tk0) = (n-1) io /(mn2), iWk(tk0) = -io /(mn2), iWx (x =1,
2,… ,n, x ≠ k-1, k) = -io /(mn2), iD(k-1)(tk0) = 0, iDk(tk0) = 2io /n, iD(k+1)(tk0) = io /n, iDx (x =
1,2,… ,n, x ≠ k-1,k, k+1) = io /n. The voltages across the primary windings at tk0 are zero.
At tk0, SkD is switched off with ZVS due to the presence of CkD. CkU is discharged
and CkD is charged in a resonant manner, providing the ZVS condition for SkU turn on at tk1.
In this mode, the voltage across CkD,vCkD, increases from 0 to Vin /n, and the voltage on CkU,
vCkU, decreases from Vin /n to 0. It can be assumed that the voltage across the dc-blocking
capacitor CW(k-1) keeps constant within one steady-state cycle with value of Vin /n (this will
be proved in Section 3.3.3). According to Fig. 3.4(b), from a KVL equation written in the
loop formed by S(k-1)D in on-state, CW(k-1), CkU and primary winding Wk-1, it results that vW(k-1)
goes from a zero value to a negative one (-Vin /n). Similarly, by writing a KVL equation in
Chapter 3-68
the following loop, formed by CkD, Ck+1, CWk and primary winding Wk, it results that vWk
increases from zero to a positive value Vin /n. Therefore
00( ) ( ) cos( ) cos( )pk pk k
ii t i t t t
mn (3.1)
( ) sin2
in o lkCkU
s
V i Lv t t
n mn C (3.2)
( ) sin2
o lkCkD
s
i Lv t t
mn C (3.3)
( 1)( ) ( ) sin2
o lkWk C k CkD CWk
s
i Lv t V v t V t
mn C (3.4)
( 1) ( 1)( ) ( ) sin2
o lkW k CkU CW k
s
i Lv t v t V t
mn C (3.5)
0 2
1( ) ( ) ( ) 1 cos
2o o
Wk Wk k Wklk
i ii t i t v t dt t
L mn mn (3.6)
( 1) ( 1) 0 ( 1) 2
11( ) ( ) ( ) 1 cos
2o o
W k W k k W klk
n i ii t i t v t dt t
L mn mn
(3.7)
where 1 lk sL C .
Taking into account that iDx= iLfx - isecx (x = 1, 2, …, n) and that the inductor currents
keep their values at the transition instant, it results
( 1)( ) ( ) ( ) ( ) 1 cosoDk Lfk Wk W k
ii t i t m i t i t t
n (3.8)
( 1) ( 1) ( 1) ( 2)( ) ( ) ( ) ( ) 1 cos( )2
o oD k Lf k W k W k
i ii t i t m i t i t t
n n (3.9)
( 1) ( 1) ( 1)( ) ( ) ( ) ( ) 1 cos( )2
o oD k Lf k W k Wk
i ii t i t m i t i t t
n n (3.10)
Chapter 3-69
Diode Dk-1, which is off in the previous Ts /n period, starts conducting because the
primary-side current ip(k-1) becomes smaller than the corresponding reflected output inductor
current iLf(k-1), indicating the transition from an energy transfer mode to a freewheeling
mode of this rectifier branch.
During the first mode, all the diodes are on. Therefore, the converter is still in the
freewheeling mode. This mode ends when vCkD reaches Vin /n and vCkU decreases to zero.
From (3.2), the duration of this mode is given by
101 1 0
21sin in
k k k
o lk s
mVt t t
i L C
(3.11)
Mode k_2 [tk1, tk2]: As vCkU (tk1) = 0, DkU conducts naturally. After a while, SkU turns
on with ZVS. The primary-side current ipk increases linearly, remaining less than the
reflected output inductor current iLfk. Therefore, the converter is still in the freewheeling
stage. According to Fig. 3.4(c)
( 1)( ) ( ) /Wk CkD C k CWk inv t v t V V V n (3.12)
( 1) ( 1)( ) /W k CW k inv t V V n (3.13)
1 2
1( ) ( ) ( ) o in
Wk Wk k Wklk lk
i Vi t i t v t dt t
L mn nL (3.14)
( 1) ( 1) 1 ( 1) 2
11( ) ( ) ( ) o in
W k W k W klk lk
n i Vi t i t v t dt t
L mn nL
(3.15)
( 1)
2( ) ( ) ( ) o in
pk Wk W klk
i Vi t i t i t t
mn nL (3.16)
( 1) ( 1) ( 2)( ) ( ) ( ) o inp k W k W k
lk
i Vi t i t i t t
mn nL (3.17)
Chapter 3-70
( 1) ( 1)( ) ( ) ( )k
inp W k Wk
lk
Vi t i t i t t
nL (3.18)
2 2( ) ( ) ( ) 1 coso o in
Dk Lfk pklk
i i mVi t i t mi t t t
n n nL (3.19)
( 1) ( 1) ( 1)( ) ( ) ( ) inD k Lf k p k
lk
mVi t i t mi t t
nL (3.20)
( 1) ( 1) ( 1)( ) ( ) ( ) o inD k Lf k p k
lk
i mVi t i t mi t t
n nL (3.21)
During this mode, the leakage inductance of the winding Wk is charged. The mode
ends when ipk reaches the reflected secondary-side current io /(mn), indicating the end of the
freewheeling stage. During this mode, the primary winding Wk is supplied with voltage
Vin /n, while the voltage across the corresponding secondary winding wk is zero (the
secondary side is still in freewheeling mode, even if the primary-side switch is turned on
with the purpose of starting the transfer of energy. This phenomenon is typical for ZVS in
FB converters), resulting in a duty cycle loss. According to (3.16), the duration of this
interval is given by
12 2 1o lk
k k kin
i Lt t t
mV (3.22)
At the end of the second mode, Dk turns off with ZCS according to (3.19) and (3.22).
At the instant tk2, according to (3.14)-(3.21), the values of the currents are: iWk(tk2) = (n-1)io
/(mn2), iW(k-1)(tk2) = -io /(mn2), ipk(tk2) = io /(mn), ip(k-1)(tk2) = 0, ip(k+1)(tk2) = -io /(mn), iDk(tk2) =
0, iD(k-1)(tk2) = io /n, and iD(k+1)(tk2) = 2io /n.
Mode k_3 [tk2, tk3]: The converter enters the energy-transfer stage. The voltages
across primary windings vWk and vW(k-1) are Vin /n and -Vin /n, respectively. In the secondary
side, the winding voltages vwk and vw(k-1) become the reflected voltage values of associated
Chapter 3-71
primary windings: Vin /(mn) and -Vin /(mn), respectively. The currents on both primary and
secondary sides are constant, by assuming that the current variations in the output inductors
are negligible.
Mode k_4 [tk3, tk4]: According to the controlled PWM signal, SkU is turned-off at tk3
with ZVS due to the parallel capacitance across the switch. The converter is commutated
from the energy-transfer stage to the freewheeling stage. CkU and CkD are charged and
discharged respectively by ipk /2
1( ) ( )
2 2o
CkU pks s
iv t i t dt t
C mnC (3.23)
1
( ) ( )2 2
in in oCkD pk
s s
V V iv t i t dt t
n C n mnC (3.24)
( 1)( ) ( ) ( )2
in oWk C k CkD CWk CkD
s
V iv t V v t V v t t
n mnC (3.25)
( 1) ( 1)( ) ( )2
in oW k CkU CW k
s
V iv t v t V t
n mnC (3.26)
This mode ends when CkD is fully discharged. According to (3.24), the duration is
34 4 3
2 in sk k k
o
mV Ct t t
i (3.27)
Mode k_5 [tk4, tk5]: At tk4, the body diode of SkD conducts naturally. Therefore, SkD
can be turned on with ZVS subsequently. From KVL written in the same loops as in the
first Mode, it results that the voltages across primary-side and secondary-side windings are
zero and no energy is transferred from the primary-side to secondary-side. The converter
operates in a new freewheeling stage. All of the currents keep constant and remain the
values as the ones calculated at the instant tk2 during the third, fourth and fifth modes.
Therefore,
Chapter 3-72
2 2
1( ) , ( ) , ( 1, 2, , , )o o
Wk Wx
n i ii t i t x n x k
mn mn
(3.28)
2 2
1( ) , ( ) ,( 1, 2, , )o o
wk wx
n i ii t i t x n x k
n n
(3.29)
( 1)( ) , ( ) , ( ) 0,( 1, 2, , , 1)o opk p k px
i ii t i t i t x n x k k
mn mn (3.30)
( 1)( ) , ( ) , ( ) 0,( 1, 2, , , 1)o oseck sec k secx
i ii t i t i t x n x k k
n n (3.31)
( 1)
2( ) 0, ( ) , ( ) , ( 1,2, , , 1)o o
Dk D k Dx
i ii t i t i t x n x k k
n n (3.32)
For the other n-1 Ts /n intervals in Fig. 3.3(a), the converter operates in a similar
manner.
3.3. Steady-State Analysis
3.3.1. DC Voltage Conversion Ratio and Duty Cycle Loss
During the analyzed k-th interval, the transfer of power from input to load occurs
during Mode k_3 by neglecting the energy transferred during the switching transition tk34
for ZVS. An input-output energy balance written for a Ts /n interval gives
3
201 12( )
k
k
tin in o s s
pk k k o ot
V V i DT Ti t dt t t V i
n n mn n n (3.33)
tk01 is very short and thus negligible compared to tk12. Therefore, according to (3.22) and
(3.33), the conversion ratio M and duty cycle loss Dloss are given by
2
1o o lk
in in s
V ni LM D
V mn mV T
(3.34)
Chapter 3-73
o lkloss
in s
ni LD
mV T (3.35)
3.3.2. ZVS Load Range
For the lower switch SkD, the energy stored in both output inductor and leakage
inductor provides the ZVS turn-on condition. However, for turning on the upper switch SkU,
as illustrated in Mode k_1, only the energy stored in the leakage inductor is used to
discharge the parallel capacitor CkU. Therefore, the ZVS load range is determined from (3.2)
by the condition that vCkU reaches zero
2 21 1
22 2 2
o lk ins
i L VC
mn n
(3.36)
Moreover, the durations of the left and right dead time between the two PWM
signals of each switch pair should be long enough to fully discharge the parasitic capacitor
voltage
101
21sin in
dl k
o lk s
mVt t
i L C (3.37)
34
2 in sdr k
o
mV Ct t
i (3.38)
where tdl and tdr are the dead time of left and right sides respectively.
3.3.3. Self-Balancing Mechanism of Switch-Pair Voltage
Fig. 3.5 represents a voltage loop during the freewheeling stage shown in Fig. 3.4(f).
Let Vin(k-1) and Vink denote the voltages across the input capacitors Ck-1 and Ck, respectively.
During the freewheeling stage, the voltage across the transformer winding Wk-1 is zero,
Chapter 3-74
implying an equality between the voltages on capacitors Ck and CW(k-1). In case that a
perturbation occurs, the current through the loop will equalize the two capacitor voltages.
1 inkCW kV V (3.39)
Fig. 3.5 Voltage loop during the freewheeling stage of k-th switch pair.
In practice, the voltage across the dc-blocking capacitor CW(k-1) is relatively constant
over one switching cycle. From KVL written in a loop formed by C(k-1)D, CkU, CW(k-1) and
Wk-1 in Fig. 3.2, as the winding average voltage is zero in a steady-state cycle, it results that
( 1) ( 1) 1CW k CW k CkU C k DV v v v , where CkUv and 1C k Dv represent the average value over
a cycle. Referring to Fig. 3.3(b), the average voltage vCkU in one cycle is given by
Chapter 3-75
0 1 2 3 4 0
0 0 1 2 3 4
1 4
0 334
( ) ( ) ( ) ( ) ( ) ( )
( ) 0 0 ( )
s k k k k k s k
k k k k k k
k k
k k
T t t t t t T t
CkU CkU CkU CkU CkU CkUt t t t t tCkU
s st t
sCkU CkU s k k inkt t
s
v t dt v t dt v t dt v t dt v t dt v t dtv
T TT
v t dt v t dt T D t Vn
T
(3.40)
where Dk is the duty cycle of switch pair SPk. In Mode k_1, as the duration tk01 is very
short, sin t t , (3.2), (3.11), (3.23), (3.27), (3.40) give
1 kCkU ink
Dv V
n
(3.41)
Similarly, the average voltage vC(k-1)D in one cycle is given by
1
1 1 ( 1)kC k D in k
Dv V k
n
(3.42)
where Dk-1 (k ≠ 1) is the duty cycle of switch pair SPk-1.
According to (3.41)-(3.42),
( 1) 11 1
1( 1)CW k CkU ink k in k inkC k D kV v v V D V D V k
n (3.43)
Substituting (3.43) into (3.39), one gets
( 1)
( 1)
( 1)kink
in k k
DVk
V D
(3.44)
A simple control scheme with only one voltage loop is configured for the proposed
converter. A pair of PWM signals is generated and then shifted by times of 360 n to drive
other switch pairs. Therefore, by neglecting tiny differences that could appear in the shifting
process, the duty cycles of the generated PWM driving signals are the same. Duty cycle
imbalances caused by the mismatched driver dead time and MOSFET switching
characteristics can be removed by system calibration [170], implying a negligible difference
Chapter 3-76
between Dk and Dk-1. As a result, regardless of the capacitors values, the voltage distribution
on each input capacitor will reach parity after a few switching cycles from start-up or other
dynamic perturbations, except for no load condition. According to (3.39), it implies that the
voltage across the dc-blocking capacitor CW(k-1) is equal to Vin/ n.
3.3.4. Steady-State Current Distribution in the Transformer Windings
It is essential to study the steady-state current distributions in the transformer
windings, therefore, to verify the initial values used for analysis of the first mode in Section
3.2. As shown in Fig. 3.3(a), there are n energy-transfer stages in one cycle. The current
in each output inductor is considered to have a constant value io /n. As diode Dx is blocked
in the x-th energy-transfer stage (x = 1, 2, …, n),
1,1 ,1 1
2,2 1,2 2
, ( 1),
stage1: /
stage 2: /
stage : /
w wn Lf o
w w Lf o
wn n w n n Lfn o
i i i i n
i i i i n
n i i i i n
(3.45)
where iwj,k denotes the current through the secondary-side winding wj in the k-th energy
transfer stage.
It can be observed from Fig. 3.3(b) that a winding current changes its value only
two times in a steady-cycle Ts. Such a change can take place only in the first two operation
modes after the transition from a Ts /n interval to the next Ts /n interval. For example, iwk,
which is -io /n2 before the beginning of the k-th interval, will change to (n-1)io /n
2 during the
first two modes of the k-th interval and will change again to -io /n2 after the transition to the
(k+1)-th interval. Therefore, during the transition from the k-th energy-transfer stage to
(k+1)-th energy-transfer stage, the currents in the corresponding two adjacent windings wk
Chapter 3-77
and wk+1 decrease and increase respectively by the same amount of current defined as i ,
and those in other secondary windings keep constant. It can be shown that
1,1 1, 2,1 2, ( 1),1 ( 1), ,1 ,
1,2 1,1 2,2 2,1 3,2 3,1 ,2 ,1
1, 1,( 1) ( 2), ( 2), 1 ( 1), ( 1), 1 , , 1
, , , ,
, , , ,
, , , ,
w w n w w n w n w n n wn wn n
w w w w w w wn wn
w n w n w n n w n n w n n w n n wn n wn n
i i i i i i i i i i
i i i i i i i i i i
i i i i i i i i i i
(3.46)
Considering that the initial current of the transformer is
1, 2, , 0w k w k wn ki i i (3.47)
By solving (3.45)-(3.47), one gets
, ,2 2
1/ , , ( 1,2, , , and )o o
o wk k wx x
n i ii i n i i x n x k
n n
(3.48)
Therefore, the current distribution in the primary windings during steady-state is
given by
, ,2 2
1, ( 1,2, , , and )o o
Wk k Wx x
n i ii i x n x k
mn mn
(3.49)
According to (3.48), the currents in the secondary windings of the isolation
transformer at the beginning of the k-th stage are given by
( 1) 0 2
1( ) o
w k
n ii t
n
(3.50)
0 2( ) ( 1,2, , , and 1)o
wx
ii t x n x k
n (3.51)
Based on (3.50)-(3.51), the initial currents flowing through the primary windings
and rectification diodes of the analyzed k-th interval in Section 3.2 are given by the
following equations (3.52) and (3.53), respectively.
Chapter 3-78
( 1) 0 2
0 2
1( )
( ) ( 1,2, , , and 1)
oW k
oWx
n ii t
mni
i t x n x kmn
(3.52)
( 1) ( 1) ( 1) ( 2)
( 1)
( 1)
( ) 0
2( )
( ) ( 1, 2, , 1, )
D k Lf k w k w k
oDk Lfk wk w k
oDx Lfx wx w x
i t i i i
ii t i i i
ni
i t i i i x n x k kn
(3.53)
3.4. Design Considerations
3.4.1. Design Specifications
Design considerations are presented for the specified prototype shown in Table 3.1.
The variation of the input voltage is within ±10% of the nominal value 1500 V. A
converter with four switch pairs are selected here as a demonstration example, i.e. n = 4.
Table 3.1Design specifications of the proposed dc-dc converter with four switch pairs.
Items Values Units Remarks
Vin,min 1350 V minimum input voltage
Vin,rated 1500 V rated input voltage
Vin,max 1650 V maximum input voltage
Vo 48 V output voltage
P 2000 W rated output power
f 50 kHz switching frequency
n 4 number of modules
∆Io 10 % current ripple
∆Vo 1 % voltage ripple
Th 20 ms hold-up time from 1500V to 1200V
Deff,designed 0.5 designed effective duty cycle
Chapter 3-79
3.4.2. Turns Ratio of the Isolation Transformer (m)
According to (3.34),
2in eff om V D n V (3.54)
where eff o lk in sD D ni L mV T . By substituting n = 4, Vin = 1500 V, Vo = 48 V, Deff,min =
0.5 into (3.54), it results in m = 0.977. Thus, the value of m is practically chosen to be close
to such theoretical value.
3.4.3. Design of the Value of the Leakage Inductance (Llk)
The leakage inductance is a very crucial parameter to determine the duty cycle loss
and soft-switching range as shown in (3.35) and (3.36), which are represented in Fig. 3.6
and Fig. 3.7. It can be observed that a lower inductance value is beneficial to reducing the
duty cycle loss while narrowing the soft-switching range. Therefore, a trade-off design
between duty cycle loss and ZVS load range is considered. Consequently, Llk is selected
with the value of 20 μH to achieve soft-switching from a 60% load and above. The duty
cycle loss at nominal load will be 0.11 accordingly. It should be noted that the leakage
inductance of isolation transformer depends on the design and fabrication process conducted
by the manufacturer. On the one hand, it is unnecessary to design transformers with the
required leakage inductance because an external inductor can be placed in series with the
primary windings of the transformer. On the other hand, the leakage inductance is usually
pre-determined, provided by the manufacturer. The components used in the converter are
thus designed with the leakage inductance.
Chapter 3-80
Fig. 3.6 Duty cycle loss versus leakage inductance under different loading condition
(Vin = 1500 V, Io,rated = 41.7 A, m = 1, n = 4, fs = 50 kHz).
Fig. 3.7 Minimal load for soft-switching versus leakage inductance
(Vin = 1500 V, Io,rated = 41.7 A, m = 1, n = 4, fs = 50 kHz).
0,00
0,05
0,10
0,15
0,20
0,25
0,30
0 5 10 15 20 25 30 35 40 45 50
Dut
y cy
cle
loss
Leakage inductance (µH)
10% load30% load50% load80% load100% load
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 5 10 15 20 25 30 35 40 45 50
Sta
rtin
g po
int o
f so
ft-s
wit
chin
g I o
/Io,
rate
d
Leakage inductance (μH)
Chapter 3-81
3.4.4. Design of Output Inductors (Lf)
Fig. 3.8 Rectifier inductor currents and output current (n = 4).
Fig. 3.8 shows the relationships between the theoretical inductor current of each
rectifier branch (phase) and the output current with n = 4. Assuming that the inductors are
identical (i.e. Lf1 = Lf2 =…= Lfn) one can obtain the phase current ripple
1 eff o sLfk
f
D V Ti
n L
(3.55)
The output current ripple is given by
1 o so eff
f
V Ti D
L (3.56)
Therefore, the output current ripple is reduced to 1 eff effn D n D times of the
phase current ripple. For n = 4, Deff = 0.5, the output current ripple will be 57% of the phase
current ripple. The output inductor is designed according to the required oi in Table 3.1 as
Chapter 3-82
min ,min1 o sf eff
o
V TL D
i
(3.57)
For each phase, an inductor with a value of 124 µH is chosen.
3.4.5. Design of Output Capacitor (Co)
The output voltage ripple ov and RMS current of the capacitor ,Co rmsI are given by
_/
8 2oo ESR Co s
oo
i Ri T nv
C
(3.58)
,
3
6Co rms oI i (3.59)
The capacitance Co, equivalent series resistance (ESR) RESR_Co, and ripple current
rating IAC of the capacitor are selected to ensure that the output voltage ripple is less than 1%
of the nominal value, and ICo,rms is lower than IAC. Accordingly, two capacitors with Co =
220 µF, RESR = 212 mΩ and IAC = 1.49 A are used in parallel for the testing prototype. The
power dissipation of the output capacitor is approximately equal to 2 12o ESRi R .
3.4.6. Design of Input Capacitors and DC-Blocking Capacitors
The input capacitor voltage ripple and hold-up time are used to choose the values of
the input capacitors. By neglecting the transition period tk01 and tk34, the current flow
through capacitor Ck,
2 2k
eff oeff o oC in pk
n D iD i ii i i
mn mn mn
when the upper switch SkU is
on, and 2k
eff oC in
D ii i
mn when SkU is off. Therefore, the voltage ripple on the capacitor Ck
is given by
Chapter 3-83
_
2 2k
k
eff o eff s eff o ESR C
Ck
n D i D T n D i RV
mn C mn
(3.60)
where _ kESR CR is the ESR of the selected capacitors to ensure
kCV is within 1% of Vin /n.
The input capacitors are designed by considering the 20 ms hold-up time from 1500 V to
1200 V. It results in
2 2, ,
2 o hin
in rated in drop
PTC
V V
(3.61)
where Th is the designed hold-up time, Vin,rated is the nominal input voltage, Vin,drop is the
designed voltage drop within the hold-up time period, and η is the designed efficiency (η =
90% for calculation). The minimum calculated value Cin is 109.7 μF. Accordingly, four
400 V (450 V surge) 680 μF electrolytic capacitors with ESR of 150 mΩ at 100 Hz are
selected for C1-C4.
Film capacitors are selected for the dc-blocking due to their high current capability
and low ESR properties. In dc-dc converter applications, the selection of film capacitors
applied for dc-blocking mainly depends on the required capacitance limited by voltage
ripple. By neglecting the transition intervals, according to Fig. 3.3, the voltage ripples of
the dc-blocking capacitors are given by
2
( 1)1 o sCWk
Wk
n i TV
C mn n
(3.62)
The value of the capacitance is designed to ensure the voltage ripple of each
capacitor is less than 2.5%. In the prototype, the voltages across CW1, CW2, CW3 are Vin /4
and the voltage stress of CW4 is (3 /4) Vin. Accordingly, 400 V/4.7 µF metallized polyester
film capacitors with measured ESR of 14.3 mΩ at 50 kHz are selected for CW1, CW2, CW3 and
Chapter 3-84
1200 V/1.5 µF metallized polypropylene film capacitor with measured ESR of 9.9 mΩ at 50
kHz is chosen for CW4.
3.4.7. Selection of MOSFETs and Diodes
The voltage stresses of the MOSFETs are Vin /n and the current stresses are io /mn.
The voltage stresses of the secondary-side diodes are Vin /(mn) while their average currents
are io /n. According to the specifications, 600 V/35 A MOSFETs (SPW35N60CFD) and
600 V/ 15 A diodes (FFH15S60S) are used.
Table 3.2 shows the design cases for different level of input voltage. The designed
number of switch pairs, associated turns-ratio of the transformer and voltage rating of
MOSFET are given to convert the input voltages to 48 V. It can be noted that in all these
cases, the widely used 500 or 600 V MOSFET can serve for implementing the proposed
converters.
Table 3.2 Number of switch pairs, turns ratio of transformer and voltage rating of
MOSFET for specific input voltage.
Vin (V) n m Rating of MOSFET VDS (V)
600 2 3:2 500
750 2 15:8 600
1000 3 6:5 500
1500 4 1:1 600
2000 4 4:3 600
3000 6 1:1 600
Chapter 3-85
3.5. Experimental Verifications
Based on the specifications given in Table 3.1, a 2 kW 1500 V / 48 V prototype with
four switch pairs has been built and tested as shown in Fig. 3.9. It should be noted that the
four phase transformer is carried out with four separate cores (i.e., four single phase
transformers) in the prototype. The experimental results are shown in Fig. 3.10-Fig. 3.16.
Fig. 3.9 Photo of the experimental prototype.
The PWM driving signals for switch pairs SP1 and SP2 are measured as shown in
Fig. 3.10. All of the values are measured at the point when the PWM signals increase to 50%
of their high level. The duty cycles for SP1 and SP2 are 0.608 and 0.606, respectively,
implying a negligible difference. The left and right dead times between driving signals for
upper and lower switch in one switch pair are 360 ns. The phase shift angle between the
observed two switch pairs is 90.4°, which is very close to the theoretical value of 90°.
Chapter 3-86
Fig. 3.10 Measured PWM driving signals for switch pairs SP1 and SP2
(vGS1U, vGS1D, vGS2U and vGS2D: 10 V/div, Timebase: 2 µs / div).
Fig. 3.11 gives the switching waveforms of switch pair SP1 under various loading
condition (i.e. 100%, 80% and 60% of the nominal load). It can be observed that both
switching transistors are turned on/off with zero-voltage, implying a negligible switching
loss. With load variations, the reflected load current in the primary-side changed; therefore,
the slopes of the MOSFET voltages have a small difference during the ZVS commutation
intervals. The voltage stresses on the two switches are only one-fourth of the total input
voltage. The switching waveforms of other switche pairs are similar with those of SP1.
Chapter 3-87
Fig. 3.11 ZVS turns on/off of one switch pair under different loading condition
(vGS1U and vGS1D: 10 V/div, vS1U and vS1D: 200 V/div, Timebase: 200 ns/div).
Chapter 3-88
Fig. 3. 12 Waveforms of transformer primary-side winding current iW1, voltage of S1D
and driving signals for the switch pair SP1.
Fig. 3.13 Waveforms of output inductor currents.
Chapter 3-89
Fig. 3.14 Waveforms of driving signals and currents in one rectification branch.
Fig. 3.12 shows the waveform of the current iW1 flowing through the primary-side
winding of the isolation transformer. The current stresses, thus, the conduction losses of the
primary-side switches depend on the primary-side currents in the isolation transformer
windings.
Fig. 3.13 presents the waveforms of the four output inductor currents. Due to the
self-balancing mechanism of the input capacitor voltages and well-balanced power stage
design, the prototype shows a good performance of output phase current sharing among
different rectification branches, with Ts /4 phase shift between two adjacent inductor currents.
It can be observed from the waveforms that the discrepancy between the largest inductor
current and smallest inductor current is 0.96 A, which is acceptable when considering the
design margin of the output inductors.
Chapter 3-90
Fig. 3.14 gives the inductor and diode currents in one rectifier branch. It can be
noted that both the current stress of the inductor and average current of the diode are 1/n of
the output current. Therefore, the magnetic size of the inductors and the conduction loss of
the diodes are reduced, giving an improved efficiency and well thermal distribution. The
waveforms are in a good agreement with the theoretical analysis.
The efficiency is measured at different loading condition, starting at light load
where ZVS is lost, and up to nominal load. The results are plotted in Fig. 3.15. The
efficiency measured at around nominal power rating (Po = 2023 W) is 90.75%. The power
losses in different components are measured under full load as shown in Fig. 3.16. The
input power is 2229.2 W and the ratios between the power loss in specific component and
input power are also indicated in the figure. It can be noted that the major losses are in the
passive components, i.e. isolation transformers, output inductors and rectifiers, while the
total loss in the MOSFETs is only 2.51% of the input power. It implies that the power loss
of the MOSFETs is dominantly induced by the conduction loss and their switching loss is
negligible with the aid of ZVS switching.
Chapter 3-91
Fig. 3.15 Measured efficiency under various loading condition.
Fig. 3.16 Measured losses in the components under full load (Pin = 2266.8 W and the ratios
between the power loss in specific component and input power are indicated in percentage).
60
65
70
75
80
85
90
95
100
800 1000 1200 1400 1600 1800 2000 2200
Eff
icie
ncy
(%)
Output power (W)
Hard-switching Soft-switching
Chapter 3-92
3.6. Chapter Summary
A generalized circuit structure for high input voltage dc-dc power conversions is
presented. It performs the conversion from several kilovolts to a low voltage of 48 V in a
single step. The voltage stress on the primary-side switches and the current stress in the
secondary-side inductors/diodes are reduced to 1/n of the input voltage and output current,
respectively. Therefore, it allows the use of MOSFETs with low voltage rating and diodes
with low current rating. ZVS of the switching devices achieves a negligible switching loss.
The voltages across the input capacitors and the currents through the output inductors are
well-balanced due to the intrinsic self-balancing mechanism. The current multiplier with
interleaved rectification in the secondary-side reveals high current capacity and reduced size
of magnetic components. The experimental evaluations on a 1500 /48 V 2 kW prototype
with four switch pairs verify the theoretical analysis. An efficiency of 90.75% is obtained
at nominal load. Compared with other available topologies, as shown in Table 3.3, the
proposed structure represents the optimum one with respect to the voltage stress on the
switches and number of switches. Especially, compared with FB- based ISOP converters,
the proposed converter withstands the same voltage stress, however, halves the number of
switches.
Table 3.3 Comparison of number of switches and voltage stresses in different topologies.
Topology No. of switch Voltage stress
FB converter 4 Vin
TL converter 4 Vin / 2
FB based ISOP converter
4n Vin / n
Proposed converter 2n Vin / n
Chapter 4-93
CHAPTER 4
HIGH INPUT VOLTAGE THREE-LEVEL DC-DC CONVERTER WITH
ASYMMETRIC VOLTAGE DISTRIBUTION ON SWITCH PAIRS
4.1. Introduction
This chapter presents a power conversion concept with asymmetric distribution of
the high input voltage among switch pairs in multi-level dc-dc converters. Instead of same
voltage stress on the primary-side switches as those discussed in Chapter 3, it is
intentionally control the voltage distribution among the switch pairs by applying different
duty cycles for them.
The advantages of the proposed asymmetric conversion concept are twofold.
Firstly, it provides an additional degree of freedom to choose switching devices, allowing
optimal selection of their voltage ratings and thus overall performance. The low-voltage
switch pairs can be implemented with MOSFETs, and the high-voltage switch pairs with
IGBTs. Secondly, it exhibits new properties which ensure ZVS of the MOSFET switch
pairs started from very light load without additional circuitry for ensuring soft-switching.
Based on the proposed concept, a TL converter with one IGBT switch pair and one
MOSFET switch pair is proposed. Besides the ZVS of the two MOSFETs, an active
snubber is introduced in the secondary-side to assist the ZCS of the two IGBTs. The ZCS
snubber energy is completely released to the load, leading also to a duty-cycle gain.
Therefore, the proposed soft-switching scheme is fundamentally different from ZVZCS and
is named as hybrid ZVS-ZCS. A 2 kW prototype, which performs the same function as the
one discussed in Chapter 3 (i.e., conversion from 1500 V dc to 48 V dc), is built and
evaluated to verify the theoretical analysis.
Chapter 4-94
4.2. Converter with Asymmetric Voltage Distribution
The circuit structure and the concept of the power conversion with asymmetric
voltage distribution on the switch pairs are given as follows.
4.2.1. Circuit Structure
(a) Circuit schematic.
(b) Simplified control block diagram.
Fig. 4.1 Proposed hybrid ZVS-ZCS dc-dc converter with secondary-side ZCS snubber
and asymmetric voltage distribution on primary-side switch pairs.
Chapter 4-95
Fig. 4.1(a) presents the proposed converter with two switch pairs SP1 and SP2,
which are composed of two IGBTs S1, S2, and two MOSFETs S3, S4 connected in series,
respectively. The intermediate stage is a dc-blocking capacitor Cb and high frequency
isolation transformer. The turns-ratio of the transformer from primary-to-secondary is m
and its leakage inductance is Llk. VC1, VC2 and VCb are the voltages across the dc-link
capacitors C1, C2 and the capacitor Cb, respectively. To improve the output current
capacity, a current doubler rectifier [99] is applied in the secondary side, formed by two
inductor-diode branches Lf1-DR1 and Lf2-DR2. A snubber composed of switches Sa1, Sa2,
diode Da, capacitors Cr1, Cr2 and inductor Lr is shown in Fig. 4.1 to fulfill ZCS of S1 and S2.
Sa1 is used to provide ZCS condition for S1 while Sa2 is used to provide ZCS
condition for S2. The function of Sa1 and Cr1 is to reduce isec, and thus ip, from positive
value to zero before S1 turns off. And the function of Sa2, Da, Lr and Cr2 is to increase isec
from negative to zero before S2 turns off.
4.2.2. Conversion Concept with Asymmetric Voltage Distribution
It will be shown in Section 4.4 that the voltages on input capacitors C1 and C2 are
inversely proportional to the duty cycles D1 and D2, implying that
1
2
2
1
D
D
V
Vk
C
C(4.1)
where k is defined as the voltage distribution factor, D1 and D2 are the steady-state duty
cycles of upper switches in each switch pair, S1 and S3. As shown in Table 1.2, the
available solutions distribute the input voltage equally among the switch pairs (i.e., k = 1).
Referring to (4.1), the concept proposed here allows asymmetric voltage stresses on each
Chapter 4-96
switch pair by adjusting the value of k. One of the implications is that it can provide an
additional degree of freedom to select switching devices and allow for optimal
combinations in terms of the operating frequency, switching loss, conduction loss and cost-
effectiveness.
4.3. Operation Principle of the Proposed Converter
A simplified control block diagram illustrating the generation of the driving signals
for S1-S4 and Sa1-Sa2 is presented in Fig. 4.1(b). The asymmetric duty cycles for S1 and S3
are obtained by using different control signals having a ratio of k for the PWM1 and PWM2
modules in the DSP controller. With designed parameters for the ZCS snubber, the
conduction interval of Sa1 and Sa2 are constant. Therefore, the turn on and turn off instants
of Sa1 depends on the turn off time of S1 (i.e., the control signal vcon). Sa2 is turned off at the
end of a switching cycle, implying a fixed turn on time instant. The voltages across C1 and
C2 are also sampled for overvoltage protection and fine tuning k if necessary for limiting the
discrepancy between the actual voltage stress distribution and the desirable one.
The operation consists of nine modes in one switching cycle. The timing diagram
for a steady-state cycle is shown in Fig. 4.2(a). Fig. 4.2(b) and Fig. 4.2(c) show the
detailed operation of the two auxiliary snubber switches Sa1 and Sa2, respectively. For sake
of simplicity, the analysis is referred to the secondary of the transformer. The equivalent
circuits in each operation mode are given in Fig. 4.3. The voltages across the input
capacitors C1, C2, and dc-blocking capacitor Cb are assumed constant in steady-state and
the output inductors Lf1 and Lf2 are large enough to be considered as constant current
sources. The parameters used in the following discussions are listed in Table 4.1.
Chapter 4-97
Table 4.1 Definitions and parameters used in the following analysis.
D1 duty cycle of switch S1 as defined Fig. 4.2(a)
D2 duty cycle of switch S3 as defined in Fig. 4.2(a)
∆D1 net effect on duty cycle D1 due to ZVS duty
cycle loss and ZCS duty cycle gain
∆D2 net effect on duty cycle D2 due to ZVS
duty cycle loss and ZCS duty cycle gain
tdl1 dead-time of gate signal from S2 to S1
tdr1 dead-time of gate signal from S1 to S2
tdl2 dead-time of gate signal from S4 to S3
tdr2 dead-time of gate signal from S3 to S4
Ts switching period of the converter
ti-j time duration from ti to tj (i.e., ti-j = tj- ti)
∆V VC2-VCb
Leq 2 2( / ) || / ( )lk r lk r lk rL m L L L L m L
ωr1 1 2( )lk r rm L C C
Zr1 1 2( )lk r rL C C m
ωr2 1lk rm L C
Zr2 1lk rL C m
ωr3 1 2 lk SL C (Cs3 = Cs4 = Cs)
Zr3 2 lk SL C
ωr4 21 r rL C
Zr4 2r rL C
ωr5 21 eq rL C
Zr5 2eq rL C
Chapter 4-98
(a) General timing diagram during one cycle
Chapter 4-99
(b) Detailed timing diagram during t3 to t5
(c) Detailed timing diagram during t10 to t12
Fig. 4.2 Timing diagram of the proposed converter.
Chapter 4-100
Mode 1 [t0-t1] - Transition from freewheeling stage to energy transfer stage I [Fig. 4.3(a)]
Before S1 is turned on, the currents through diodes DR1 and DR2 keep constant and
the body diode of S2 is conducting as shown in Fig. 4.3(a)-(i) and Fig. 4.3(a)-(ii). When S1
is on, the current in DS2 is diverted to S1 linearly due to the presence of parasitic inductance
LS1 as shown in Fig. 4.3(a)-(iii). After DS2 stops conducting, the current isec increases
linearly due to voltage (VC1+VC2-VCb) /m applied on the leakage inductance Llk /m2. Thus,
the current in DR1 decreases and reaches zero at t1, while that in DR2 increases to the load
current. At t1, current isec increases to iLf1 and DR1 is finally blocked. The duration of this
mode is given by
VVm
tmiiLL
V
tiLtttt
C
SLflkS
C
SSdl
1
12211
1
122111001
)]([)()( (4.2)
where iS2(t12) is the current flowing through DS2 at the instant t12, i.e. at the end of steady-
state cycle, as given by (4.33). The absolute value of iS2(t12) depends on the loading
condition and increases with the reduction of the load. With practical design, at full load,
iS2(t12) is approximately equal to zero while at no load iS2(t12) is -iLf2,nom / m, where iLf2,nom is
the current flowing through Lf2 under the nominal load. Moreover, the duration in which iS1
increases from zero to iLf1/m is very short, as compared to the switching period. To simplify
the analysis, iS1 is assumed to increase linearly from zero to iLf1/m as shown in Fig. 4.2(a)
and the value of LS1 is negligible compared to Llk. Therefore, the duration of t0-1 in (4.2) is
approximated by
VVm
iLt
VVVm
iLtttt
C
Lflkdl
CbCC
Lflkdl
1
11
21
111001 (4.3)
Meanwhile, Lr and Cr2 are in a resonant mode until iSa2 (current flowing through the
body diode of Sa2) reaches zero within t0-1 as shown in Fig. 4.3(a)-(i) and Fig. 4.2(c).
Chapter 4-101
(i)
(ii)
Chapter 4-102
(iii)
(iv)
Fig. 4.3(a) Mode 1 (t0-t1).
Chapter 4-103
Mode 2 [t1-t4]-Energy transfer stage I [Fig. 4.3(b)-(d)]
During this mode, the energy is transferred from the input to the load through the
switches S1 and S4. This mode can be divided into three sub-stages:
Sub-stage I [t1-t2] [Fig. 4.3(b)] - Charging of capacitors Cr1 and Cr2. At t1, the
voltage across the secondary-side winding of the transformer becomes positive, thus, the
diodes DSa1 and Da conduct. Capacitors Cr1 and Cr2 are charged in a resonant manner with
the leakage inductance Llk. The initial value of isec is iLf1. Therefore,
)(sin)( 111
11sec tt
mZVV
iti rr
CLf (4.4)
)(cos1)()( 111
21 ttm
VVtvtv r
CCrrC (4.5)
By referring isec to the primary side,
)(sin)()( 11
12
111 tt
ZmVV
mi
titi rr
CLfpS (4.6)
After one-half resonant cycle, at t2, the capacitor voltages vCr1 and vCr2 reach their
maximum value 2(VC1+ V) / m and the current isec returns to iLf1. The diode DSa1 and Da are
blocked and the voltages of Cr1 and Cr2 are clamped at the maximum level. The time
interval of this sub-stage is equal to half of the resonant cycle, that is
mCCL
ttt rrlk )( 212112 (4.7)
Sub-stage II [t2-t3] [Fig. 4.3 (c)] - Energy transfer with constant isec. During this
sub-stage, all of the voltages and currents in the circuits are assumed constant.
Sub-stage III [t3-t4] [Fig. 4.3 (d)] - Commutation of S1 with ZCS. At t3, Sa1 turns on
Chapter 4-104
with ZCS due to the presence of leakage inductance Llk, which starts resonating with Cr1 to
make the current through S1 drop to zero or become negative. The initial voltage of Cr1 is
vCr1(t3) = 2(VC1+∆V) / m as discussed above. Therefore, it can be obtained that
)(sin)( 322
11sec tt
mZ
VViti r
r
CLf
(4.8)
)(cos1)( 321
1 ttm
VVtv r
CrC
(4.9)
)(sin)( 322
11 tt
mZ
VVti r
r
CSa
(4.10)
It implies that
)(sin)()( 322
211
1 ttZm
VV
m
ititi r
r
CLfpS
(4.11)
When the current through S1 drops to zero, and goes negative, DS1 conducts. S1 is
turned off at t4 with ZCS when iS1 reaches its negative peak value as shown in Fig. 4.2(b)
(iS1 = isec /m). Therefore,
m
VVtv C
rC
1
41 )( (4.12)
m
CLttt rlk
21
4334
(4.13)
Chapter 4-105
Fig. 4.3(b) Mode 2 sub-stage I (t1-t2).
Fig. 4.3(c) Mode 2 sub-stage II (t2-t3).
Chapter 4-106
(i)
(ii)
Fig. 4.3(d) Mode 2 sub-stage III (t3-t4)
Chapter 4-107
Mode 3 [t4-t5]-Transition from energy transfer stage to freewheeling stage I [Fig. 4.3(e)]
After S1 is turned off at t4, isec increases to zero from negative values, and then the
body diode of S1, DS1, is blocked. Therefore, the primary transformer voltage drops as
shown in Fig. 4.2(a). As the diode DR1 is still in the blocking state, iLf1 is fully supplied by
the capacitor Cr1 before S2 is turned on. After S2 is on, Cr1 is further discharged until its
voltage drops to zero as shown in Fig. 4.2(b). The duration of this mode is approximately
equal to
1
115445
)(
fL
Cr
mi
VVCttt
(4.14)
It should be noted that although S1 is off during this period, the diode DR1 is still off
and the resonant energy of Cr1 is released to the load, contributing to a duty cycle gain.
(i)
Chapter 4-108
(ii)
Fig. 4.3(e) Mode 3 (t4-t5).
Mode 4 [t5-t6]-Freewheeling stage I [Fig. 4.3(f)]
As vCr1 reduces to zero at t5, DR1 turns on naturally. iDR1 increases from zero to
iLf1while iSa1 reduces to zero quickly as shown in Fig. 4.2(a) and Fig. 4.3(f)-(i). Therefore,
Sa1 can be turned off with ZCS after a short while since iSa1 becomes zero. The diodes DR1
and DR2 are in freewheeling state. However, unlike that stage with symmetric operation
between two switch pairs in TL converter [43], the current flowing through the transformer
winding isec increases linearly due to a difference of the voltages on C2 and Cb. This
phenomenon is owing to asymmetric operation of the two switch pairs, which will be
investigated in Section 4.5 in detail. As shown in Fig. 4.3(f),
lkL
ttVmti
)()( 5
sec
(4.15)
Chapter 4-109
This mode ends when t = Ts /2 and S4 is turned off with ZVS due to the presence of
its parasitic capacitance CS4. The duration of this mode is
11
6556 2
)1(dr
s tDT
ttt
(4.16)
Accordingly, the current isec at t6 is given by
11566sec )1(
2)()( dr
s
lklk
tDT
L
Vmtt
L
Vmti (4.17)
(i)
Chapter 4-110
(ii)
(iii)
Fig. 4.3(f) Mode 4 (t5-t6).
Chapter 4-111
Mode 5 [t6-t7] - Transition from freewheeling stage to energy transfer stage II [Fig. 4.3(g)]
After S4 is turned off at t6, the equivalent circuit is shown in Fig. 4.3(g). With initial
conditions vCS3(t6) = VC2 and ip(t6) = isec(t6) / m,
)(sin)(2
1)(cos)( 6336633 ttZtittVVtv rrprCbCS (4.18)
)(cos)()(sin2
)( 636633
tttittZ
Vti rpr
rp (4.19)
The process described by (4.18)-(4.19) is the resonance occurred among Llk, CS3 and
CS4. CS3 is fully discharged and CS4 is fully charged by the energy stored in the leakage
inductance. DS3 will conduct when the voltage of CS3 reaches zero as shown in Fig. 4.3(g)-
(ii). This transition takes place in a similar way as the corresponding process in symmetric
FB or TL converters. However, the significant difference lies in that the energy that is
provided by Llk is independent of loading condition, which can be observed from (4.17). It
implies that S3 can be turned on with ZVS from very light load to full load without any
additional assisted strategies. S3 is turned on with ZVS in a short while after DS3 conducts.
The current in DR2 reaches zero at t7 while the current of DR1 increases to the load
current. At t7, the primary-side current ip negatively increases to -iLf2/m. Therefore, the
duration of this mode is given by
VVm
iLtttt
C
Lflkdl
2
227667 (4.20)
Chapter 4-112
(i)
(ii)
Chapter 4-113
(iii)
Fig. 4.3(g) Mode 5 (t6-t7).
Fig. 4.3(h) Mode 6 (t7-t8).
Chapter 4-114
Mode 6 [t7-t8]-Energy transfer stage II [Fig. 4.3(h)]
During this mode, DR1 is conducting and DR2 is blocked. Energy is transferred from
Cb to load through the switches of S2 and S3. All of the voltages and currents in the circuits
can be assumed constant.
Mode 7 [t8-t9]-Transition from energy transfer stage to freewheeling stage II [Fig. 4.3(i)]
At t8, S3 is turned off with ZVS at the presence of CS3. isec starts to charge CS3 and
discharge CS4 with an approximately constant current isec(t8)/2 (i.e. -iLf2/2). This mode ends
when the voltage across CS4 reduces to zero. It implies that
2
2
8sec
29889
2
)(
2
Lf
CsCs
i
VmC
ti
VmCttt
(4.21)
Fig. 4.3(i) Mode 7 (t8-t9).
Chapter 4-115
Mode 8 [t9-t11]-Freewheeling stage II [Fig. 4.3(j)-(k)]
After vCS4 reaches zero, DS4 is conducting to clamp this voltage at zero. S4 can be
turned on with ZVS after t9. Therefore, the duration of tdr2 should be long enough to ensure
vCS4 reaches zero before S4 turns on, that is tdr2 ≥ t8-9. This mode can be divided into two
sub-stages and their equivalent circuits are presented in Fig. 4.3(j)-(k).
Sub-stage I [t9-t10] [Fig. 4.3(j)]- Linear increase of isec. During t9-t11, diode DR1 and
DR2 are conducting and the voltage between the nodes ‘a’ and ‘b’ as indicated in Fig. 4.3(j)
is zero. The secondary-side winding current isec increases slightly from negative values due
to the voltage difference ∆V. It gives that
lk
Lf L
ttVmiti
)()( 9
2sec
(4.22)
Fig. 4.3(j) Mode 8 sub-stage I (t9-t10).
Chapter 4-116
Sub-stage II [t10-t11] [Fig. 4.3(k)]- Resonance between Lr and Cr2. Cr2 starts to
resonate with Lr after Sa2 turns on with ZCS at t10 as shown in Fig. 4.2(c). The equivalent
circuit is presented in Fig. 4.3(k) with the initial value of vCr2(t10) = 2 (VC1+∆V) / m,
implying that
)-(cos)(2
)( 1041
2 ttm
VVtv r
CCr
(4.23)
)-(sin )(2
)( 1044
12 tt
mZ
VVti r
r
CSa
(4.24)
This mode ends when vCr2 drops to zero at t11, therefore, the duration of this sub-stage is
2
211101011
rrCLttt
(4.25)
4
1112
)(2)(
r
CSa mZ
VVti
(4.26)
According to (4.22), by neglecting the short period of tdr2 and t11-12, one gets
lk
sLf L
VTDmiti
2
)1()( 2
211sec
(4.27)
Chapter 4-117
Fig. 4.3(k) Mode 8 sub-stage II (t10-t11).
Mode 9 [t11-t12]-Energy transfer stage induced by Cr2 [Fig. 4.3(l)]
During this mode, resonance occurs among the components Lr, Llk and Cr2. At t11,
the snubber diode Da starts conducting, and Cr2 begins to resonant with both Lr and Llk. vCr2
becomes negative and the diode DR2 is blocked. The output inductor current iLf2 is supplied
by both isec and iSa2 as shown in Fig. 4.3(l). By neglecting the effect of ∆V during this
resonant period,
)(sin])()([)( 1155211sec1122 ttZitititv rrLfSaCr (4.28)
)](cos1][)()([)()( 115211sec11221122 ttititiLLm
Ltiti rLfSa
lkr
lkSaSa
(4.29)
)](cos1][)()([)()( 115211sec1122
2
11secsec ttititiLLm
Lmtiti rLfSa
lkr
r
(4.30)
It implies that the primary-side current flowing through S2 is given by
Chapter 4-118
)](cos1][)()([)()(
)( 115211sec112211secsec
2 ttititiLLm
mL
m
ti
m
titi rLfSa
lkr
rS
(4.31)
Within one-half of the resonant cycle, isec increases from negative values to zero,
and then to positive values. iSa2 drops to zero and then goes to below zero as indicated in
Fig. 4.2(c). Therefore, S2 and Sa2 can be turned off with ZCS after their currents become
negative, respectively. It can be noted that during this period, the diode DR2 is blocked and
the energy in Cr2 is transferred to the load, contributing a duty cycle gain. The duration of
this sub-stage is given by
212111112 reqCLttt (4.32)
According to (4.26)-(4.27) and (4.31)-(4.32),
lk
s
r
C
lkr
r
lk
sLfS L
VTDm
mZ
VV
LLm
mL
L
VTD
m
iti
2
122
2
1)( 2
4
12
22122 (4.33)
(i)
Chapter 4-119
(ii)
(iii)
Fig. 4.3(l) Mode 9 (t11-t12).
Chapter 4-120
4.4. Steady-State Analysis
4.4.1. Steady-State Voltage Stress on Cb
The voltage across the dc-blocking capacitor Cb can be derived by calculating the
voltage-second values in one steady-state cycle between the mid-points of the two switch
pairs, that are, nodes ‘A’ and ‘B’ as indicated in Fig. 4.1. It can be obtained that
s
dlC
sp
Cs
sp
CsCCCCb T
tV
Tti
VC
Tti
VCVDVDVV 11
8
22
6
22
22112 )()(2
1
(4.34)
Detailed proof of (4.34) is given in the Appendix A.1. In practical design, the third
term is negligible compared to other ones because of a very small value of Cs and small
difference between ip(t6) and -ip(t8). Therefore, VCb is approximately equal to
s
dlCCCCCb T
tVVDVDVV 11
22112 2
1 (4.35)
According to (4.35),
221111
2 2
1CC
s
dlCCbC VDVD
T
tVVVV (4.36)
4.4.2. Voltage Conversion Ratio
The voltage-second balances written on the inductors Lf1 and Lf2 give
111 2
1DD
mVV
V
C
o
(4.37)
222 2
1DD
mVV
V
C
o
(4.38)
Chapter 4-121
where
111 1
11 1 1
22
lk Lflk rr C
Lf s s C s C
L iL CC V V VD
mi T mT V mT V V
(4.39)
21 2 22 2
22 2 22 2
4 12 eq C lk Lf eqs C dl
Lf s s C s lk Cr r C s
L V V L i m L D VmC V tD
i T T m V V T L V VL C V V T
(4.40)
Detailed proof of (4.37)-(4.40) is given in Appendix A.2 and A.3. It should be
noted that the above equations for ΔD1 are for heavy loading condition when the secondary
winding current isec can be assumed to be zero during t01 and t45. Under light load, with the
consideration of isec, the first term (i.e., t45/(2Ts)) of ΔD1 is approximately presented by
1 1
1 sec2r C
Lf s
C V V
m i i T
, where seci is the average current of isec during t45. The fourth term of ΔD1
is zero due to that isec itself is sufficient to supply the load current, implying that there is no
duty cycle loss during the turn on transition of S1.
According to (4.37)-(4.38), the conversion ratio is given by
2211
2211
2
1
DDDD
DDDD
mV
VM
in
o
(4.41)
Practically, the net effect values of ∆D1 and ∆D2 are negligible compared to D1 and
D2. Therefore, Eq. (4.41) can be simplified into
21
21
2
1
DD
DD
mV
VM
in
o
(4.42)
By substituting (4.1) into (4.42), the conversion ratio can be represented by
112
1D
k
k
mM
(4.43)
Chapter 4-122
4.4.3. Voltage Distribution across Switch Pairs
According to (4.37) and (4.38),
221111
221122
2
1
DDDDVDDV
DDDDVDDV
V
Vk
in
in
C
C
(4.44)
By neglecting ∆V, ∆D1 and ∆D2, the steady-state voltage distribution factor is given
by
1
2
2
1
D
D
V
Vk
C
C (4.45)
Therefore, the voltage across the switches in each switch pair can be adjusted by
varying D1, D2, and thus k, allowing for the choice of the optimal combination of switching
devices. It should be noted that the input to output voltage ratio is not necessary to be
constant. The duty cycles of D1 and D2 will be updated accordingly with the required
voltage conversion ratio.
During the startup, the voltage distribution can be assured by selecting the ratio
between the capacitance values of C1 and C2. The capacitors C1 and C2 are charged up
instantaneously at the beginning to the initial values defined as VC1 (0) and VC2 (0), which
are assumed to be inversely proportional to their capacitance values. It gives that
1
2
2
1
)0(
)0(
C
C
V
V
C
C (4.46)
The DSP controller provides a soft-start function that makes the effective duty cycle
increase slowly, and controls the two capacitor voltages (i.e., VC1 and VC2) in the designed
ratio.
Chapter 4-123
4.5. Design Guidelines
The design guidelines for the proposed converter are illustrated by an experimental
prototype. The specifications are tabulated in Table 4.2. The discussions here focus on
the determination of the turns-ratio of the transformer, leakage inductance (or external
inductance if necessary) Llk, the voltages difference ∆V, and the snubber passive
components Cr1, Cr2 and Lr. For selection of other components selection, the design
guidelines are similar with conventional cases (e.g., the converter discussed in Chapter 3)
and will not be presented here.
Table 4.2 Design specifications of the experimental prototype.
Specifications Value
Nominal input voltage (Vin) 1500 V
Minimum input voltage (Vin,min) 1350 V
Maximum input voltage (Vin,max) 1650 V
Nominal output power (Po) 2 kW
Nominal voltage distribution factor ( knom ) 2
Output voltage ripple <1 %
Nominal output voltage (Vo) 48 V
Output current ripple <10 %
Switching frequency ( fs ) 50 kHz
4.5.1. Design Issues
1) Issues on the turns-ratio of the isolation transformer and duty cycle ranges
According to (4.43), (4.45) and the specifications listed in Table 4.2, the duty cycle
ranges with respect to different turns-ratio of the isolation transformer are shown in Table
4.3. To allow the proper operation, the values of D1 and D2 should be within [0, 0.5] and
Chapter 4-124
[0, 1], respectively. m = 4 is selected to retain reasonable margins of the D1 and D2.
Moreover, compared to the cases when m is less than 4 (e.g., m = 2, m = 3), it will reduce
the primary-side currents to achieve lower conduction losses of the switching devices.
Table 4.3 Ranges of duty cycles with respect to m.
m 2 3 4 5
D1,min 0.175 0.262 0.349 0.436
D1,nom 0.192 0.288 0.384 0.480
D1,max 0.213 0.320 0.427 0.533
D2,min 0.349 0.524 0.698 0.873
D2,nom 0.384 0.576 0.768 0.960
D2,max 0.427 0.640 0.854 1.067*
*An invalid state.
2) Issues on the soft-switching conditions
(a) ZCS condition of S1
According to (4.11), to ensure that iS1 drops to zero before t4,
2min,1
21
1VV
iLC
C
Lflkr (4.47)
where VC1,min is the minimum voltage stress on C1.
(b) ZCS condition of Sa1
After S1 turns off at t4, the energy stored in Cr1 is released to load until the current in
Cr1 decays to zero, therefore, iSa1 becomes zero and then Sa1 can be turned off with ZCS
without special constraints on the snubber parameters.
Chapter 4-125
(c) ZCS condition of S2 and Sa2
According to (4.26)-(4.27), (4.29) and (4.31), to ensure that iS2 and iSa2 drop to zero
before t12, the capacitance value of Cr2 should fulfill the inequalities
2
2,min
2 22
1,min
1
4
r s
r
lk r C
L D VTC
L m L V V
(4.48)
2r lkL L m (4.49)
(d) ZVS condition of S3
As discussed in Section 4.3, the voltage difference ∆V is used to charge the leakage
inductance Llk of the transformer during the freewheeling stage t5-6 and then the energy
stored in Llk provides the ZVS condition for turning on S3 within the interval [t6, t7].
According to (4.18), the following condition should be adopted to ensure that the voltage
across CS3 drops to zero before S3 turns on.
2,max
1 max 1
2
1 2C lk s
, s dr
V L CV
D T t
(4.50)
where VC2,max is the maximum voltage stress on C2. According to (4.50), provided that
there is a slight difference in the voltages between VC2 and VCb, S3 will be in ZVS.
Practically, the variations of the midpoint voltage between C1 and C2 only affect the
duration of the switching transition of S3.
(e) ZVS condition of S4
It is practically easy for S4 to achieve ZVS as the converter is still operating in
energy transfer stage before S4 is turned on.
Chapter 4-126
The secondary-side active snubber provides ZCS condition for the IGBTs. Without
it, all IGBTs could be switched with ZVS, but not a favorable operation. Moreover, S3
might also be hard-switched at turn on.
3) Issues on the current limits of switching devices
(a) Current limit of S1
The maximum current stress of S1, iS1,max, occurs within t1-2. It should not exceed
the pre-selected maximum current rating of the switching device S1, defined as IS1,max.
According to (4.6), it is given by
1 1,max1,max 1,max
1 2( )Lf C
S S
lk r r
i V Vi I
m m L C C
(4.51)
(b) Current limit of the primary-side winding during the freewheeling stage t5-6
During the freewheeling stage t5-6, the current in the primary-side winding flows
through S2 and S4 and its magnitude should be less than the pre-selected maximum current
ratings of these devices. According to (4.17), the condition is given by
1,min
6 max 1,min 1 2,max 4,max
1( ) 1 min ,
2 2ss
p dr S Slk lk
D VTTVi t D t I I
L L
(4.52)
where IS2,max and IS4,max are the pre-selected maximum current ratings of S2 and S4,
respectively.
(c) Current limit of Sa2
The maximum current flowing in Sa2 occurs at t11 and from (4.26), one gets
Chapter 4-127
1,max
2,max 2,max
2
2 C
Sa Sa
r r
V Vi I
m L C
(4.53)
where ISa2,max is the pre-selected maximum current rating of Sa2 and VC1,max is the maximum
voltage stress on C1.
4) Issues on the conduction time of Sa1 and Sa2 and resonant time of t1-2
The conduction time of Sa1 is t3-5 and that of Sa2 is t10-12. To ensure proper operation
of the switching devices, the minimum conduction durations should be larger than
reasonable values (e.g., larger than five times of the total turn on/off time of Sa1 and Sa2,
respectively). Therefore, according to (4.13)-(4.14), (4.25) and (4.32), the conditions are
given by
11
1
min,111 5)(
2 fr
fL
Crrlk ttmi
VVC
m
CL
(4.54)
2222 5
2 frreqrr ttCL
CL
(4.55)
where tr1 and tf1 are the turn on and turn off time of Sa1, respectively. tr2 and tf2 are the turn
on and turn off time of Sa2, respectively.
The time duration of t1-2 is given by (4.7), which will affect the conduction loss of
S1. The longer t1-2 is, the larger conduction losses are induced. Therefore, t1-2 is designed
to be less than 25% of the conduction time of S1. It gives that
2
%25)(
min,121 srrlk T
Dm
CCL
(4.56)
Chapter 4-128
4.5.2. Boundaries of the Design Parameters
1) Boundaries of Llk and Lr
According to (4.53),
2 22,max
2 2
1,max4
Sa rr
C
m I LC
V V (4.57)
According to the definition of Leq in Table 4.1 and (4.49),
2r eq rL L L (4.58)
By substituting the maximum values of Cr2 and Leq represented by (4.57) and (4.58),
respectively, into (4.55), one gets
1,max 2 2 2 2 1,max
2,max 2,max
20 20
3 3C r f r f C
rSa Sa
V V t t t t VL
mI mI (4.59)
According to (4.47),
1
2
1 2 1,min 2min
1,min
Lflkr r r
C
L iC C C
V V(4.60)
By substituting the minimum value of Cr1 + Cr2 represented by (4.60) into (4.56),
1,min 1,min 1,min 1,min
1 18 8C s C s
lkLf Lf
m V V D T mV D TL
i i(4.61)
Therefore, according to (4.49), (4.59) and (4.61), the boundaries of Lr and Llk are
given by
2 2 1,max 1,min 1,min
2,max 1
20
3 8r f C C s
lkSa Lf
m t t V mV D TL
I i (4.62)
2 2 1,max
22,max
20
3r f C lk
rSa
t t V LLmI m
(4.63)
Chapter 4-129
2) Boundary of V
According to (4.52),
2,max 4,max
1,min
2 min ,
1lk S S
s
L I IV
D T(4.64)
By considering (4.50) and (4.64) together,
2,max 4,max2,max
1,max 1 1,min
2 min ,2
1 2 1lk S SC lk s
s dr s
L I IV L CV
D T t D T (4.65)
3) Boundary of Cr2
According to (4.48) and (4.57),
22 2
2,min 2,max22 2
21,max1,min
1
44
r s Sa rr
Clk r C
L D VT m I LC
V VL m L V V (4.66)
4) Boundary of Cr1
According to (4.51),
2
1,max 1
1 22
1,max
lk S Lfr r
C
L mI iC C
V V(4.67)
Taking into account (4.47),
1
2 221,max 1 1,max 1
1 22 2 2
1,min 1,max 1,max
Lflk lk S Lf lk S Lfr r
C C C
L i L mI i L mI iC C
V V V V V V(4.68)
Chapter 4-130
4.5.3. Optimal Design
1) Minimization of the circulating current during freewheeling stage t5-6
According to (4.52), the circulating current in the freewheeling stage t5-6 will jump
up with the increase of ΔV under specific Llk. Moreover, by referring to (4.53) and (4.66), it
can be observed that small value of ΔV is beneficial to reduce the lower boundary of Cr2,
therefore, allowing reduction of the current stress of Sa2. ΔV is designed with its minimum
value represented by (4.65). Therefore,
2,max
min
1,max 1
2
1 2C lk s
s dr
V L CV V
D T t
(4.69)
According to (4.36) and (4.45),
s
dlC
T
tVV 11 (4.70)
It reveals that the desired value of ∆V presented by (4.69) can be achieved by
selecting a proper dead-time tdl1 and is irrelevant with loading condition.
2) Trade-off between ΔD1 and the current stress of S1
Based on (4.39) and (4.51), Fig. 4.4 graphically presents the values of ΔD1 and
current stress of S1 with different Llk and Cr1. Each pair of values of Llk and Cr1 within the
boundaries presented by (4.62) and (4.68) are reiterated by (4.54) and (4.56) and only the
ones meet the conditions are shown in Fig. 4.4. It should be noted that the value of Cr2 is
neglected for the sake of simplification during the checking process. Moreover, the values
of the current stress shown in Fig. 4.4(b) are approximated ones with Cr2 = 0. This
approximation will not affect the design of Llk and Cr1 as Cr2 is much smaller than Cr1 and
Chapter 4-131
the selection of Cr2 is independent of Cr1 as shown later.
It can be observed that large values of Llk and Cr1 are beneficial to achieve the duty
cycle gain and increase its value. However, high value of Cr1 will induce large current
stress of S1, leading to increasing conduction losses.
(a) ΔD1versus Llk and Cr1
Chapter 4-132
(b) Approximated current stress of S1versus Llk and Cr1
Fig. 4.4 Graphically trade-off conditions for designing of Llk and Cr1 (m = 4, VC1,min = 900 V,
VC1 = 1000 V, VC1,max = 1100 V, iLf1 = 27.8 A, IS1,max = 20 A, Ts = 20 µS).
3) Trade-off between ΔD2 and the current stress of S2
According to (4.40) and (4.53), Fig. 4.5 plots the surfaces of ΔD2 and the current
stress of Sa2 with varying values of Lr and Cr2. Each pair of values of Lr and Cr2 within the
boundaries presented by (4.63) and (4.66) should meet the condition in (4.55). It can be
noted that higher value of Lr is beneficial to increase the value of ΔD2 and reduce the
current stress of Sa2. Large value of Cr2 is also preferable to obtain more duty cycle gain,
however, will induce high current stress on Sa2.
Chapter 4-133
(a) ΔD2 versus Lr and Cr2
(b) Current stress of Sa2 versus Lr and Cr2
Fig. 4.5 Graphically trade-off conditions for designing of Lr and Cr2 (m = 4, VC1,min = 900 V,
VC1 = 1000 V, VC1,max = 1100 V, Llk = 36 µH, iLf2 = 13.9 A, ISa2,max = 48 A, Ts =20 µS, tdl2 =
0.278 µS).
Chapter 4-134
4.6. Prototype and Experimental Verifications
A 1500 V to 48 V 2 kW prototype is built to verify the proposed dc-dc conversion
concept. The specifications are as shown in Table 4.2. The design flow chart of ΔV, Llk,
Lr, Cr1 and Cr2 based on the design guideline in Section 4.5 is presented in Fig. 4.6.
According to Table 4.3, the turns ratio of the isolation transformer is selected as m = 4 and
the duty cycle D1, D2 are within [0.349, 0.427] and [0.698, 0.854], respectively. Fig. 4.4
and Fig. 4.5 are plotted with the pre-selected switching devices which have the following
parameters: IS1,max = 20 A, ISa2,max = 48 A, tr1 = tr2 = 22 ns and tf1 = tf2 = 29 ns. To
compromise ΔD1 and current stress of S1, maximum allowable Llk is chosen and minimum
value of Cr1 is selected. With the design specifications, Llk = 36 µH and Cr1 = 34 nF. Lr is
selected with the allowable maximum value and trade-off considerations should be made
for the selection of Cr2. According to (4.66) and Fig. 4.5, Lr is limited within 1.93 µH.
Therefore, Lr is selected with 1.6 µH to maintain a reasonable difference from that of Llk /m2
and to retain margin for tolerance considerations of practical inductors. Cr2 is chosen to
be 10 nF. Accordingly, the selected component parameters of the converter are presented
in Table 4.4. Llk is designed to be 36 H. It is realized by connecting an external inductor
with inductance of 25 H in series with the 11 H leakage inductance of the transformer.
Film capacitors instead of electrolytic capacitors are used for the dc-link due to
their high voltage blocking capability. The dc-blocking capacitor Cb is also implemented
by film capacitor with low equivalent series resistance (ESR) to sustain high current and
reduce its power losses. Fig. 4.7 shows the photo of the prototype (without showing the
DSP control board).
Chapter 4-135
Fig. 4.6 Design flow chart for ΔV, Llk, Lr, Cr1 and Cr2.
Chapter 4-136
Table 4.4 Component selections of the prototype.
Items Component Selections
Transformer
Turns ratio m 4:1
Magnetizing inductance 9.5 mH
Transformer leakage inductance 11 H
Inductance Llk 36 HTransformer leakage inductance 11 H
Externally added inductor 25 H
dc-link capacitors C1 1100 V/30 µF (2pc film cap.)
dc-link capacitors C2 800V/60 µF (2pc film cap.)
dc-blocking capacitor Cb 600 V/10 µF /ESR 5.3 mΩ (film cap.)
Output capacitor Co 100 V/2200 µF / ESR 90 mΩ (electrolytic cap.)
Output inductors, Lf1 and Lf2 120 H
Primary-side IGBT S1 and S2 IHW20N120R3 (1200 V/20 A)
Snubber IGBT Sa1 and Sa2 IRGS4062DPBF (600 V/24 A)
MOSFETs S3 and S4 SPW20N60C3 (650 V/20.7 A)
Rectifier diode D1 and D2 FFH30S60S (600 V/30 A)
Snubber diode Da STTH10LCD06SB (600 V/10 A)
Snubber capacitor Cr1 34 nF (film cap.)
Snubber capacitor Cr2 10 nF (film cap.)
Snubber inductor Lr 1.6 H
Chapter 4-137
Fig. 4.7 Photo of the 2 kW 1500 V-to-48 V prototype.
Fig. 4.8 describes the driving signals for the primary-side switches. It can be
observed that different duty cycles are applied to the two switch pairs to achieve the
asymmetric voltage distribution on them. The gate signals for S1 and S3 have a phase
difference of around 180°.
Fig. 4.9 presents the switching waveforms of the proposed converter under full load
and 10% loads. It can be observed that the IGBT switches S1 and S2 are turned on/off with
ZCS and the MOSFET switches S3 and S4 are switched by ZVS. Soft-switching can be
achieved from very light load to nominal load. Moreover, the voltage stresses on S3 and S4
are around 500 V as shown in Fig. 4.9(b), implying that it achieves an asymmetric voltage
distribution with k = 2, which is in well agreement with the theoretical predictions. The
ZCS waveforms for the auxiliary switches Sa1 and Sa2 are presented in Fig. 4.9(e).
Chapter 4-138
Fig. 4.8 Asymmetric driving signals for the two switch pairs.
(a) ZCS turn on/off of S1 and S2 under full load.
Chapter 4-139
(b) ZVS turn on/off of S3 and S4 under full load.
(c) ZCS turn on/off of S1 and S2 under 10% load.
Chapter 4-140
(d) ZVS turn on/off of S3 and S4 under 10% load.
(e) ZCS turn on/off of Sa1 and Sa2 under full load.
Fig. 4.9 Switching waveforms of S1-S4 and Sa1-Sa2.
Chapter 4-141
Fig. 4.10 shows the voltage waveforms across the input capacitors C1 and C2 at start
up. The voltage distribution ratio is found to be 1.998, which is in consistent with (4.45)
and (4.46).
Fig. 4.11 shows the relationship of open loop voltage and output current with fixed
duty cycle and input voltage. The output voltage increases with the reduction of load
current due to increased effective duty cycles. As the practical voltage drops on diodes,
active switches and parasitic resistors have not been considered in the theoretical
calculations, the calculated output voltages are observed to have some discrepancies with
the simulation and experimental ones.
Fig. 4.12 presents the measured efficiencies of the prototype. It reveals that the
proposed converter exhibits high efficiency within wide load ranges. The efficiency under
nominal load is 92.4%. The power losses in main components are analyzed in Fig. 4.13.
The key loss is on the rectifier diodes. With the aid of soft-switching, the power dissipated
on the two switch pairs is only 0.72% of the input power. The efficiency without the ZCS
snubber is also presented in Fig. 4.12, indicating an efficiency reduction of 1.7% under
nominal load mainly due to the turn off losses of IGBTs S1 and S2. The efficiencies with
open loop voltage varying from 48 V to 52.1 V (corresponding to Fig. 4.11) under different
loading condition are shown in Fig. 4.12. The power losses are mainly composed of two
parts. The first part is almost constant, such as the core losses of isolation transformer and
output inductors, power supplies for gate drivers and control circuits, and part of the power
losses in the ZCS snubber. The second part is increased with the output power. The
efficiency drops at light load due to that the first part power losses will become dominant.
Chapter 4-142
Fig. 4.10 Voltage across C1 and C2 during start-up.
Fig. 4.11 Open loop voltage and current characteristics with fixed duty cycles and input
voltage.
47
48
49
50
51
52
53
54
55
0 5 10 15 20 25 30 35 40 45
Out
put V
olta
ge V
o(V
)
Output Current (A)
simulatedcalculatedmeasured
Chapter 4-143
Fig. 4.12 Measured efficiencies under different loading condition.
Fig. 4.13 Power losses in main components under nominal load.
75
77
79
81
83
85
87
89
91
93
95
100 500 900 1300 1700 2100
Eff
icie
ncy
(%)
Output power (W)
With ZCS SnubberWithout ZCS SnubberOpen loop with constant duty cycle
Chapter 4-144
Compared to the prototype in Chapter 3 with same specifications, the proposed one
achieves 16.2% volume reduction and 1.6% and 8.2% efficiency improvement under full
load and 50% load, respectively.
4.7. Chapter Summary
A novel concept of dc-dc conversion with asymmetric voltage distribution across
switch pairs is proposed and applied for a particular kind of high input voltage application.
It allows using optimal choices of switching devices to achieve high frequency and high
efficiency operations. A hybrid ZVS-ZCS soft-switching technique is developed to make
the switching losses of MOSFETs and IGBTs negligible. The asymmetric operations of the
MOSFET switch pair and IGBT switch pair induce a voltage difference between dc-link
capacitor C2 and dc-blocking capacitor Cb. This voltage difference is independent of
loading condition and is the energy source for achieving ZVS of the lagging switch in the
MOSFET switch pair. The proposed snubber for ZCS of the IGBT switch pair completely
releases the snubber energy to the load, resulting in a duty cycle gain. The two switch
pairs can be soft-switched from very light load to full load with minimum circulating
energy. The control stage is implemented with a single digital controller without additional
hardware circuitry as compared to its counterpart in FB or TL converters. The switches of
the snubber commutate with ZCS. The concept is verified by a 1500/48 V 2 kW prototype.
Experimental results are in good agreement with the theoretical analysis. A voltage
distribution factor of 2 is achieved and the measured efficiency at nominal load is 92.4%.
Chapter 5-145
CHAPTER 5
A UNIFORM FAST TRANSIENT CONTROLLER FOR DC-DC CONVERTERS
5. 1 Introduction
The output of the high input voltage converters discussed in Chapter 3 and Chapter
4 are usually used to supply energy for various kinds of low-voltage converters. The
performance of the dynamic response of those low-voltage converters is critical as they are
momentary loads in the metro train applications. This chapter presents a uniform fast
transient controller for those low-voltage converters based on the second-order switching
surface control method developed in [117].
Much effort has been made to the switching surface control of buck converter.
However, it remains a fundamental challenge to apply the same concept and associated
control technique to converters with non-minimum-phase characteristics. A nonlinear
control method for all basic dc-dc converters (i.e. buck converter, boost converter, buck-
boost converter, uk converter and SEPIC) is proposed by deriving a uniform switching
surface. It retains the advantages of boundary control for buck converter with second-
order switching surface. For example, the converters can reach steady-state in two
switching actions after being subjected to large-signal disturbances. The derivations are
general-oriented and can determine the circuit variables needed in the switching function.
The same controller is universally applicable to different converters operating in both
continuous conduction mode (CCM) and discontinuous conduction mode (DCM).
A 190 W 48/48 V (i.e., unregulated input voltage with nominal value of 48 V to a
regulated output voltage of 48 V with different polarity) buck-boost converter prototype has
been built and evaluated to confirm the theoretical predictions.
Chapter 5-146
5. 2 Uniform Second-Order Switching Surface
5.2.1. Derivation of Uniform Second-Order Switching Surface
Fig. 5.1 shows the basic dc-dc converters. The first three ones, as presented in Fig.
5.1(a)-(c), are composed of one capacitor and one inductor. The last two, Ćuk converter
and single-ended primary-inductor converter (SEPIC), include two inductors and two
capacitors. Fig. 5.2 plots the theoretical waveforms of their inductor currents and capacitor
voltages. Generally, there are two types of distinctive curves to present the relationship
between inductor currents and capacitor voltages as shown in Fig. 5.2(a) and Fig. 5.2(b). It
can be noted from Fig. 5.2(b) that the capacitor voltages are monotonically decrease with
the corresponding inductor currents for converters with non-minimum phase characteristics,
imposing the challenge to apply switching surface control to those converters.
(a) Buck converter.
(b) Boost converter.
Chapter 5-147
(c) Buck-boost converter.
(d) Ćuk converter.
(e) Single-ended primary-inductor converter (SEPIC).
Fig. 5.1 Basic dc-dc converters.
Chapter 5-148
Fig. 5.2 Theoretical relationships between inductor current and capacitor voltage:
(a) iL-vC in buck converter and iL2-vC2 in uk converter; (b) iL-vC in boost and buck-
boost converter, iL1-vC1 in uk converter and iL1-vC1, iL2-vC2 in SEPIC.
To handle the above fundamental issue in switching surface control and incorporate
the advantages of the boundary control with second-order switching surface which has been
applied on buck converter [117], a uniform second-order switching surface is proposed. It
extends the control state variables (i.e. inductor currents and capacitor voltages) in
previously proposed switching surface controllers to arbitrary direct or indirect control
variables, namely x and y. Consequently, the relationships between x and y in all basic dc-
dc converters are exactly the same as that of iL-vC in buck converter shown in Fig. 5.2(a).
Therefore, the switching surfaces of different kind of converters can be easily defined on a
Cartesian x-y plane. x and y have the same properties as those of inductor current and
capacitor voltage respectively in buck converter, implying that
)(2 refs xxkdx
dy (5.1)
where ks is state trajectory parameter related with the slope of x and xref is the reference
value.
Chapter 5-149
Fig. 5.3 Principle of boundary control with uniform second order switching surface:
(a) control variables, (b) control law.
With the aid of Fig. 5.3, according to (5.1), the approximated on-state trajectory
Traj on and off-state CCM trajectory offTraj can be expressed respectively as follows
2 2
0 1 0Traj ( ) ( ) ( ) ( ) 0on s ref refy t y t k x t x x t x (5.2)
2 2
2 2 2Traj ( ) ( ) ( ) ( ) 0off s ref refy t y t k x t x x t x (5.3)
where t0 and t2 are the turn on/off instants, respectively, ks1 is the trajectory parameter
during on-state period and ks2 is that during off-state CCM period. ks1 > 0 and ks2 < 0. In
DCM, after the x reaches zero, the trajectory moves along the y-axis, x = 0 and the
corresponding trajectory parameter ks3 = 0 during this interval.
Fig. 5.4 presents typical switching surface, load line and ideal on/off state-
trajectories of basic dc-dc converters on x-y plane. The trajectories are plotted by firstly
Chapter 5-150
solving on- and off-state space equations of specific converter with different initial
conditions and then mapping the state variables iL and vC to x and y, respectively. It is the
ideal state trajectories which can be approximated by (5.2) and (5.3).
Fig. 5.4 Typical trajectories, load line and switching surface of basic dc-dc converters on
the x-y plane.
As discussed in [117], the ideal second-order switching surface 2 should pass
through the target operating point (yref, xref), and exactly along the approximated on-state
trajectory when x is below the load line, and the off-state trajectory when x is above the
load line. By transforming the iL-vC state plane to the Cartesian x-y plane, a well-defined
uniform second-order switching surface 2 can be obtained as shown in Fig. 5.4. It
approximately follows the ideal on-state trajectory and off-state trajectory when the state is
below and above the load line, respectively, implying a high velocity to revert to the target
Chapter 5-151
operating point from arbitrary operating points.
The switching instants are determined by predicting the operating point at t1 and t3
as shown in Fig. 5.3. By putting y(t) = yref, x(t) = xref, y(t0) = y, and y(t2) = y into (5.2) and
(5.3), respectively, a general form of the switching surface is given by
2 2( ) ( )ref refy y k x x (5.4)
where σ2 is the uniform second-order switching surface, k is the control parameter and can
be expressed as follows for an ideal second-order switching surface
2
)(sgn1
2
)(sgn121
refs
refs
xxk
xxkk (5.5)
k can be of other values, which affect the stability and trajectory velocity along the
switching surface as discussed in Section 5.3. In the following analysis, k1 and k2 are
defined as general control parameters for turn-on and turn-off switching actions,
respectively. Practically, in order to avoid chattering phenomenon, a modified switching
surface 2 is derived by adding a hysteresis band 2 y as shown in Fig. 5.4 into (5.4),
resulting in
)()(
)()(
22
2
21
2
2
refrefref
refrefref
xxyxxkyy
xxyxxkyy
＝ (5.6)
where 2 and 2
are the uniform second-order switching surface below and above load
line.
Therefore, the uniform control law for the basic dc-dc converters is formulated as
follows. The switch S is turned on if
Chapter 5-152
refrefref xtxyyxxkty )(and0)()()( 21 (5.7a)
S is turned off if
refrefref xtxyyxxkty )(and0)()()( 22 (5.7b)
Table 5.1 Load line and control variables of the proposed uniform control law.
Converter type Load line x y
Buck oL
vi
R iL vo
Boost o o
Lin
v ii
v iL 2 21 1
2 2L oLi Cv
Buck-boost o o
L oin
v ii i
v iL 2 21 1
2 2L o in oLi Cv Cv v
Ćuk 2o
L
vi
R iL2 vo
SEPIC 1 2o o
L L oin
v ii i i
v iL1+iL2
2 21 2 2 2
1( ) 2
2 L L o in oL i i C v C v v
Table 5.2 Control parameters of the proposed uniform control law.
Converter type kS1 (on-state) kS2 (off-state
CCM) kS2 (off-state
DCM)
Buck 2 ( )in o
L
C v v
2 o
L
Cv 0
Boost 2
L
2( )in
in o
Lv
v v 0
Buck-boost 2
L
2in
o
Lv
v 0
Ćuk 2
2 12 ( )C o
L
C v v 2
22 o
L
C v 0
SEPIC 2
L
2in
o
Lv
v 0
Chapter 5-153
Table 5.1 and Table 5.2 tabulate the transformed variables x, y and their associated
load line and control parameters ks1 and ks2 for ideal second-order switching surfaces. An
example demonstrating the derivation procedures of x, y, and k for a buck-boost converter
will be given in Section 5.3. It should be noted that the derivations for uk converter and
SEPIC are based on reduced-order models discussed in [108]-[110]. In uk converter, the
output inductor current iL2 and output capacitor voltage vC2 are selected as the state
variables. In SEPIC, the inductor currents iL1, iL2 and output capacitor voltage vC2 are
chosen as the state variables. The results for SEPIC presented in Table 5.1 and Table 5.2
are based on assumptions that the voltage across the dc-blocking capacitor C1 is equal to
vin, and the converter is designed with L1 = L2 = L.
Simulations have been done on boost converter, buck-boost converter, uk
converter and SEPIC to verify the analysis shown Table 5.1 and Table 5.2. Load changes
from CCM to CCM, from CCM to DCM and from DCM to CCM are simulated. The
results presented in Fig. 5.5 reveal that the single controller (with different control
parameters) can control the four converters operating in both CCM and DCM. The
converters can revert to steady-state by two switch actions after being exposed to large
disturbances. It can also be noted from Fig. 5.5(e)-(f) that x and y exhibit similar
properties during steady-state and transient periods as those of iL and vC in buck converter
discussed in [117].
Chapter 5-154
(a) Boost converter with load change from 12 Ω to 50 Ω (CCM to CCM)
(vin = 24 V, vo,ref = 48 V, L = 0.2 mH, C = 110 uF).
(b) Buck-boost converter with load change from 12 Ω to 200 Ω (CCM to DCM)
(vin = 48 V, vo,ref = 48 V, L = 0.1 mH, C = 150 uF).
Chapter 5-155
(c) Ćuk converter with load change from 50 Ω to 12 Ω (CCM to CCM)
(vin = 48 V, vo,ref = 48 V, L1=1 mH, L2 = 0.45 mH, C1 = 220 uF, C2 = 110 uF).
(d) SEPIC converter with load change from 200 Ω to 12 Ω (DCM to CCM)
(vin = 48 V, vo,ref = 48 V, L1 = L2 = 0.3 mH, C1 = 4.7 uF, C2 = 220 uF).
Chapter 5-156
(e) SEPIC converter with load change from 50 Ω to 12 Ω (x-y waveforms)
(vin = 48 V, vo,ref = 48 V, L1 = L2 = 0.3 mH, C1 = 4.7 uF, C2 = 220 uF).
(f) SEPIC converter with load change from 12 Ω to 50 Ω (x-y waveforms)
(vin = 48 V, vo,ref = 48 V, L1 = L2 = 0.3 mH, C1 = 4.7 uF, C2 = 220 uF).
Fig. 5.5Simulation results of basic dc-dc converters with the proposed uniform controller.
Chapter 5-157
5.2.2. Stability Analysis
By varying the control parameters of k1 and k2, the points along 02 can be
divided based on the directions of on/off trajectories at the switching surface [106]. There
are three possible modes of the points: rejective mode, reflective mode and refractive mode.
In rejective mode, the trajectories on both sides of the switching surface depart away from
the switching surface, which will lead to unstable operation of the converter. In reflective
mode, the sate trajectories direct toward the switching surface on both side and will move
along the surface to the target operating point. In refractive mode, trajectories reach to the
switching surface on one side and away from the other side. The state will move around
the target operating point. Thus, based on the analysis in [106], the conditions leading to
rejective mode are given by
0,0or0
0,0or0
stateoff2
stateoff2
stateoff2
stateon2
stateon2
stateon2
(5.8)
and the ones for ensuring reflective operation are given by
0,0or0
0,0or0
stateoff2
stateoff2
stateoff2
stateon2
stateon2
stateon2
(5.9)
where ‘on-state’ and ‘off-state’ indicate the corresponding value when the initial state is on-
state and off-state, respectively. For example, stateon2 is the rate change of 2 (i.e.
2 ) when the initial state is on and stateoff2 is the rate change of 2 (i.e. 2 ) if the
initial state is off. According to (5.2), (5.3) and (5.6), if the initial state is on,
2
21stateon2 ))(2 refs xxkk (5.10a)
Chapter 5-158
2
11stateon2 ))(2 refs xxkk （－ (5.10b)
)())((2 21
stateon
2
stateon2
refon
refs xxdt
dxxxkk
dt
d
(5.10c)
If the initial state is off,
2
22stateoff2 ))(2 refs xxkk （ (5.11a)
2
12stateoff2 ))(2 refs xxkk （ (5.11b)
)())((2 12
stateoff
2
stateoff2
refoff
refs xxdt
dxxxkk
dt
d
(5.11c)
where 0on
dtdx , 0off
dtdx are the slopes of x during on- and off-state, respectively.
By substituting (5.10) and (5.11) into (5.8) and (5.9), the regions of the control
parameters for rejective mode and reflective mode are given by (5.12) and (5.13),
respectively.
1221 and ss kkkk (5.12)
2211 and ss kkkk (5.13)
The conditions for refractive mode are within the ones outside the conditions of
(5.12) and (5.13). However, global stability can only be assured if each successive
intersection with the switching surface brings the operation closer to the target operating
point as illustrated in Fig. 5.6. ‘A’ (xn, yn), ‘B’ (xn+1, yn+1) and ‘C’ (xn+2, yn+2) are three
subsequent intersections between the state trajectories and the switching surface, called
successor points. The condition for stable operation is given by
Chapter 5-159
2 nn SS (5.14)
where Sn is the distance between ‘A’ and the target point ‘O’ (xref, yref),
222 )() refnrefnn yyxxS （ and Sn+2 is the distance between ‘C’ and ‘O’,
22
22
22 )() refnrefnn yyxxS （ .
Fig. 5.6 Illustration of the movement of successor in refractive mode.
By neglecting the hysteresis band y2 , for a generic successor point on 02 ,
2)( refnrefn xxkyy (5.15)
Therefore the condition given in (5.14) can be rewritten as
222 )()( refnrefn xxxx (5.16)
Chapter 5-160
As shown in Fig. 5.6, the successor points ‘A’ and ‘C’ are on 2 and ‘B’ is on 2
－ .
Both of ‘A’ and ‘B’ are on the off-state trajectory while ‘B’ and ‘C’ are on the on-state
trajectory. According to (5.2)-(5.3), (5.6) and (5.15), it can be derived that
2 2 1 1 2 22
1 2 2 1
( ) ( ) s sn ref n ref
s s
k k k kx x x x
k k k k
(5.17)
In order to satisfy (5.16), it results in
21 kk (5.18)
Fig. 5.7 Stability analysis of the proposed uniform second-order switching surface with
different control parameters k1 and k2.
Fig. 5.7 summarizes the aforementioned analysis and presents k1 and k2 regions for
different operation modes. It can be observed that when k1 = ks1 and k2 = ks2, the switching
Chapter 5-161
surface is along the boundary of the reflective and refractive regions. Fig. 5.8 shows five
typical switching surfaces with specific values of k1 and k2. ‘A’ and ‘B’ are points on the
right and left sides of switching surfaces of 21 , 2
2 and 23 , and ‘A’ and ‘C’ locate on the two
sides of switching surfaces 24 and 2
5 . 2n (n = 1, 2, 3, 4, 5) and 2
n indicate turn off/on
part of one specific switching surface above and below the load line, respectively. It can
be noted that the curved switching surfaces 21 , 2
3 , 24 and 2
5 will make arbitrary point
operate in reflective, stable refractive, unstable refractive and rejective mode, respectively.
When 22 is selected, which approximately follows the on/off state trajectory, the arbitrary
point “A” or “B” will reach the target operating point by two switching actions.
Fig. 5.8 Illustration of rejective, refractive and reflective operation modes.
Chapter 5-162
5.3. Derivation and Implementation (for Buck-Boost Converter)
Fig. 5.9 Operation modes of buck-boost converter.
With the aid of Fig. 5.9, the derivation procedures for getting the results tabulated in
Table 5.1 and Table 5.2 are explained by a buck-boost converter as follows:
Step 1 - Derivation of the load line. The load line is derived by considering the
average steady-state inductor current iL,ref. For buck-boost converter,
oin
oorefL i
v
ivi , (5.19)
where vin is the input voltage, and vo and io are the output voltage and current, respectively.
Step 2 - Determination of x, y and ks1. For buck-boost converter, the control
variable x is firstly selected as the inductor current Li . As shown in Fig. 5.9(a), during on-
Chapter 5-163
state interval,
in
o
L
o
vCR
vL
id
vd (5.20)
where L and C are the inductor and output capacitor, respectively, and R is the equivalent
load resistance.
By using (5.1), it can be shown that
)2
1
2
1(
2)(2 221
,1 oinoLs
LrefLLs vvCvCiLL
kidiiky (5.21)
Hence, y can be chosen as
oinoL vvCvCiLy 22
2
1
2
1 (5.22)
21
Lks (5.23)
Step 3 - Determination of ks2. As shown in Fig. 5.9(b), during off-state interval,
)( ,refLLo
in
LL
iiv
vL
id
td
td
yd
id
yd (5.24)
o
ins v
Lvk
22 (5.25)
Step 4 - Calculation of yref . Based on (5.19) and (5.22),
refoinrefooin
ooref vvCvCi
v
ivLy ,
2,
2
2
1)(
2
1 (5.26)
Step 5 - Formation of the control law. According to (5.7), the switching criterion is
described as follows. The switch S is turned on if
Chapter 5-164
refLLrefrefLL itiyyiikty ,2
,1 )(and0)()()( (5.27a)
S is turned off if
refLLrefrefLL itiyyiikty ,2
,2 )(and0)()()( (5.27b)
An ideal second-order switching surface is that k1 = ks1 and k2 = ks2.
Step 6 - Implementation of control law. Based on the above derivations, the block
diagram of the controller for buck-boost converter is shown in Fig. 5.10.
Fig. 5.10 Block diagram of the proposed uniform controller for buck-boost converter.
Chapter 5-165
5.4. Steady-State Characteristics (for Buck-Boost Converter)
5.4.1. Switching Frequency
(a) CCM.
(b) DCM.
Fig. 5.11 Switching surface 2 and the steady-state trajectories of buck-boost converter.
Chapter 5-166
The effect of the equivalent series resistance (ESR) of the output capacitor is taken
into account for the analysis as it is critical to the switching frequency variation. Define
ESRov as the measured output and act
ov as the actual capacitor voltage. It can be shown that
ESR acto o C Cv v i R (5.28)
where iC is the capacitor current, iC = -io during the on-state period and iC = iL-io during the
off-state period. RC is the ESR of output capacitor. Therefore, the measured yESR and
ESRrefy including ESR effect are given by
2 21 1( ) ( )
2 2ESR act act
L o C C in o C Cy Li C v i R C v v i R (5.29)
2 2, , ,
1 1( ) ( )
2 2ESR act actref L ref o ref C C in o ref C Cy Li C v i R C v v i R (5.30)
Fig. 5.11 presents the 2 and the steady-state trajectory of buck-boost converter
operated in CCM and DCM. Points ‘A’ (y1, xmax) and ‘B’ (y2, xmin) are on the switching
surface of 2 and 2
as shown in Fig. 5.11(a) to illustrate the CCM case:
0)( 2max21 yxxkyy refref (5.31a)
0)( 2min12 yxxkyy refref (5.31b)
At steady-state, the ripple currents xmax – xref and xref – xmin are of the same value.
As points ‘A’ and ‘B’ are both on the on and off state trajectories, y1 = y2. Substitute
ESRyy 11 , ESRyy 22 , (5.26), (5.29) and (5.30) into (5.31), resulting in
ESRref
ESRESR yykk
kkyy
21
2121 (5.32)
Chapter 5-167
2 21 2
min max1 2
( ) 4( ) ( ) 2 ( )
2( )
C in o C in o o in C in oR C v v k k R C v v i v y R C v vx x
k k
(5.33)
where minmin xxx ref and refxxx maxmax .
When RC = 0,
min_ 0 max_ 01 2
2C CR R
yx x
k k
(5.34)
For buck-boost converter, when S is on, Ltvi oninL , where ont is the on time.
When S is off, Ltvi offoL , where offt is the off time. Therefore, the switching frequency
fs_CCM of the buck-boost converter operated in CCM is
1 2
_2 2
1 2
( )
( ) ( ) 4( ) ( ) 2 ( )
o ins CCM
in o C in o C in o o in C in o
k k v vf
L v v R C v v k k R C v v i v y R C v v
(5.35)
By substituting RC = 0 into (5.35) to obtain the switching frequency excluding the
effect of ESR as follows:
_ _ 0
1 2
22 ( )
C
o ins CCM R
in o
v vf
yL v v
k k
(5.36)
When operated in DCM, x reaches to zero during the off-state period as indicated by
the points ‘B’ (y2, 0) and ‘C’ (y3, 0) shown in Fig. 5.11(b). In a similar way, it yields
2 2
1 2
max1 2
( ) 4( ) ( ) 2 ( )
2( )
C in o C in o o in C in o
ref
R C v v k k R C v v i v y R C v vx x
k k
(5.37)
Chapter 5-168
For buck-boost converter, the average inductor current is equal to xref, given by
oin
Loin
s
i
i Lo
LL
in
L
sLL vv
ivvL
Tdi
v
Lidi
v
Li
TiI
L
L 2
)(11 2max,
0
0max,
max,
(5.38)
According to (5.26), (5.37) and (5.38),
_ 2
2 21 2
1 2
2
( ) 4( ) ( ) 2 ( )
2( )
o os DCM
C in o C in o o in C in oin oo
in
v if
R C v v k k R C v v i v y R C v vv vL i
v k k
(5.39)
When RC = 0
_ _ 0 2
1 2
2
2C
o os DCM R
in oo
in
v if
v v yL i
v k k
(5.40)
Fig. 5.12 presents the switching frequency of buck-boost converter with the
proposed control scheme. In DCM, the switching frequency increases with load current
and reaches a constant value when the converter enters into the CCM if ideally RC = 0.
The switching frequency in DCM increases slightly with the ESR of the output capacitor,
while in CCM it drops with the increasing value of ESR. Therefore, an output capacitor
with low ESR is beneficial to reduce the variation of the switching frequency in CCM.
Chapter 5-169
Fig. 5.12 Steady-state switching frequency of buck-boost converter with the controller.
5.4.2. Output Voltage
For buck-boost converter, the minimum and maximum voltages occur when the
inductor current iL reach highest and lowest levels, respectively. According to Fig. 5.11,
min,2
max,,2
min,1 2
1
2
1oinLrefLo vvCiiLvCy (5.41a)
max,2
min,,2
max,2 2
1
2
1oinLrefLo vvCiiLvCy (5.41b)
Based on (5.32), (5.34) and (5.41),
10k
14k
18k
22k
26k
30k
34k
38k
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5
Sw
itch
ing
freq
uenc
y (H
z)
Output current (A)
0.00E+001.40E-036.00E-031.00E-022.00E-0230k
31k
32k
33k
34k
35k
0,17 0,22 0,27 0,32 0,37Output current (A)
Sw
itch
ing
freq
uenc
y (H
z)
RC increase
RC increase
DCM CCM
RC = 0
RC = 1.4 mΩ
RC = 6 mΩ
RC = 10mΩ
RC = 20 mΩ
Chapter 5-170
inrefLo viBAv ,max, (5.42)
inrefLo viBAv ,min, (5.43)
where ykk
Lkk
CvvA refoin
21
212,
2)( and
21
22
kk
y
C
LB
. Thus, the average output
voltage vo,av is given by
in
refLrefL
avo viBAiBA
v
2
,,
, (5.44)
011
4 ,,,
,
refLrefLrefL
avo
iBAiBA
B
id
vd (5.45)
It reveals from (5.45) that the steady-state output voltage will be slightly decreased
with the increase of load. Fig. 5.13 plots the average output voltage under different
loading condition when vin = 48 V, vo,ref = 48 V, ∆y = 2.4 mV, k1 = 1.8×10-4 and k2 = -
1.8×10 -4. It can be noted that the maximum variation of the average output voltage from
no load to rated load is 64 mV.
Chapter 5-171
Fig. 5.13 Average output voltage versus output current of buck-boost converter with
proposed uniform control law (vin = 48 V, vo,ref = 48 V, ∆y = 2.4 mV, k1 =1.8×10-4 and k2 = -
1.8×10-4).
5.5. Experimental Verifications
A 190 W, 48/48 V prototype of buck-boost converter is built with an inductor of
0.36 mH and output capacitor of 150 µF. For the sake of investigation, the proposed
control method is implemented according to Fig. 5.10 by a digital method. The prototype
is tested under six kinds of load change conditions: a) output resistance is from 47 Ω to12.3
Ω, and vice versa; b) the value of output resistor reduces from 100 Ω to 12.3 Ω, and vice
versa, and (c) a large load variation with output resistance from 500 Ω to 13.6 Ω, and vice
versa.
Fig. 5.14(a) and Fig. 5.15(a) present waveforms of the output voltage vo, output
current io, inductor current iL and switching signal VGS under a load change from 1.02 A to
47,930
47,940
47,950
47,960
47,970
47,980
47,990
48,000
48,010
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5
Ave
rage
out
put v
olta
ge (
V)
Output current (A)
Chapter 5-172
3.9 A and vice versus. The converter operates in CCM under both loading condition. It
can be observed from the gate signal VGS that the output voltage approaches to the steady-
state after two switching actions. The setting time is 230 μs and 242 μs for the transients
of load increase and load decrease, respectively.
Fig. 5.14(b) and Fig. 5.15(b) show the dynamic response of the converter when the
load is switched between the value for critical current conduction mode operation and
nominal value. The load currents are 0.48 A and 3.9 A, respectively. The inductor current
reaches zero at the end of each cycle. A fast dynamic response and well output voltage
regulation can be maintained.
Fig. 5.14(c) and Fig. 5.15(c) give the dynamic response when the operation mode of
the converter change from DCM to CCM or versus after large signal disturbance. The load
currents are switched between 0.096 A and 3.53 A. It can be observed that the converter
reaches steady-state by two switching actions for energy absorbing and releasing,
confirming that the same controller is suitable for both CCM and DCM operation. The
variations of the average output voltages are 45 mV, 60 mV and 70 mV respectively for the
three cases of load increase, as presented in Fig. 5.14 (a), (b) and (c).
Chapter 5-173
(a)
(b)
Chapter 5-174
(c)
Fig. 5.14 Waveforms of dynamic response under increased loading condition. (a) RL
from 47 Ω to 12.3 Ω, (b) RL from 100 Ω to 12.3 Ω, (c) RL from 500 Ω to 13.6 Ω. (vo: (ac)
500 mV/div, io: 2 A/div, iL: 5 A/div, vGS: 20 V/div and Timebase: 100 µs/div).
Chapter 5-175
(a)
(b)
Chapter 5-176
(c)
Fig. 5.15 Waveforms of dynamic response under reduced loading condition. (a) RL from
12.3 Ω to 47 Ω, (b) RL from 12.3 Ω to 100 Ω, (c) RL from 13.6 Ω to 500 Ω.(vo: (ac) 500
mV/div, io: 2 A/div, iL: 5 A/div, vGS: 20 V/div and Timebase: 200 µs/div).
Fig. 5.16 shows the output voltage, output current and driving signal when start-up.
The switch is always off to release the energy stored in the inductor to the load to increase
the output voltage level before reaching steady-state. The start-up time is measured with
2.15 ms.
Fig. 5.17 presents the measured switching frequency at Rc = 1.4 mΩ. With output
capacitor of low ESR, the switching frequency is found to vary 4.2 kHz when the converter
is operated from critical conduction mode to the rated load.
Chapter 5-177
Fig. 5.16 Waveforms of start-up period of buck-boost converter (vo: 50 V/div, io: 1 A/div,
vGS: 20 V/div and Timebase: 2 ms/div).
Fig. 5.17 Measured switching frequency of buck-boost converter.
20k
22k
24k
26k
28k
30k
32k
34k
36k
38k
0 0,5 1 1,5 2 2,5 3 3,5 4
Sw
itch
ing
freq
uenc
y (H
z)
Experimental resultsCalculation (Rc=0)
Calculation (Rc=1.4mΩ)
Output current (A)
Experimental results Calculation (R
C = 0)
Calculation (RC
= 1.4 mΩ)
Chapter 5-178
5.6. Chapter Summary
A uniform fast transient controller with second-order switching surface for basic dc-
dc converters is proposed. State variables such as capacitor voltage and inductor current
are transformed to Cartesian x-y plane to formulate a general form of switching criterion for
different types of dc-dc converters. The control parameters are obtained readily by
considering the component values of the power stage without any sophisticated
calculations. Stability analysis has been carried out by varying the control parameters in
different regions. Derivation steps, design approaches and steady-state analysis are
demonstrated with a buck-boost converter. A 48/48 V 190 W prototype has been built and
tested under both CCM and DCM conditions. It has been verified that the control method
addresses a complete operation and does not differentiate startup, transient, and steady-state
intervals. The results of the large-signal response are in good agreement with the
theoretical predictions.
Chapter 6-179
CHAPTER 6
A DC-LINK MODULE FOR REDUCING DC-LINK CAPACITANCE
6.1 Introduction
The aluminum electrolytic capacitors (E-Caps) consume considerable power and
induce reliability concern in one of the prototypes of the high input voltage converter
presented in Chapter 3. The observations motive that partial of the work is devoted to the
component level research of capacitors. It explores the possibilities to reduce the dc-link
capacitance in general capacitor-supported power electronic systems, which in turn has the
potential to be applied in the front-end ac-dc stage of high-voltage dc-dc converters.
Accordingly, a dc-link module consists of a dc-link capacitor and a voltage
compensator connected in series with the dc bus line is proposed. The compensator
processes the ripple voltage and reactive power only and thus can be implemented with
switches and capacitors of low voltage rating. The capacitance value used in the dc-link
module is significantly reduced from the original one. Therefore, it allows the use of
alternatives (e.g., power film capacitor) with long lifetime and low power loss to replace E-
Caps with comparable size and cost.
Simulation on several types of power electronic converters and prototype testing on
a power factor corrector (PFC) verify the feasibility of the proposed concept.
Chapter 6-180
6.2 Basic Concept of the Proposed DC-Link Module
A typical power conditioning system consists of multiple power converters
interconnected by a high-voltage dc-link. Fig. 6.1 shows an example with two converters.
The first converter is used to convert the input, either in the form of ac or dc, into dc. The
second converter is used to provide the required form of power to the load from the dc-link.
The dc-link voltage is supported by a capacitor bank, which is used to absorb the
instantaneous power difference between the input source and output load, minimize the
voltage variation on the dc-link, and in some applications provide sufficient energy during
the hold-up time of the whole system.
Fig. 6.1 Block diagram of a typical capacitor-supported power electronic conversion system.
Fig. 6.2 Basic concept of the proposed dc-link module.
Chapter 6-181
Fig. 6.2 illustrates the basic concept of the proposed dc-link module with reduced
dc-link capacitance. The dc-link capacitor is connected to the output of the front-end
power conversion stage. Typically, the previous stage is a bridge rectifier or PFC, which
generates a dc voltage and an ac ripple component. As shown in Fig. 6.2, the capacitor
voltage vC is composed of a dc component VC superimposed a voltage ripple of ΔvC with a
peak-to-peak value of 2 Cv . To decouple these two parts, a voltage compensator is
connected in series with the dc-bus to generate an ac voltage vab that closely follows the
ripple voltage ΔvC. Therefore, an ideal dc voltage VDC will appear at the two terminals of
the bus line. A much higher voltage ripple is allowed on the dc-link capacitor.
The value of dc-link capacitance depends on the designed maximum magnitude of
vab permitting the reduction of the value of the capacitor. The dc-link capacitor together
with the proposed voltage compensator forms a dc-link module that can be applied in
various capacitor-supported power electronic systems.
6.3 Steady-State DC and AC Analysis
A dc analysis of the circuit shown in Fig. 6.2 gives
d CV V (6.1)
d AI I (6.2)
where Vd and VC are the dc components of vd and vC, respectively, and Id and IA are the dc
component of id and iA, respectively.
An ac analysis of the circuit in steady-state operation is taken by assuming that
Chapter 6-182
1 1( ) sinA Ai t I t (6.3)
2 2( ) sind di t I t (6.4)
where Ai and di are the ac components of id and iA, respectively, AI and dI are the
amplitudes of Ai and di , respectively, and 1 and 2 are the frequencies of Ai and di ,
respectively.
Thus, the ac component of vC, (i.e., Cv ) and vab (i.e., abv ) can be expressed as
1 1 2 21 2
1( ) ( ) ( ) ( )
sin 90 sin 90
ab C A d
A d
v t v t i t i t dtC
I It t
C C
(6.5)
Based on (6.4)-(6.5), the average power Pab provided by the voltage compensator in
a period T is given by
0
1 2 1 201
1( ) ( )
sin2
T
ab ab d
Td A
P v t i t dtT
I It dt
CT
(6.6)
where T is the least common multiple of 1
2
and 2
2
. It can be noted that Pab = 0 except
for a special case when 1 2 and 1 2 . Therefore, the voltage compensator handles
reactive power only in all of other cases. For the special case mentioned, the dc-link
capacitance can be reduced by synchronization control of the phase 1 and 2 without the
proposed voltage compensator.
The apparent power of the voltage compensator is given by
Chapter 6-183
2
2 2 221
1 2
12
2ab A d d dS I I I IC
(6.7)
Therefore, when 1 2 or 1 2 1 2and , the reactive power processed by the
voltage compensator is equal to Sab, that is
2
2 2 221
1 2
1 2 1 2 1 2
12
2
( ,or and = )
ab A d d dQ I I I IC
(6.8)
The output terminal voltage (i.e.,vab) of the voltage compensator is only the voltage
ripple of the dc-link. Therefore, Sab presented by (6.7) is considerable small compared to
that of the specific main dc-link power conversion system. Especially, the apparent power
rating is reduced significantly compared to that of the solutions with parallel active circuits
discussed in Section 1.4.3.
6.4 Series-Connected Voltage Compensator
6.4.1 Implementation
Fig. 6.3 shows the implementation of vab and its control method. vab is an dc-ac
converter consisting of a full-bridge (FB) and an output filter formed by the inductor Lf and
capacitor Cf. Its dc side is connected to an energy storage device such as a capacitor or
voltage source. The gate signals for the switches S1-S4 in the FB are generated by a PWM
modulator. It should be noted that the power stage could be implemented by a half-bridge
for loads with unidirectional current flow. The voltage ripple on C is sampled by a scaling
factor of α. In order to avoid vab from generating dc voltage, the dc output of vab is
Chapter 6-184
extracted by a low-pass filter. The output of the low pass filter passes to a PI control block.
The output of the PI block, vos, is combined with the ripple voltage on C to compose the
modulating signal vm for the PWM modulator.
S1 DS1
S3 DS3
S2 DS2
S4 DS4
Lf Cfva
a b
vC vd
vab
ia
iC
id
C+
Ca+
LoadFront-end
stage
voltage sense and low pass filter
PI
voltage sense
DC offset
vm-+ -
CV
vos
PWM controller
driving signals
for S1-S4
vfd
+
=
con
C
v
v
Control Stage
Power Stage
Ma
Fig. 6. 3 Implementation of the voltage compensator.
6.4.2 Analysis of the Voltage Compensator
Figs. 6.4(a) and (b) present the operating modes of the voltage compensator. When
S2 and S3 are on, the capacitor Ca is charged by the load current id and when S1 and S4 are
on, the capacitor Ca is discharged. Fig. 6.4(c) shows the waveforms of the dc-link
Chapter 6-185
capacitor voltage vC, modulating signal vm, carrier signal vtri, and the voltage across Ca, va.
It should be noted that the control signal vcon may contain multiple frequency components
as it is obtained by scaling down ΔvC. According to (6.5), the amplitude modulation ratios
for different frequency components can be defined as
11
Aa
tri
Im
CV
(6.9)
22
da
tri
Im
CV
(6.10)
where is the scaling factor /con Cv v and Vtri is the amplitude of the tri-angular waveform
used for PWM.
Chapter 6-186
Lf
Cf
a
b
vab
id
iCf
iLf
Cava
Lf
Cf
a
b
vab
id
iCf
iLf
Cava
(a) (b)
t
t
t0 t2t1
va,min
va,max
2 av
vC,min
vC,max
2 Cv
t
VmVtri
(c)
Fig. 6. 4 Operation of the voltage compensator: (a) operating mode when S2 and S3 are on,
(b) operating mode when S1 and S4 are on and (c) SPWM and the voltage across Ca.
To study the charging and discharging processes of Ca, t0 and t1 in Fig. 6.4 (c) are
defined as the two time instants when ΔvC is across zero within one period. During t0-t1,
the capacitor Ca is being charged by the load current and its voltage increases from
minimum to maximum. Based on Fig. 6.4 and unipolar SPWM principle discussed in
[169], the voltage across Ca during t0-t1 is given by
Chapter 6-187
0
0
0
,min 2 2
1 1 1 2 2 2
1 1 1 2 2 2
1 1 1 2 2
,min
2 2 2
1( ) sin ( )
sin 90 sin 90
sin 90 sin 90
sin 90 sin1
sin cos
t
Ca Ca d d Cfta
a a
t
d a at
t
a d t
Caa
a d
v t v I I t i tC
m t m t dt
I m t m t dt
m I t t dtv
C m I t
0
0
2 2
1 1 1 2 2 2- ( ) sin 90 sin 90
t
t
t
Cf a at
t dt
i t m t m t dt
(6.11)
where vCa,min is the minimum voltage on Ca. During t0-t1, the net charge of the filter
capacitor Cf by iCf is zero, therefore, when 1 2 , the voltage ripple of Ca , 2 Cav , is
given by
1
01 1 1 2 2 2
1 21 1 1 1 0 1 2 1 2 2 0 2
1 2
12 sin 90 sin 90
sin sin sin sin
t
Ca d a ata
a d a d
a a
v I m t m t dtC
m I m It t t t
C C
(6.12)
For practical applications when 2 is much larger than 1 , the effect of the second
terms of (6.5) and (6.12) are negligible and 1 1 1sin 1t , 1 0 1sin 1t , therefore,
1
1
22 a d
Caa
m Iv
C (6.13)
The above equation is also applicable for the case when 2 is even multiples of 1 as
2 1 2 2 0 2sin sint t . The voltage across Ca is therefore presented by
11 1
1
sina dCa C a
a
m Iv t V t
C
(6.14)
The output voltage of the voltage compensator vab is obtained by
Chapter 6-188
11 1 1 1 1 2 2 2
1
21
1 1 1 2 2 2 1 11
sin sin 90 sin 90
sin 90 sin 90 sin 2 22
a dab C a a a
a
a dC a a a
a
m Iv t V t m t m t
C
m IV m t m t t
C
(6.15)
The first term of (6.15) is used to cancel the dc-link voltage ripple while the second term is
a double frequency ripple that generates voltage variation on vd.
6.5 Design of Capacitors for DC-Link and the Voltage Compensator
6.5.1 Design of the DC-Link Capacitor
The reduction of the dc-link capacitance is limited by the voltage stresses on the
input capacitor and switching devices of the voltage compensator. Fig. 6.5 plots the trade-
off design curve. Without the proposed voltage compensator, it requires a capacitance of
Cnorm meeting the design specification. Practically, the required one may be larger than
Cnorm to sustain ripple current stress. Moreover, the dc-link voltage ripple will increase
from ,2 C nomv to 2 Cv due to the aging process with a decay of the capacitance value.
With the proposed voltage compensator, the selection of the dc-link capacitance C
is independent of the required dc-link voltage ripple, but is compromised with the allowable
voltage stress on the capacitor Ca and MOSFETs S1-S4. A smaller value of C requires
higher voltage ratings of Ca and S1-S4. Moreover, a boundary capacitance Cbd can be
determined based on specifications of power electronic systems, availability, cost and
volume of different type of capacitors. It provides guideline on the selection of capacitor
type. For instance, power film capacitors are applied in Selection 1 with a higher level of
the dc component of vCa, VCa, compared to that of Selection 2 in which E-caps are used.
Chapter 6-189
With the aid of the proposed voltage compensator, the required dc-link capacitance can be
reduced, making it possible to achieve long lifetime power electronic systems (i.e., by using
power film capacitors) as well as maintaining high power density and comparable low cost.
Fig. 6.5 VCa-C curve for capacitance selection of the dc-link capacitor ( ,C nomv -half of the
design specification of the dc-link voltage ripple, Cnom-required dc-link capacitance without
the voltage compensator, nomC - dc-link capacitance after certain degree of aging, Cbd -
boundary of the selected type of dc-link capacitor according to specifications, availability,
cost and volume, Vbd- value of VCa corresponding to Cbd.
6.5.2 Design of the Input Capacitor of the Voltage Compensator
As illustrated in Fig. 6.2, the voltage compensator generates a voltage vab that
exactly follows the voltage ripple of the dc-link capacitor. However, in practical case, as
revealed by (6.15), there is an undesirable voltage ripple with doubled frequency in vab,
Chapter 6-190
leading to variations in the output voltage of the proposed dc-link module. Therefore, the
value of Ca is designed to suppress the voltage ripple across the output terminals of the dc-
link module within the specification of ,2 C nomv .
As the capacitor Ca withstands a low voltage stress, there are many choices for
practical implementation. One choice is to use low voltage E-caps with high ripple current
and long lifetime. Unlike the ones with high voltage ratings, they are available and cost-
effective. Another choice is to use ceramic capacitor tank or low voltage film capacitors.
6.6 Simulation and Experimental Verifications
6.6.1 Simulations
Various type of power conversion systems are simulated with and without the
proposed dc-link module. Table 6.1 tabulates the study cases. It covers both 400 V and
800 V dc-link systems with diode rectifier or PWM converter front-end stage and resistive
load, inductive load or switching load. Fig. 6.6 presents the simulation results accordingly.
It verifies the feasibility and applicability to apply the proposed dc-link module in various
power electronic systems.
Chapter 6-191
Table 6.1 Simulation cases
Front-end topology Descriptions
Case 1 Current sources (dc + ac) 2 kW 400 V dc-link, inductive load
Case 2 Three-phase uncontrolled rectifier 2 kW 800 V dc-link, resistive load.
Case 3 Boost PFC front-end 1 kW, 400 V dc-link, resistive load
Case 4 Single-phase full-bridge PWM
rectifier 2 kW 800 V dc-link, resistive load.
Case 5 Single-phase full-bridge PWM
rectifier 2 kW 800 V dc-link, inductive load.
Case 6 Boost PFC front-end 1 kW, 400 V dc-link, full-bridge
converter load
(a) Simulation results with current source front-end and 400 V dc-link (IA = 5 A, Ia = 1 A,
ZL: 80+j0.063 Ω, C: 450 V/ 40 µF, Ca: 50 V/1000 µF) (Case 1).
vCa (V)
Chapter 6-192
(b) Simulation on three-phase uncontrolled diode bridge rectifier with 800V dc-link voltage
(Po = 2 kW, load RL: 320 Ω, C: 900 V/ 40 µF, Ca: 100 V /220 µF) (Case 2).
(c) Simulation on boost PFC with controlled 400 V dc-link voltage (Po = 1 kW, RL: 160 Ω,
C: 450 V/ 100 µF, Ca: 50 V/1000 µF) (Case 3).
vCa (V)
vCa (V)
Chapter 6-193
(d) Simulation on PWM rectifier with 800 V dc-link voltage and resistive load (Po = 2 kW,
RL: 320 Ω, C: 900 V/ 50 µF, Ca: 100 V/470 µF) (Case 4).
(e) Simulation on PWM rectifier with 800 V dc-link voltage and inductive load (Po = 2 kW,
load RL: 320 Ω, load L: 1 H, C: 900 V / 50 µF, Ca: 100 V /470 µF) (Case 5).
vCa (V)
vCa (V)
Chapter 6-194
(f) Simulation on Boost PFC with 400 V dc-link voltage and full-bridge converter load (Po
= 1 kW, Vo = 48 V, RL: 2.3 Ω, C: 450 V/ 100 µF, Ca: 50 V/1000 µF) (Case 6).
Fig. 6.6 Simulation results of different application cases.
6.6.2 Experimental Verifications
Two prototypes of the dc-link module have been built and implemented by analog
circuit and low cost MCU, respectively, as shown in Fig. 6.7. The designed dc-link module
is used to replace the E-caps in a PFC conversion system. The input of the voltage
compensator is implemented by two 63 V E-caps with rated lifetime of 128,000 hours at
nominal voltage and current stresses under 85°C. Their lifetime is comparable with that of
the film capacitors used in the prototypes. To reduce the conduction losses, four low
voltage (i.e., 100 V) MOSFETs are used in the FB inverter. Therefore, all of the
components in the voltage compensator withstand very low voltage stresses.
vCa (V)
Chapter 6-195
(a) Voltage compensator implemented by an analog controller.
(b) dc-link module implemented by a low cost MCU
Fig. 6.7 Photos of the prototypes.
Fig. 6.8 presents the experimental waveforms on a PFC product by using the
prototype shown in Fig. 6.8(a). Fig. 6.8(a) shows the feedback control signal and output
voltage vab. It reveals that vab is in phase with the feedback voltage ripple signal, therefore,
in phase with the dc-link voltage ripple. The 450 V/940 µF E-caps used in the PFC board
are replaced by a 450 V/ 110 µF power film capacitor with the proposed voltage
compensator. Fig. 6.8(b) gives the captured waveforms tested at 500 W load. It can be
Chapter 6-196
noted that the voltage ripple appears at the output terminal of the proposed dc-link module
is 3.9 V, while the one with E-cap is 4.8 V. The voltage ripple across the power film
capacitor in the proposed dc-link module is still high, which is cancelled by output voltage
of the compensator, resulting in a very low ripple component in the output terminals.
(a) Operational waveforms of the voltage compensator.
(b) Voltage ripples on the dc-link capacitor and the output of the dc-link module.
Fig. 6.8 Experimental verifications of a 400 V dc-link PFC front-end conversion
system prototype (C: 450 V/ 110 µF, Ca: 63 V/940 µF, 500 W load testing).
Chapter 6-197
6.7 Chapter Summary
An active series voltage compensator for reducing dc-link capacitance is proposed.
Accordingly, a dc-link module is introduced and analyzed, which is widely applicable to
capacitor-supported power electronic systems. The voltage compensator in the dc-link
module processes reactive power and withstands the voltage ripple of the dc-link capacitor
only. The simulations on different application cases reveal the feasibility and applicability
of the dc-link module. The steady-state analysis and selection of the dc-link capacitor and
voltage compensator input capacitor are given. Two prototypes are built and implemented
by analog and digital methods, respectively. The experimental evaluations on a PFC
system verify that the required dc-link capacitance can be reduced significantly. The
research makes it possible to design high power density long lifetime cost-effective power
electronic systems.
Chapter 7-198
CHAPTER 7
CONCLUSIONS AND SUGGESTIONS FOR FURTHER RESEARCH
7.1. Summary of the Thesis
This thesis has proposed energy-efficient solutions for both low-to-high voltage and
high-to-low voltage dc-dc power converters. Based on system level considerations, a
uniform fast transient controller and a kind of dc-link capacitance reduction technique have
also been proposed.
By using a switched-capacitor snubber with adaptive energy, the proposed current-
fed FB PWM converter achieves ZCS with minimum resonant energy under each loading
condition. The operation principles of the snubber and the current-fed converter have
been investigated. A 5 kW prototype with output voltage of 15 kV has been built and
tested. It exhibits high efficiency from very light load to nominal load.
By using a symmetric multilevel circuit structure and an asymmetric three-level
circuit structure, two solutions have been proposed for high-to-low voltage power
conversions. The voltage distributions on switch pairs of the multilevel converter are self-
balanced, thus the voltage stresses on them are the same and equal to a fraction of the input
voltage. While the voltage distributions on the two switch pairs of the TL converter are
different and controlled by duty cycles. Accordingly, a hybrid ZVS-ZCS scheme has been
proposed for the MOSFETs and IGBTs used in the TL converter. The proposed two
converters are the promising candidates for providing a single-step conversion from high
voltages (e.g., 1.5 kV, 3 kV) to low load voltages for the on-board applications in railway
systems. Two 2 kW prototypes with input voltage of 1500 V are built to verify the
theoretical analysis.
Chapter 7-199
By using axis transformation of the control state variables, a generalized second-
order switching surface, thus a uniform fast transient controller, has been proposed and
applicable for all basic dc-dc converters (i.e. buck converter, boost converter, buck-boost
converter, Ćuk converter and SEPIC). A unified derivation and design approach has been
presented. The control parameters are obtained readily by considering the component
values of the power stage without any sophisticated calculations. The controller can be
applied for various kinds of low voltage dc-dc converters distributed as loads of the high-
to-low voltage converters.
By connecting a voltage compensator in series with dc bus line, a dc-link module
has been proposed. It aims to replace E-caps used by long lifetime alternatives (e.g.,
power film capacitors) without sacrificing converter performance, power density and cost-
effectiveness. The voltage compensator processes reactive power and withstands low
voltage stress only. Two prototypes have been built and implemented by analog and digital
methods, respectively. The simulations on various kinds of power conversion systems and
experimental evaluations on a PFC have verified the theoretical predictions. The research
makes it possible to design high power density long lifetime cost-effective power electronic
systems. It can be extended to the application of ac-dc front-end high-voltage power
conversion systems.
7.2. Major Contributions
The major contributions of the research work described in this thesis can be
summarized to the following aspects.
1) Proposed a new snubbering concept with adaptive snubber energy for achieving
Chapter 7-200
ZCS with minimized resonant energy at each load.
2) Proposed an asymmetric dc-dc conversion concept with different voltage
stresses on series-connected switch pairs and a hybrid ZVS-ZCS scheme.
3) Proposed a uniform second-order switching surface for all of the basic dc-dc
converters (i.e. buck converter, boost converter, buck-boost converter, Ćuk
converter and SEPIC).
4) Proposed a new concept to reduce the dc-link capacitance by introducing a
series voltage compensator.
5) Analyzed, designed, implemented and tested one 5 kW 15 kV and two 2 kW 1.5
kV high-voltage power converters and other associated low-voltage converters.
7.3. Suggestions for Further Research
The research on the current-fed FB PWM converter has the potential to be applied
for medical X-ray high-voltage generators, which are dominant by series-parallel resonant
type converters up to now. It requires higher output voltage up to 150 kV and much lower
voltage ripple than the prototype designed. It is worthwhile to investigate the feasibility to
apply the proposed ZCS PWM converter for such application and compare the performance
with that of resonant converters.
The application of the proposed dc-link module in other power conversion systems,
such as solar inverters, EV battery chargers and LED road lighting ballasts, should be
investigated and experimentally verified. The lifetime testing of the developed system is
suggested and compared with that of the one with E-caps.
Appendix A-201
APPENDIX A
A.1 Derivation of Eq. (4.34)
The voltage between nodes “A” and “B” shown in Fig. 4.1(a) is tabulated in Table
A.1 during the corresponding intervals. The volt-time value during one steady-state cycle
is given by
2 6 2 8
112 1 1 2 1 2
0
2 / ( ) 2 / ( )6 8 2 2
2 280 0
22
2 1 1 2 2
1( )
2 2
( ) ( ) (1 ) 20
2 2 2 ( )
1
2 (
s
s C p s C p
Tss
AB C dl C C dl C
C V i t C V i tp p s s C
C Cs s p
s CC s C C s
p
D TD TVT v t dt V t V V t V
i t i t D T C VV t t dt V
C C i t
C VV T DV D V T
i t
-
22
1 16 8) ( )
s CC dl
p
C VV t
i t
(A.1)
As the volt-second of the isolation transformer during one steady-state cycle is zero,
the average voltage of VCb is given by
s
dlC
sp
Cs
sp
CsCCCCb T
tV
Tti
VC
Tti
VCVDVDVV 11
8
22
6
222211
2 )()(2
(A.2)
Appendix A-202
Table A.1 Voltage between nodes ‘A’ and ‘B’ and corresponding time intervals.
Time intervals vAB
t0-tdl1 tdl1 VC2
tdl1-t4 11
2 dls t
TD VC1+VC2
t4-t6
2
1 1 sTD VC2
t6-tvCs3=0 )(
2
6
2
ti
VC
p
Cs tC
tiVv
s
pCCs 2
)( 623
tvCs3=0-t8 )(
2
2 6
21
ti
VCTD
p
Css 0
t8- tvCs4=0 )(
2
8
2
ti
VC
p
Cs
(ip(t8)<0) t
C
tiv
s
p
Cs 2
)( 8
3
tvCs4=0-t12
)(
2
2
1
8
22
ti
VCTD
p
Css
VC2
A.2 Derivation of Eq. (4.37) and Eq. (4.39)
The overall volt-second value of the inductor Lf1 is equal to zero in one steady-state
cycle. According to Table A.2,
2 4
1 3
5
4
1 11 1 2 3
11 14 0-1 2-3 5-12
1
1 cos ( ) 1 cos ( )
0
t t
C Cr o r o
t t
tLfC C
o o o ort
V V V Vt t V dt t t V dt
m m
iV V V Vt t V dt V t V t V t
m C m
(A.3)
Therefore, it can be obtained from (A.3) that
Appendix A-203
VVmT
iL
T
t
mT
CL
Tmi
VVCD
mVV
V
Cs
Lflk
s
dl
s
rlk
sLf
Cr
C
o
1
111
1
121
1 22
2
1 (A.4)
By substituting (4.70) into (A.4), it results
VVmT
iL
V
V
mT
CL
Tmi
VVCD
mVV
V
Cs
Lflk
Cs
rlk
sLf
Cr
C
o
1
1
1
1
1
121
1 22
2
1(A.5)
Table A.2 Voltage across output inductor Lf1 and corresponding time intervals.
Time intervals VLf1 ( = vsec - Vo)
t0-t1 VVm
iLt
C
Lflk
dl
1
1
1 -Vo
t1-t2 m
CCL rrlk )( 21 or
C Vttm
VV
)(cos1 11
1
t2-t3
VVm
iLt
m
CL
m
CCLTD
C
Lflkdl
rlkrrlks
1
11
1211
2
)(
2
o
C Vm
VV
1
t3-t4 m
CL rlk
21
orC Vtt
m
VV
)(cos1 32
1
t4-t5 1
11 )(
fL
Cr
mi
VVC
or
LfC VttC
i
m
VV
)( 4
1
11
t5-t12
1
111 )(
2
2
fL
Crs
mi
VVCTD
-Vo
Appendix A-204
A.3 Derivation of Eq. (4.38) and Eq. (4.40)
The overall volt-second value of the inductor Lf2 is equal to zero in one steady-state
cycle. According to Table A.3 and (4.26)-(4.27), in a similar fashion as the derivations of
(A.4), one gets
122
2 2 2 2
22 22
2 2
412
- 2
1
eq Co s C
C Lf s r r C s
lk Lf eqdl
s C s lk C
L V VV mC VD
V V m i T L C V V T
L i m L D Vt
T m V V T L V V
(A.6)
Table A.3 Voltage across output inductor Lf2 and corresponding time intervals.
Time intervals VLf2 ( = vsec - Vo)
t0-t7 22
2
2 dlC
Lflks tVVm
iLT
-Vo
t7-t8 22
22
2 dlC
Lflks tVVm
iLTD
o
C Vm
VV
2
t8-tvCs4=0 2
22
Lf
Cs
i
VmC o
s
LfC VtCm
i
m
VV
2
22
2
tvCs4=0-t11
22
22 2
2
1req
Lf
Css CLi
VmCTD
-Vo
t11-t12 2reqCL orrLfSa VttZititi )(sin]-)(-)([ 1155211sec112
Publications -205
PUBLICATIONS FROM THIS THESIS
Journal / Transaction Papers
[1] Huai Wang, Henry Chung, and Adrian Ioinovici, “A new concept of high voltage
dc-dc conversion with asymmetric voltage distribution on switch pairs and hybrid
ZVS-ZCS scheme,” IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2242-2259,
May 2012.
[2] Huai Wang, Henry Chung, and Adrian Ioinovici, “A class of high-input low-output
voltage single-step converters with low voltage stress on the primary-side switches
and high output current capacity,” IEEE Trans. Power Electron., vol. 26, no. 6, pp.
1659-1672, Jun. 2011.
[3] Huai Wang, and Henry Chung, “A uniform nonlinear control method for dc-dc
converters with fast transient response,” HKIE Trans., vol. 17, no. 4, Dec. 2010.
(Outstanding Paper Award for Young Engineers/Researchers, Hong Kong IE)
[4] Huai Wang, Qian Sun, Henry Chung, Saad Tapuchi, and Adrian Ioinovici, “A ZCS
current-fed full-bridge PWM converter with self-adaptable soft-switching snubber
energy,” IEEE Trans. Power Electron., vol. 24, no. 8, pp. 1977-1991, Aug. 2009.
[5] Ting-ting Song, Huai Wang, Henry Chung, Saad Tapuhi, and Adrian Ioinovici, “A
high-voltage ZVZCS dc-dc converter with low voltage stress,” IEEE Trans. Power
Electron., vol. 23, no. 6, pp. 2630-2647, Nov. 2008.
[6] Huai Wang, and Henry Chung, “Use of a series voltage compensator for reduction
of the dc-link capacitance in a capacitor-supported system,” IEEE Trans. Power
Electron. (to be submitted)
Publications -206
Conference Papers
[7] Huai Wang and Henry Chung, “A novel concept to reduce the dc-link capacitor in
PFC front-end power conversion systems,” in Proc. IEEE Appl. Power Electron.
Conf., 2012, pp. 1192-1197.
[8] Huai Wang and Henry Chung, “Study of a new technique to reduce the dc-link
capacitor in a power electronic system by using a series voltage compensator,” in
Proc. IEEE Energy Convers. Congr. and Expo., 2011, pp. 4051-4057.
[9] Huai Wang, Henry Chung and Adrian Ioinovici, “Analysis and optimized design of
a new dc-dc converter with asymmetrical voltage distribution for stepping down
1500 V to 48 V,” in Proc. IEEE Appl. Power Electron. Conf., 2011, pp. 593-599.
[10] Huai Wang, Henry Chung and Adrian Ioinovici, “A new concept of high input
voltage to low load voltage (1500V-48V) dc-dc conversion with hybrid ZVS-ZCS
and asymmetrical voltage distribution,” in Proc. IEEE Energy Convers. Congr.
and Expo., 2010, pp. 3711-3718.
[11] Huai Wang, Henry Chung and Adrian Ioinovici, “Analysis and optimized design of
an efficient high-voltage converter with high output capacity,” in Proc. IEEE Appl.
Power Electron. Conf., 2010, pp. 1904-1910.
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