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57 58 59 60 61 62 63 64 65 66
59 66
57 64
60 63
Japan
Australia
America,Canada
Europe57 66
Frequency [GHz]
・60GHz帯・幅広い帯域が無免許で利用可能・近距離の超高速無線通信の実現
・QPSK (14 Gbps)
・ダイレクトコンバージョン方式・60GHz PLL (20GHz PLL + 3逓倍 ILO)・60GHz Rx (LNA + Down Conv. Mixer)・60GHz Tx (PA + Up Conv. Mixer)
RFフロントエンド構成図
利用可能な周波数帯域
・60GHz Up-conversion Mixer
0.06/40
0.06/40
0.06/80
0.06/80
50Ω TLMIM TL
PA 回路図 PA チップ写真
・60GHz Power Amplifier
Mixer チップ写真Mixer 回路図
・モデリングしたコンポーネントを用いて設計
・ギルバートセル・RFの片側はトランジスタを用いて終端
[1] Alberto Valdes-Garcia, et al., RFIC 2008(IBM) [2] Mikko Varonen, et al., ESSCIRC 2007 (Helsinki Univ. of Tech)
1.21446.689.92061.565This work
1.1--1113.86045[2] ISSCC 2009
143.53.952.515.86065[1] ISSCC 2009
VDD [V]PDC [mW]PAE [%]P1dB [dBm]Gain [dB]Freq. [GHz]CMOSNode [nm]Reference
1.21446.689.92061.565This work
1.1--1113.86045[2] ISSCC 2009
143.53.952.515.86065[1] ISSCC 2009
VDD [V]PDC [mW]PAE [%]P1dB [dBm]Gain [dB]Freq. [GHz]CMOSNode [nm]Reference
[1] W. L. Chan, et al., ISSCC 2009 (IMEC) [2] K. Raczkowski, et al., ISSCC2009 (Arizona Univ.)
S2
1
Frequency [GHz]
LNA 回路図
LNA チップ写真
・60GHz Low Noise Amplifier
LNA 通過特性
・バイアスポイントを変えることにより利得を制御・~23dB の利得を達成
Down Conversion Mixerチップ写真
・60GHz Down-conversion Mixer
LOin
Vdd
Vdd
Vgs
Vlo
IFout
Vgs
RFinVdd
Down Conversion Mixer回路図
可変利得
ILFDDiv 4
P-CounterDiv 38
P-SwallowerDiv 21,26,31,36
PFD CP LPF
Pre-ScalerDiv 3,4
2 Bit Control
・20GHz+周波数3逓倍器により60GHzを出力
-30dBm-20dBmOutPower
4440Power (mW)
56-6057-66Lock Range (GHz)
MeasGOALILO
-30dBm-20dBmOutPower
4440Power (mW)
56-6057-66Lock Range (GHz)
MeasGOALILO
65nmProcess
1.48Area (mm2)
1.2Supply (V)
88.8mW (1.6 / 72.2 mA)58.8mW (6.27 / 42.82 mA)TotalPower (Dig/Ana)
540, 556, 560, 576540, 560, 580, 600Div. ratio
36Ref. freq. (MHz)
-94 to -97-95 to -100PN@1MHz (dBc/Hz)
-60 to -49-71 to 51 nom -60Ref. spurs (dBc)
19.44, 20.016, 20.16, 20.73619.44, 20.16, 20.88, 21.6Freq. lock (GHz)
17.8-21.4 (18.4%)19-23 (19%)VCO freq. (GHz)
Meas.GOALPLL
65nmProcess
1.48Area (mm2)
1.2Supply (V)
88.8mW (1.6 / 72.2 mA)58.8mW (6.27 / 42.82 mA)TotalPower (Dig/Ana)
540, 556, 560, 576540, 560, 580, 600Div. ratio
36Ref. freq. (MHz)
-94 to -97-95 to -100PN@1MHz (dBc/Hz)
-60 to -49-71 to 51 nom -60Ref. spurs (dBc)
19.44, 20.016, 20.16, 20.73619.44, 20.16, 20.88, 21.6Freq. lock (GHz)
17.8-21.4 (18.4%)19-23 (19%)VCO freq. (GHz)
Meas.GOALPLL
VDD
Vbias
INp INn
INJp INJn
OUTp OUTn
Vctrl
SW
Vinj
INp
INn
INJp
INJn
INp
INn
20GHz OSC +
-ILFD
ILO
PLL layout
ILO layout
656565
CMOSNode [nm]
19.2-8.5-0.6@IF=0.1GHz-519.2This work
34-19-13.5@IF=2GHz90[2]ESSCIRC2007
30-5-6.5@IF=10GHz529[1]RFIC2008
LO-RF Isolation [dB]
RF Output @1dB [dBm]
Conversion Gain[dB]
LO P.[dBm]
DC Power[mW]Reference
656565
CMOSNode [nm]
19.2-8.5-0.6@IF=0.1GHz-519.2This work
34-19-13.5@IF=2GHz90[2]ESSCIRC2007
30-5-6.5@IF=10GHz529[1]RFIC2008
LO-RF Isolation [dB]
RF Output @1dB [dBm]
Conversion Gain[dB]
LO P.[dBm]
DC Power[mW]Reference