Performance Challenges of Future DRAM´s SINANO WS, Munich, Sept. 14th, 2007 M. Goldbach / J. Faul

Performance Challenges of Future DRAM´sSINANO WS, Munich, Sept. 14th, 2007

M. Goldbach / J. Faul

Qimonda · M. Goldbach · Month Date, Year · Page 2 For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.

Content

Introduction

DRAM Challenges

Array Device Scaling

Support Device Scaling

Conclusion


Introduction

DRAM Challenges



Conclusion


MOS Transistor Scaling (1974 to present):MOS Transistor Scaling (1974 to present):

Note: Scaling refers to gate half Pitch in nm

Introduction I

Pitch

Half Pitch

250 180 130 90 65 45 32 22

0.5x

0.7x

HP logic

HP logic: Speed & area driven

DRAM: Area & speed driven

more nodes, however smaller steps


Introduction II

ITRS Roadmap 2001:

Scaling continues, however, logic scaling slowed down to 3 yrs cycle


Scaling history for

- power-supply voltage Vdd

- threshold voltage Vt

- gate oxide thickness tox

Vdd, Vt and tox saturate!

Key Question: Are we approaching the limit of silicon scaling!?Key Question: Are we approaching the limit of silicon scaling!?

Introduction III


Ref. 1

Introduction IV

Power Consumption:

Both, passive and active power density increase

8” hot plate at 1500W

Reason: Demand for ever increasing performances


Introduction

DRAM Challenges



Conclusion


DRAM´s are offered in various densities & architectures:

Synchronous DRAM: Data, commands, and addressessynchronized with clock

Single data rate (SDR)

Double data rate (DDR)

Double data rate II (DDR II)

DRAM Challenges I (Architectures)

Vdd

Vss

Vddq

Vssq

Clock

Adresses

Data (DQ)

Commands

DRAM

Simplified Block Diagram DRAM

Clock

Data SDR

Data DDR

Data DDR II (double freq)

Commands DDRII


DRAM Challenges II (Speed Classes)

For DDR, data rate 2x clock frequency (both graphics and main memory)

Ref. 2


DRAM Challenges III (Array Access)

Array Access:

• tAA ~ Tpd

• Higher densities: More speed critical

• speed depends on parasitics

tAA: Array Access Time

Tpd: Propagation delay Ref. 2


DRAM Challenges IV (General Remarks)

• Strong Interaction Array / Support Device Design

- Defect Treatment

Required for long data retention, however, limited doping activation

- Structuring

Structure both, dense array and logic circuits in same steps

- Density / Aspect ratios

Driven by very dense cell areas

- Low leakage requirements

Junction leakage < 1fA per node in array

Array transistor: < 1fA to ensure data retentionSupport transistors: Ioff ~10pA/µm (high speed logic ~100nA/µm)

• Low Complexity & overall costs


Introduction

DRAM Challenges



Conclusion


Array Device Scaling I (Asymmetric Device)

• Asymmetric Device: Low Node leakage & low Ioff

by asymmetric well doping

Localized Doping

@ BL-sideLow Field required byhigh Retention time

Localized Doping

@ BL-sideLow Field required byhigh Retention time

WL

BL

Cnode

WL

BL

Cnode

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

-1 -0.5 0 0.5 1 1.5 2 2.5

Vgate [V]

Ids

[A]

Forward Reverse

T = 85°CVds=1.3V

Forward

Reverse

Reverse: Source @ Node

Forward: Source @ Bit Line (BL) - contact

DRAM cell schematics

Asymmetric cell device

Ref. 5


Array Device Scaling II (EUD Device)

X-section along device (perpendicular WL)

X-section width device (parallel WL)

• All major DRAM companies convert from planar to 3D devices in the 60-90nm nodes

• Example: Qimonda´s Extended U-shape device (EUD)

Ref. 3


1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

-0.5 0 0.5 1 1.5 2

Vg / V

Id /

A

Vd=0.05V

Vd=1.30V

15

20

25

30

0,00 5,00 10,00

corner depth / nm

Id /

uA

95,00

100,00

105,00

110,00

115,00

120,00

slo

pe

/ (m

V/d

ec

)

Id

slope

1,E+01

1,E+02

1,E+03

1,E+04

-1,2 -1,1 -1 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0

VNWLL (V)

Fai

lco

un

t (a

rb. u

nit

s)

Planar array device

EUD array device

Transfer Characteristics

Side gate device Impact

Data retention Characteristics

Target Vnwll

• Introduction of EUD for node field reduction

(no current gain expected)

• Current modification by side gate

Array Device Scaling III (EUD Device)

Ref. 3


Array Device Scaling IV (FinFet in Array)

1,0E-14

1,0E-13

1,0E-12

1,0E-11

1,0E-10

1,0E-09

1,0E-08

1,0E-07

1,0E-06

1,0E-05

1,0E-04

-0,5 0 0,5 1 1,5 2 2,5 3

Vgate

I ds

Ids (Vd=1.3V, Vpw= 0V)

Ids (Vd=1.3V, Vpw=-1V)

Ids (Vd=1.3V, Vpw=-2V)

Fig.12: Measured FinFET I-V characteristics of the 90nm demonstrator for different p-well voltage (V).

FinFET

BuriedStrap

Trench

BitlineContact

FinFET

BuriedStrap

Trench

BitlineContact

Wordline

Si-Fin

Wordline

Si-Fin

X-section along device (perpendicular WL)

X-section width device (parallel WL)

Motivation for FinFet:

• Slope of 80mV/dec @ 85°C achieved

• Ids of ~ 30µA achieved

• no Body effect

No body effect

Potential Future: FinFet in array

Ref. 4


Array Device Scaling V (Array Path)

Ref. 2


Introduction

DRAM Challenges



Conclusion


Support Device Scaling I (History)

10

100

1000

1996 1999 2002 2005 2008

Year

Lo

g (

Ld

es)

L_n

L_p

Logic_ITRS_2001

DRAM Support Device Scaling:

• Lpoly scales by ~0.5x every 3 years

• DRAM support transistors longer than

high speed logic devices but comparable to low standby power

• Since ~ 2006: Lpoly(pf) = Lpoly(nf)

(Dual gate work function processes)

• Off current constraints:

Logic Lpoly scaling slows down

Lpoly scaling drives scaling of other properties as well

DRAM

Ref. 5


Support Device Scaling II (Topics & Issues)

Scaling Topics Issues

Ref. 2


Support Device Scaling III (Gox scaling)

Gate Oxide Scaling:

Gate Oxide Leakage:Ig(tox) = A0 exp(–B0tox)

• Direct tunnelling thru dielectric

• Ig(nf) ~ 1.5 dec higher than Ig(pf)

(Reason: Hole vs. electron tunneling)

• Ig / tox ~ 1dec / 2 Angstrom

For tox 2.5nm Ig uncritical

(Ig < 10pA/µm²)

Between 2 < tox < 2.5nm

Ig needs to be considered

Below 2nm: High k gate dielectricsmight be employed

(Eqivalent oxide thickness (EOT))Ref. 6


Support Device Scaling IV (Scaling Path)

Ref. 2


Introduction

DRAM Challenges



Conclusion


• Scaling of Si technology not yet reached will continue down below 30nm ground rules

• Unlike logic, DRAM support device design obey array driven limitations (e.g. doping activation, structuring, low leakage requirements)

• Array device scaling path:conventional asymmetric doping 3D structures

• Support device scaling path:conventional adaptions (e.g. stress, high k) 3D structures

Conclusion


1. “Silicon CMOS devices beyond scaling”, W. Hänsch et al., IBM J. of Res. and Dev. 50, 2006.

2. DRAM short course, VLSI 2007, by S. Hong.

3. “A 58nm Trench DRAM Technology”, T. Tran et al., IEDM 2006.

4. “DRAM Scaling Roadmap to 40nm”, W. Müller et al., IEDM 2005.

5. “Transistor Challenges – A DRAM Perspective”, J. Faul et al., NIM in Phys. Res. B 237 (2005) 228-234.

6. “Ultra Low Power SRAM technology”, R.W. Mann et al., IBM J. of Res. and Dev. 47, 2003.

References

Thank you

The World’s LeadingCreative Memory Company

Documents

Performance Challenges of Future DRAM´s SINANO WS, Munich, Sept. 14th, 2007 M. Goldbach / J. Faul