Microelectronics Reliability 54 (2014) 2253–2257

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Microelectronics Reliability

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Performance and reliability trade-offs for high-j RRAM

http://dx.doi.org/10.1016/j.microrel.2014.07.1350026-2714/� 2014 Elsevier Ltd. All rights reserved.

⇑ Address: 20 Dover Drive, SUTD, Singapore 138 682, Singapore. Tel.: +65 98621185; fax: +65 6779 5161.

E-mail address: nagarajan@sutd.edu.sg

Nagarajan Raghavan ⇑Engineering Product Development Pillar, Singapore University of Technology and Design, Singapore 138 682, Singapore

a r t i c l e i n f o

Article history:Received 17 July 2014Accepted 17 July 2014Available online 19 August 2014

Keywords:Design for reliabilityEndurance degradationFilamentOxRAMRead disturb immunityRetention loss

a b s t r a c t

Resistive random access memories (RRAM) have shown tremendous potential in replacing Flash technol-ogy for future non-volatile data storage device applications in just about a couple of years from now.Although RRAM has various advantages in terms of simple design, high density integration and CMOScompatible process flow, it has its own intrinsic constraints in terms of variability and reliability, justas is the case for any other technology. While performance and reliability are both key metrics for anynew product or technology design initiative, the critical aspect to investigate is the trade-off involvedin improving them, as the measures implemented to boost performance do not necessarily have a posi-tive impact on its reliability (lifetime). Optimization of the RRAM design for commercial applicationsrequires a clear understanding and acknowledgment of these performance – reliability trade-offs. Thisstudy presents a qualitative perspective to identifying and understanding these trade-offs and probingthe various sources of variability in high-j RRAM.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Resistive random access memory (RRAM), which comprises of asimple metal–insulator–metal (MIM) structure, has been at theforefront of non-volatile memory technology research for the pastfew years and is touted to be the most suitable alternative toreplace NAND Flash technology in around 2016–17. The popularityof RRAM is attributed to its simple design, standard CMOS compat-ible materials, high integration density and localized phenomenongoverning the binary data storage in terms of the dielectric con-ductance, in contrast to Flash technology where the threshold volt-age shift due to charging and discharging is area-dependent andscalability becomes a critical concern as devices operate with onlyfew tens of electrons, the loss of a few inducing substantial param-eter variability issues and shrinking the program/erase memorywindow beyond the acceptable range. Table 1 provides a qualita-tive comparison of RRAM with Flash and other potential candidatetechnologies such as spin transfer torque magnetic RAM (STT-RAM) and phase change RAM (PCRAM).

Of the many mechanisms postulated to explain the localizedswitching phenomenon in RRAM [1], the two popular ones areoxygen vacancy–oxygen ion based (Fig. 1) [2] and metal migrationbased (Fig. 2) [3]. While the former operates due to dielectricvoltage and temperature stress induced defect creation (bond

breaking) and percolation breakdown followed by bipolar drift-assisted oxygen ion transport and its recombination with thevacancies (referred to as OxRAM), the latter operates by means ofionic migration of metal ions/atoms from the electrode to formconductive filaments (CF) and subsequent rupture of the filamentby Joule Heating (referred to as CBRAM) [4,5].

As is the case for any electronic device, RRAM is also prone tovarious reliability and variability issues, while the traditional focushas been on enhancing performance metrics such as low switchingpower, wide memory window, low switching voltage, thin dielec-tric and small area footprint. In terms of reliability, the key issuesare endurance and retention degradation as well as read disturbfailure. From a variability perspective, the dielectric microstructure(with presence of weak link grain boundaries where filaments aremost likely to nucleate), device area and roughness of metal-dielectric interface remain a major hindrance to be addressed.When optimizing performance, we may most certainly have tomake a compromise with the device useful lifetime. It is thereforeessential to carry out a multi-objective optimization study consid-ering performance, reliability and variability all at once. The pur-pose of the study here is to provide an overview of the possibleoperational, material and process design factors that govern thetrade-off between performance and reliability/variability in high-j based RRAM so that future research initiatives are focused onaddressing these complexities in a better way. We shall nowanalyze the influence of the following factors one by one (Fig. 3)– dielectric microstructure, current compliance, dielectric thick-ness, electrode material, device area, switching voltage pulsing

Table 1Qualitative comparison of the RRAM technology with other upcoming non-volatile memory candidates suchas phase change memory (PCM), magnetic spin-transfer-torque RAM (MRAM) and the current NAND Flashtechnology under use, with respect to various standard reliability and performance metrics.

FLASH PCM MRAM RRAM

Endurance High Moderate Very High High

Retention Low High Very High High

Fabrication CMOS New Materials New Materials CMOS

Voltage Very High High High Low

Power Moderate High Low Moderate

Scalability High Moderate High Very High

Variability Moderate High High High

Switching Speed High Low Very High Very High

Fig. 1. Schematic illustrating the forming/SET and RESET events for an M–I–MOxRAM stack with high-j dielectric. The process of filament formation is governedby the percolation theory (soft breakdown). If a higher value of Icomp is chosen, thefilament grows laterally. Subsequent RESET is initiated by reversing the polarity ofthe voltage (bipolar stress) so as to facilitate recombination of the mobile oxygenions stored in the electrode with the vacancies residing in the dielectric thatconstitute the filament, eventually resulting in a tunnel barrier. The red and whitefilled circles refer to the oxygen ions and vacancies respectively. (For interpretationof the references to colour in this figure legend, the reader is referred to the webversion of this article.) Note that LRS and HRS refer to low and high resistance staterespectively.

Fig. 3. Various process, operational and material design factors that impact thefailure mechanisms (endurance degradation, retention loss and read disturb) inRRAM. The different aspects to be studied to have a complete understanding of thedegradation phenomenon are listed.

Fig. 2. Illustration of the switching phenomenon in conducting bridge RAM(CBRAM) where forming/SET involves the migration of metal atoms/ions from theelectrode to create a metallic filament and RESET involves the rupture of thisfilament due to Joule Heating. CBRAM devices are non-polar, i.e. they can beoperated in both the unipolar and bipolar modes of operation, as the RESETmechanism is not voltage polarity driven, rather it is current density driven.

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parameters, device architecture (1T-1R, 0T-1R) and filament shape/size engineering.

2. Role of dielectric microstructure

High-j dielectrics such as HfO2, thicker than 5 nm, are prone tobe polycrystalline either during the deposition or the annealing

process. This implies that there are grain boundaries (GB) that linkboth the electrodes in the device, as shown in Fig. 4(a). Since theseGB contain higher local concentration of oxygen vacancy defects,they help in reducing the forming voltage (VFORM) significantly[6]. Forming refers to the very first event of creating a conductivefilament in a virgin dielectric with very few as-processed defects.By purposely having GB fault lines, the forming power can be sub-stantially reduced. The downside however is that the variability inthe number of defects in the GB of different devices induces widerspread in VFORM (shallower Weibull slope) as it is not easy to con-trol (Fig. 4(b)). Also, being intrinsically more ‘‘trappy’’, the memorywindow appears to be smaller in this case as the high resistancestate (HRS) is not as deep as we would like it to be (this is due tohigher concentration of defects that stay permanent or inert atthe GB sites). Therefore, the endurance degradation trends aremore severe for GB-assisted switching (Fig. 4(c)). It has beenshown that oxygen vacancies generated elsewhere in the bulk(grain) of the device also have a thermodynamic tendency to seg-regate towards the GB leading to vacancy accumulation [7], imply-ing that, with cycling, the filament is likely to dilate laterally whichdeprives us of low power operation and shrinks the memory win-dow even further (due to shallower HRS state).

Controlling the grain size distribution is another challenge(Fig. 4(d)). As an example, typical grain sizes in HfO2 have a distri-bution with the mean diameter being 25 nm and a deviation ofapproximately 8–10 nm [8]. With RRAM expecting to be commer-

Fig. 4. (a) Formation of filament (percolation path) along the grain boundary(serves as weakest link) contour across the dielectric. The red and purple dotsrepresent pre-existing defects localized at the GB and stress induced defectsrespectively. (b) Lateral shift and change in shape of the forming voltagedistribution when the dielectric microstructure is altered from amorphous topolycrystalline for the same physical oxide thickness. (c) Sketch of the expectedendurance degradation trend with a faster shrinkage of the memory window for thepolycrystalline stack. The symbol NSW refers to the number of switching cycles. (d)Possibility of a 10 � 10 nm2 device containing zero, one or more than one (triplepoint) GB lines, which results in large variability of the switching trends. (e and f)Extracted distribution of the xX and xY values for the filament (by fitting I–V slowsweep data to the QPC model) with {xX,xY} being inversely correlated to the lengthand width of the filament constriction respectively [10]. (g) Tendency for vacanciesto accumulate around the GB (thermodynamically favored) which increases the sizeof the filament and stabilizes it in the LRS state, resulting in improved retention.(For interpretation of the references to colour in this figure legend, the reader isreferred to the web version of this article.)

N. Raghavan / Microelectronics Reliability 54 (2014) 2253–2257 2255

cialized with dimensions of 10 � 10 nm2 [9], it is likely that somedevices would have zero GB, while some may have two, three (tri-ple point) or even more. As a result, the aggressively downscaleddevices will have very severe variability in the switching voltageand HRS resistance values.

Since the GB tends to localize the evolution of the filament,using the Quantum Point Contact (QPC) I–V formulation to quan-tify the shape and size of the filament in terms of the frequencies{xX, xY} for the energy bands, it has been proven that the filamentshape (lower spread in xX and xY) is more well controlled in thepresence of GB (Fig. 4(e and f)) [10]. Therefore, having GB couldbe an advantage for RRAM operation as long as we can ensure thatevery device has precisely one GB. Moreover, in terms of retention,since GBs tend to accumulate vacancies (Fig. 4(g)), the data in thelow resistance state (LRS) state can be stored for a longer period of

time in spite of oxygen ion self-diffusion from the electrode, asthere are many more defects to be passivated in order to introducea tunnel barrier.

3. Role of current compliance

The compliance level (Icomp) used for switching determines thehardness of the breakdown (forming/SET) event. In effect, theresistive switching mechanism is similar to the process ofdielectric breakdown and its partial recovery, as reported recently[11–13]. When a higher Icomp is chosen, the filament is allowed tonucleate and then subsequently grow (laterally dilate), analogousto soft and progressive breakdown in ultra-thin dielectrics(tox < 5 nm). With higher Icomp, since the filament is larger in size,we can logically expect retention to be better as the filament ismore stable. The local filament temperature (TFIL� 298 K) duringthe reset process [14] is also higher in such cases and as a resultthe ionic drift and recombination process is thermally stimulatedensuring good switching from the LRS to HRS. Therefore, endur-ance is also expected to be prolonged. With larger number ofdefects (higher Icomp), the variability in resistance state is alsolow [15] and current noise is substantially reduced resulting inbetter disturb immunity. The downside though is that the switch-ing power is substantially high. From a performance perspective,we have to compromise for high power operation in order toenhance reliability and reduce variability in the switching processover the entire lifecycle of the memory device.

4. Role of dielectric thickness

The thickness of the dielectric (tox) is in some sense correlatedto the compliance level (Icomp) as both of these impact the hardnessof the breakdown/SET event. Thicker dielectrics are more prone tohard breakdown (HBD) as the instant of percolation is hard to con-trol and catastrophic. We therefore risk the possibility of compli-ance overshoot if Icomp is kept too small. If the RRAM suffers aHBD event, it may lose its switching capability as the dielectricmay be too highly conductive (due to other mechanisms such asabrupt metal migration into the dielectric shorting the two elec-trodes together) for any filamentary rupture to be possible. In gen-eral however, for moderate dielectric thickness, the endurance andretention lifetime are expected to improve as the thicknessincreases, both in their mean values as well as the spread whichgoes down (harder forming for thicker dielectrics results in higherlocal filament temperature, TFIL). The effect of roughness at themetal–dielectric interfaces, which remains a key process issue totackle, is not so detrimental when thicker stacks are considered.However, for low power applications and combined vertical–lat-eral scaling, it is necessary to eventually scale down the dielectricin order to realize an areal footprint of 10 � 10 nm2.

5. Role of electrode material

As for OxRAM, the choice of the electrode material is governedby its oxygen solubility, while for CBRAM, the nature of metalmigration and bulk melting point of the metal are key consider-ations. Electrodes such as W, Ni, Ti, Pt and Hf are considered idealfor OxRAM, while Ni, Cu and Ag have been extensively investigatedfor CBRAM application [16]. For vacancy modulated resistiveswitching phenomenon, Monte Carlo simulation studies [17] haveshown that endurance distribution is more favorable if the fila-ment is asymmetric in shape. This can be achieved by choosingtop and bottom electrode materials with very different oxygenscavenging ability so that the defect distribution to start with priorto forming is already asymmetric. Ni and Cu are the two most

Fig. 5. Four different configurations of the oxygen–vacancy filament in OxRAM forthe different resistance states and compliance levels chosen for switching. Whileconfiguration (A) and (D) represent fully Ohmic and deep reset regimes withspatially uniform potential drop (as conventionally expected), configurations (B)and (C) correspond to the special case of a Quantum Point Contact (QPC) mode withthe narrow constriction of defects governing the stability (read disturb) of thememory device and the voltage dropping locally at these filament–constrictioninterfaces, as shown by the potential profile in the bottom sketch of the figure. Sincethe configurations B and C are commonly encountered for LRS at low Icomp and HRSat high Icomp, the disturb immunity of the OxRAM device depends on the localelectric-field at these constriction ends, which can be quite high. This makesOxRAM vulnerable to read-disturb issues even at low read voltages ofVREAD = 100 mV.

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suitable materials for CBRAM application as Ni, which is a popularcontact metal for drain/source contacts in transistors enablesfront-end integration of RRAM with the logic devices and Cu,which is the current choice for back-end interconnect applications,enables RRAM to be placed across different levels of the metal linesin the complex network. Gradual oxidation of the metal electrodeis one of the postulated mechanisms to explain the shrinkage ofthe memory window during endurance cycling. It is necessary totherefore choose electrode materials that have a less favorable freeenergy change for the oxidation process. The heat confinementwithin the filament is also a key determinant of reliable switching.If the electrodes have a lower thermal conductance, that will alsoassist in reducing the voltage requirements for switching andenable longer lifetime for the RRAM.

6. Role of device area

Although switching is a local phenomenon, the very first form-ing event on a virgin dielectric is an areal percolation process withPoisson random defect generation. The smaller the device area, thehigher the forming voltage (VFORM) needed to create a filament.When VFORM is too high, it is possible for the forming process tobecome uncontrolled and catastrophic. Therefore, the robustnessof the forming event becomes questionable as we go down to smal-ler device area. On the contrary, if the device area is too large, thenthere exists a statistically finite probability of new filament nucle-ation away from the previous ones even though VSET is much lowerthan VFORM. The presence of more than one filament introduces alot more variability into the HRS resistance distribution. As a result,an optimum range of area exists where both these issues are min-imal for reliable switching operation.

7. Role of pulsing parameters (Vps,Tps)

Speed is one key performance metric and can be gauged byapplying different pulsing schemes to the RRAM device withrepeated ON and OFF. For higher speed (lower Tps), the value ofVps would have to be increased. If the Vps value is too high, thestress experienced by the dielectric during the reset process (whenthere is no compliance cap) may induce additional defects furtherdegrading the oxide. In other words, the rate of ionic drift andrecombination may be overtaken by the rate of additional field-induced defect generation. Careful choice of the pulsing conditionsplays a key role in enhancing the endurance lifetime. The values of{Vps,Tps} and the asymmetry of the time duration for SET and RESEThave been shown to impact the endurance trends significantly byLu et al. [18].

8. Role of device architecture

To avoid current overshoot and ensure internal compliance con-trol, RRAM devices are often integrated with the transistor in seriesas a 1T-1R architecture. During operation of the RRAM, it is alsopossible for the transistor to degrade due to time dependentdielectric breakdown or bias temperature instability that causesits threshold voltage (Vth) to increase gradually. This degradationin the Vth value may make it more difficult for the RRAM to turn-on and reach the SET state during repeated cycling, because theeffective voltage drop across the RRAM stack decreases and voltageacross the transistor increases. Such a scenario may be termed as a‘‘soft error’’ for the RRAM as enhancing the pulse voltage maycontinue to trigger switching as per normal. The gist of this sub-section is to direct focus on the transistor as well when a compre-hensive reliability study on RRAM is carried out. The root cause ofdegradation in the performance of the switching memory may not

originate from the M–I–M stack, but instead from the M–O–S tran-sistor stack connected in series.

9. Role of filament size and shape

It is often assumed that the potential drops across the conduc-tive filament uniformly both in the HRS and LRS. While this may betrue in some cases, there are intermediate resistance states withfew vacancies in the filament wherein the potential distributionis spatially non-uniform and concentrated more at the narrow con-striction (necking point) with very few defects in an asymmetrichour-glass shaped filament (refer to Fig. 5) [19,20]. In such cases,the local electric field can be many times higher than the standardfield of (V/tox), thereby making the device highly prone to read dis-turb events at low read voltages of VREAD = 100 mV. Read disturbevents are more likely in the HRS for high Icomp and in the LRS forlow Icomp because in both these scenarios, the filament would com-prise of very few defects with a narrow constriction. This local fieldconcentration evolves from the Quantum Point Contact (QPC) for-mulation [21] for a low defect count chain in the dielectric. Theinterference of the incident and reflected electron wavefunctionsat the filament–constriction interfaces causes the field to be locallyintensified. Immunity to disturb events is therefore possible only ifwe can switch all the way from a shallow LRS state (highly Ohmicfilament) to a very deep HRS state (sufficient rupture and creationof thick oxide barrier), corresponding to a large memory window of4–5 orders in magnitude. It is however practically difficult to

Table 2Impact of various design metrics on the endurance and retention lifetime as well as read-disturb immunity of the OxRAM device. The green and red arrows representimprovement and deterioration in lifetime respectively.

Lifetime Endurance cycles Retention lifetime Read disturb immunity

Increase Icomp " in LRS; in HRS

Higher tox

Increase area –

Thin filaments (SBD) with field intensificationLower grain size " in LRS

; in HRS

Asymmetric filament shape ; in LRS

N. Raghavan / Microelectronics Reliability 54 (2014) 2253–2257 2257

consistently achieve such large windows of switching, more so forthin dielectric stacks. Therefore, read disturb events are prone toexist in either of the two resistance states depending on the Icomp

chosen for operation.

10. Summary and conclusions

A summary of the expected impact of various design metrics onendurance, retention and read disturb (the three key reliability cri-terion) is presented in Table 2. These design metrics (material, pro-cess, architecture and operational) are bound to have a glaringeffect on the lifetime and cyclability of RRAM devices. In mostcases, the measures taken to enhance reliability/reduce variabilityresult in a degradation of the performance of the memory device(speed, memory window and switching voltage). These trade-offsbetween reliability/variability and performance are bound to existand the device has to be optimized with acceptable range of valuesfor all these three criteria. Although RRAM devices are simple todesign and fabricate, there are many complexities in understand-ing and optimizing them. Further research is required in this areaof multi-objective robust design of the RRAM stack before it is via-ble for commercialization with an area as low as 10 � 10 nm2.

Acknowledgement

The author would like to thank the International Design Center(IDC) at the Singapore University of Technology and Design (SUTD)for resource support and travel funding for this project under GrantNo. IDG11300103.

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