PEE LAB MANUAL.doc

8/18/2019 PEE LAB MANUAL.doc

1/77

1. Verification of Kirchhoff ’s Voltage and Kirchhoff’s Current Law

AIM: To verify the Kirchhoff’s Voltage Law and Kirchhoff’s Current Law for a given circuit.

APPARAT! R"#IR"$:%

!l.

&o.&a'e of the Co'(onent !(ecifications #uantit)

1 Resistors 1.1KΩ, 2.2KΩ !.!KΩ 1 each

2 "read "oard # 1

! $.R.%.&. '(#!() V 1

* +eters '(#2(()+ !

- Volteters '(#!()V ! Connecting wires &ingle strand Re/uired

T*"+R,:#

KCL0 This law states that the algeraic su of currents eeting at a unction of conductors is 3ero. 4n

other words, the su of currents flowing away fro a unction is e/ual to the su of currents flowing

towards the unction.

Kirchhoff’s current law is nothing ore than a restateent of 5rinci5le of conservation of

charge. &ince the aount of charge entering a unction at an instant ust e sae as the aount of

charge leaving the unction.

KVL: This law states that any tie instant the algeraic su of voltages around a closed circuit or a

loo5 is 3ero. That is, for a closed circuit having 678 eleents,

K

9V:(

:(-here V re(resents the /oltage dro( across the th ele'ent.

V10V0V20333.V4 5 6

1


2/77

This stateent si5ly tells us that if we start fro a 5articular unction and go around a closed

circuit so as to coe ac7 to the sae unction, the net 5otential dro5 'or 5otential rise) is 3ero,

ecause we have coe ac7 to the 5oint at the sae 5otential.

Kirchhoff’s Voltage Law can also e stated as in any closed circuit the algeraic su of the

5roducts of current and resistance in each of the conductors is e/ual to the algeraic su of the ef’s

of the atteries

CIRCIT $IA7RAM:

2


3/77

PR+C"$R" 8+R KCL:%

1. Connect the circuit as 5er the figure shown aove.

2. +dust the in5ut voltage as 1( volts, and switch on the su55ly.

!. ;easure the current flowing through R1, R2, R! resistors using +eters i.e., 4T, 41 42.

*. Taulate the readings in the taular colun.

9. Verify that the IT : I1 0 I.

. Re5eat the 5rocedure for different voltage values, and then switch off the su55ly.


4/77

TALAR C+LM&!:

8or KCL:

!.&o V1;/olts< IT;'A<

theoretical

IT;'A<

(ractical

I1;'A<

theoretical

I1;'A<

(ractical

I;'A<

theoretical

I;'A<

(ractical

8or KVL:

!.&o I;'A< V1;/olts<

theoretical

V1;/olts<

Practical

V;/olts<

theoretical

V;/olts<

(ractical

V2;/olts<

theoretical

V2;/olts<

(ractical

!A8"T, PR"CATI+&! :

1. Reading ust e ta7en without 5aralla error.

2. ;easuring instruents ust e connected 5ro5erly should e free fro errors.

!. +ll connections should e free fro loose contacts.

*. The direction of currents should e identified correctly.

R"!LT:

*


5/77

VIVA V+C" #"!TI+&!:

1. Dhat is KCLE $efine with res5ect to node.2. Dhat is KVLE $efine with res5ect to loo5.!. Fn which 5rinci5le KCL wor7sE*. Fn which 5rinci5le KVL wor7sE-. Dhat is e/uivalent resistance when three resistors are connected in seriesE. Dhat is e/uivalent resistance when three resistors are connected in 5arallelE


6/77

. !"RI"! A&$ PARALL"L R"!+&A&C"

AIM: % To find the resonant fre/uency, /uality factor, and and width of a series and 5arallel resonant

circuit.


7/77

A PPARAT! R"#IR"$ :

!.&o. "=ui('ent Range T)(e #uantit)

1. &ignal generator 2. $ecade resistance o!. $ecade inductance o*. $ecade ca5acitance o-. +eter . Connecting wires

T*"+R,:

4n a series RLC circuit. The current lags ehind or leads the a55lied voltage de5ending u5on the

values of JL and Jc. JL causes the total current to lag ehind the a55lied voltage while Jc causes the

total current to lead the a55lied voltage. Dhen JL Jc the circuit is 5redoinantly inductive, and

when JL Jc the circuit is 5redoinantly ca5acitive.

4n the series RLC circuit resonance ay e 5roduced y varying the fre/uency 7ee5ing L and C

constant. Ftherwise resonance ay e 5roduced y varying either L or C for fied fre/uency .%arallel

resonance occurs when JL : Jc. when JL : Jc the two ranch currents are e/ual in agnitude and

1H( deg out of 5hase with each other .Mence two currents cancel each other and net current is 3ero.

CIRCIT $IA7RAM:

!eries Resonance


8/77

Parallel resonance:

PR+C"$R":

1. Connect the circuit as shown in fig.1 for series resonant circuit fig.2 for 5arallel resonant

circuit.

2. &et the voltage of the signal fro function generator to -V.

!. Vary the fre/uency of the signal fro 1(( M3 to 1KM3 in ste5s and note down the

corres5onding aeter readings.

*. Fserve that the current first increases then decreases in case of series resonant circuit the

value of fre/uency corres5onding to aiu current is e/ual to resonant fre/uency.

-. Fserve that the current first decreases then increases in case of 5arallel resonant circuit

the value of fre/uency corres5onding to iniu current is e/ual to resonant fre/uency.. $raw a gra5h etween fre/uency and current calculate the values of andwidth /uality

factor.

TALAR C+LM&:

H


9/77

S.No.

Series Resonance Parallel Resonance

Frequency(Hz)Current(mA)

Frequency(Hz

)

Current(mA)

M+$"L 7RAP*!:

8+RMLA":

!eries Resonance:

Resonant Bre/uency 'f r ) : 1@'2NOLC)

Lower cut off fre/uency 'f 1) : fr#R@*NL

P55er cut off fre/uency 'f 2) : fr?R@*NL

I


10/77

Quality factor Qr : r L@R : 1@r RC

"and Didth : f 2#f 1 : R@2NL

Parallel Resonance:

Resonant Bre/uency 'f r ) : 1@'2NOLC)

Lower cut off fre/uency 'f 1) :fr#1@*NRC

1 : '#1@2RC) ?O''1@2RC)2 ? '1@LC))

P55er cut off fre/uency 'f 2) : fr?1@*NRC

2 : '1@2RC) ?O''1@2RC)2 ? '1@LC))

Quality factor Qr : r CR : f r @".D

"and Didth : f 2#f 1 : 1@2NRC

PR"CATI+&!:

1. +void a7ing loose connections.

2. Readings should e ta7en carefully without 5aralla error.

!. +void series connection of volteters and 5arallel connection aeters.

R"!LT:%

2. $"T"RMI&ATI+& +8 T-+ P+RT

1(


11/77

&"T-+RK PARAM"T"R!

AIM: To deterine S and 5araeters of a given two 5ort =etwor7.

APPARAT!:

!l.

&o.&a'e of the Co'(onent !(ecifications #uantit)

1Two %ort networ7 %araeters

trainer 7it# 1

2 $.R.%.&. '(#!() V 1

! +eters '(#2(()+ 1* Connecting wires &ingle strand Re/uired

T*"+R,:

+ networ7 containing two 5airs of terinals is called as two (ort networ4 . =orally one 5air

of terinals coing together to su55ly 5ower or to withdraw 5ower or to easure the 5araeters, are

called as (ort. To achieve si5licity, the whole networ7 is shown with a single loc7. + ty5ical two

5ort networ7 is as shown elow in fig 'a)

+P"& CIRCIT IMP"$A&C" PARAM"T"R! ;>%(ara'eters%(ara'eters can e defined y the following e/uations

V1 : S11 41 ? S12 42 UUUUUUUU '1)

11


12/77

V2 : S21 41 ? S22 42 UUUUUUUU '2)

;atri for0

4f 5ort 2#21 is o5en circuited, i.e. 42 : ( then S11 : V1@41 S21 : V2@41

4f 5ort 1#11 is o5en circuited, i.e. 41 : (, then S12 : V1@42 S22 : V2@42.

Mere,

>11 is the dri/ing (oint i'(edance at 5ort 1#11 with 2#21 o5en circuited. 4t can

also e called as o(en circuit in(ut i'(edance.

>1 is the transfer i'(edance at 5ort 1#11

with 2#21

o5en circuited. 4t can also ecalled as o(en circuit forward transfer i'(edance.

>1 is the transfer i'(edance at 5ort 2#21 with 1#11 o5en circuited. 4t can also e

called as o(en circuit re/erse transfer i'(edance and

> is the dri/ing (oint i'(edance at 5ort 2#21 with 1#11 o5en circuited. 4t can also

e called as o(en circuit out(ut i'(edance.

S#5araeter re5resentation for a two 5ort networ7, shown aove, will e as shown elow in fig').

=etwor7 is

a) Reci5rocal then V1@42 'where 41 : () : V2@41 'where 42 : () i.e. S12 : S21

) &yetrical then V1@41 'where 42 : () : V2@42 'where 41 : () i.e. S11 : S22

!*+RT CIRCIT A$MITTA&C" PARAM"T"R! ;,%(ara'eters


13/77

42 : 21 V1 ? 22 V2 UUUUUU. '2)

4n atri for

4f 5ort 2#21 is short circuited, i.e. V2 : ( then 11 : 41@V1 21 : 42@V1

4f 5ort 1#11 is short circuited, i.e. V1 : ( then 12 : 41@V2 22 : 42@V2

Mere, ,11 is the short circuit dri/ing (oint ad'ittance at 5ort 1#11 with 2#21 short circuited. 4t

will also e called as short circuit in(ut ad'ittance.

,1 is the Transfer ad'ittance at 5ort 1#11 with 2#21 short circuited. 4t will also e called as

short circuit forward transfer ad'ittance.

,1 is the Transfer ad'ittance at 5ort 2#21

with 1#11

short circuited. 4t will also e called asshort circuit re/erse transfer ad'ittance and

, is the dri/ing (oint ad'ittance at 5ort 2#21 with 1#11 short circuited. 4t can also e called

as short circuit out(ut ad'ittance.

#5araeter re5resentation for a two 5ort networ7, shown aove, will e as shown elow fig'c).

4f the networ7 is

a) Reci5rocal then 42@V1 'where V2 : () : 41@V2 'where V1 : () i.e. 21 : 12

) &yetrical then 41@ V1 'where V2 : () : 42@ V2 'where V1 : () i.e. 11 : 22

CIRCIT $IA7RAM!:

1!


14/77

8or >%Para'eters:

8or ,%Para'eters:

1*


15/77

T*"+R"TICAL CALCLATI+&!:

PR+C"$R":

1-


16/77

8or >%Para'eters0

1) Connect the circuit as 5er fig.1

2) Kee5 the 5ort 2 terinals 'C$) o5en, then '4 2:().

!) &et desired voltage on V1, etween terinals +"

*) ;easure V2 etween terinal C$ and 41, Then taulate V1, V2, 41.

-) =ow o5en the %ort1.terinals '+"), Connect desired voltage to 5ort 2'C$) terinals, '41:() as

shown in fig.2 then easure V2, V1, 42.

8or ,%Para'eters

1) Connect the circuit as 5er fig.!, connect desired voltage at 5ort1 '+"). Then short 5ort2. 'C$)

=ote the values of 41, 42, V1.

2) Connect any desired voltage at 5ort2. 'C$) and short 5ort1 '+") as shown in fig.*

!) Then note the values of V2, 41 and 42.

TALATI+&:

8or >%(ara'eters: Dhen 42:(

S.No V 1(V) I 1(mA) V 2(V) 11(!) 21(!)12!*

Dhen 41:(

S.No V 1(V) V 2(V) I 2(mA) 12(!) 22(!)12!*

8or ,%(ara'eters:

Dhen V2:(

S.No V 1(V) I 1(mA) I 2(mA) " 11(!) " 21(!)1

1


17/77

2!*

Dhen V1: (

S.No I 1(mA) I 2(mA) V 2(V) " 12(!) " 22(!)12!*

C+&CL!I+&:

11(!)

t#eoretical

11(!)

Practica

l

12(!)

t#eoretical

12(!)

Practica

l

22(!)

t#eoretical

22(!)

Practical

21(!)

t#eoretical

21(!)

Practical

" 11(!)

t#eoretical

" 11(!)

Practical

" 12(!)

t#eoretical

" 12(!)

Practical

" 22(!)

t#eoretical

" 22(!)

Practical

" 21(!)

t#eoretical

" 21(!)

Practical

PR"CATI+&!:%

1. +void loose connections.


!. et your connected circuit chec7ed y staff eer.

R"!LT:%

1


18/77

VIVA #"!TI+&!:

1. Dhat do you ean y a 2#5ort networ7E

2. Dhat are i5edance, adittance and iittanceE

!. Dhat is driving 5oint i5edanceE

*. Dhat is driving 5oint adittanceE

-. Dhat is driving 5oint iittanceE

. Drite e/uations for S#5araeter.


19/77

!. &o. &a'e of the Co'(onent !(ecifications #uantit)

1Two %ort networ7 %araeters

trainer 7it# 1

2 $.R.%.&. '(#!() V 1

! +eters '(#2(()+ 1* Connecting wires &ingle strand Re/uired

T*"+R,:

+ networ7 containing two 5airs of terinals is called as two (ort networ4 . =orally one 5air

of terinals coing together to su55ly 5ower or to withdraw 5ower or to easure the 5araeters, are

called as (ort. To achieve si5licity, the whole networ7 is shown with a single loc7. + ty5ical two

5ort networ7 is as shown elow in fig 'a)

*)@rid Para'eters ;h%Para'eters


20/77

h11 : V1@41 h21 : 42@41

h11 is called in5ut i5edance and h21 is called forward current gain.

4f 5ort 1#11 is o5en circuited, i.e., 41:( then

h12 : V1@V2 h22 : 42@V2

h22 is called out5ut adittance and h12 is called reverse voltage gain.

h#5araeter re5resentation for a two 5ort networ7, shown aove, will e as shown elow fig'd).

AC$ Para'eters:

+"C$ 5araeters can e defined y the following e/uations

V1 : + V2 ? " '#42) UUUUUU. '1)

41 : C V2 ? $ '#42)UUUUUU. '2)

+"C$ 5araeters can e written in atri for as

2(


21/77

4f 5ort 2#21 is o5en circuited i.e., 42:( then + : V1@V2 C : 41@V2

+ is called reverse voltage ratio and C is 7nown as transfer adittance.

4f 5ort 2#21 is short circuited i.e., V2:( then " : V1@ '#42) $ : 41@ '#42)

" is called transfer i5edance and $ is called reverse current ratio.

CIRCIT $IA7RAM!:

8or Trans(ose (ara'eters:

8or h (ara'eters:

21


22/77

T*"+R"TICAL CALCLATI&!:

PR+C"$R":

1. To find + and C %araeters '42 : ()0 Connections are ade as 5er the circuit diagra shown in

fig '1). Fut5ut terinals are 7e5t F5en via a volteter. &u55ly is given to in5ut 5ort. =ote the

readings of aeter as V1 and Volteter as V2.2. To find " and $ %araeters 'V2 : ()0 Connections are ade as 5er the circuit diagra shown in

fig '2). Fut5ut terinals are short circuited via an aeter. &u55ly is given to in5ut 5ort. =ote

the readings of aeters as 41 and V2.

22


23/77

!. To find h11 and h21 'V2 : ()0 Connections are ade as 5er the circuit diagra shown in fig '!).

Fut5ut terinals are short circuited via an aeter. &u55ly is given to in5ut 5ort. =ote the

readings of aeters as 41 and V1.*. To find h12 and h22 '41 : ()0 Connections are ade as 5er the circuit diagra shown in fig

'*).4n5ut terinals current is 3ero. &u55ly is given to in5ut 5ort. =ote the readings of aetersas 41, V1 and 42.

-. +"C$, Myrid 5araeters using forulae and verify the with theoretical values.

TALAR C+LM&!:

8or h%(ara'eters: Dhen V2:(

S.No V 1(V) I 1(mA) I 2(mA) #11 #2112!*

Dhen 41:(

S.No V 1(V) V 2(V) I 2(mA) #12 #2212!*

8or Trans'ission%(ara'eters:

Dhen 42:(

S.No V 1(V) I 1(mA) V 2(V) A C 12!*

Dhen V2:(

S.No V 1(V) I 1(mA) I 2(mA) $ %12

2!


24/77

!*

C+&CL!I+&:

#11

t#eoretical

#11

Practical

#12

t#eoretica

l

#12

Practica

l

#22

t#eoretical

#22

Practical

#21

t#eoretical

#21

Practical

A

t#eoretical

A

Practical

$

t#eoretical

$

Practical

C

t#eoretical

C

Practical

%

t#eoretical

%

Practical

PR"CATI+&!:%

1. +void loose connections.


!. et your connected circuit chec7ed y staff eer.

R"!LT:%

VIVA V+C" #"!TI+&!:

1. Dhat do you ean y a 2#5ort networ7E

2. Dhat are i5edance, adittance and iittanceE

!. Dhat is in5ut i5edanceE

*. Dhat is forward current gainE

2*


25/77

-. Dhat is out5ut adittanceE

. Dhat is reverse voltage gain


26/77

9. V"RI8ICATI+& +8 !P"RP+!ITI+& A&$ R"CIPR+CIT,

T*"+R"M!

AIM0 # To verify &u5er5osition and Reci5rocity theores.APPARAT! R"#IR"$:

S. No. Name o& t#e Com'onent S'eci&ications uantity

1&u5er 5osition Reci5rocity

theores trainer 7it# 1

2 $.R.%.&. '(#!() V 1

! +eters

'(#-() +

'(#2(()+

1

1* Connecting wires &ingle strand Re/uired

T*"+R,: %

2


27/77

I. !u(er(osition Theore' !tate'ent:

B In a linear networ4 with se/eral inde(endent sources which include e=ui/alent sources due to

initial conditions and linear de(endent sources the o/erall res(onse in an) (art of the networ4 is

e=ual to the su' of the indi/idual res(onses due to each inde(endent source consideredse(aratel) with all other inde(endent sources reduced to Dero.E

&ote: 1. the sources which are considered one at a tie a7ing all other sources 3ero, are the

inde5endent sources including sources due to initial conditions only. The de5endent sources are

retained as they are in the networ7.

2. Dhen one inde5endent source is considered all other inde5endent sources are reduced to 3ero

eans that all the other inde5endent voltage source are re5laced with short circuit and all the other

inde5endent current sources are re5laced with o5en circuit. 4f the sources contain internal i5edances,

that sources are re5laced y their internal i5edances.

II. Reci(rocit) Theore' !tate'ent:

BThe Reci(rocit) theore' states that the ratio of res(onse to ecitation is in/ariant to an

interchange of the (osition of the ecitation and res(onse in a single source networ4. *owe/er if

the ecitation is a /oltage source the res(onse should @e a current and /ice /ersa.E

CIRCIT $IA7RAM!0 #

!u(er(osition Theore':

2


28/77

Reci(rocit) Theore'

2H


29/77

PR+C"$R":

!u(er(osition Theore':

1. Connect V1, V2 as shown in Big 1#a.

2. Bor different V1 and V2 values note the $.C. aeter '( X -( +) reading as 648

!. Re5lace WV2’ with a short circuit as shown in Big 1# and read the aeter reading as 6418 for

corres5onding values of V1*. Re5lace 6V18 with a short circuit as shown in Big 1#c and connect 6V28 in the circuit and read

W42’ for corres5onding values of V2.

-. 4 : 41 ? 42.

. Verify the 5ractical values y co5aring theoretical values.

Reci(rocit) Theore':

1. Connect the circuit as shown in Big 1#d.

2. +55ly soe voltage Vs

!. =ote down the aeter '( X 2(( +) reading as 6418

*. 4nter change aeter and voltage source as shown in Big 1#e. and read the aeter reading as

6428

-. Re5eat the aove 5rocedure for different values or Vs and taulate the values.

2I


30/77

. Fserve that whether 41 should e e/ual to 42 or not.


!u(er(osition Theore'

Reci(rocit) Theore'

+!"RVATI+& TAL"!:

;A< !u(er(osition Theore':

S.No

In'ut Voltae I 1 (mA)

*#eoretical

I 2 (mA)

*#eoretical

I(mA)

*#eoretical

I 1 (mA)

Practical

I 2 (mA)

Practical

I (mA)

Practical V 1 (+olts)

V 2

(+olts)

!(


31/77

;< Reci(rocit) Theore'

Bor I1

S.No V IN V (+olts) I 1 (mA)*#eoretical I 1 (mA)Practical

Bor I

S.No. V IN V(+olts) I 2 (mA) *#eoretical I 2 (mA) Practical

PR"CATI+&!:

1. Connect the circuit eleents as 5er the circuit diagra

2. +void loose connections of the circuit eleents

!. Ta7e the readings carefully and accurately

*. $o not ta5er the circuit eleents.

R"!LT:

VIVA V+C" #"!TI+&!:

1. Dhat is linear eleentE

!1


32/77

2. Dhat is a ilateral eleentE

!. Dhat is KCLE

*. Dhat is KVLE

-. Dhat is the difference etween a circuit and a networ7E

. &tate &u5er5osition Theore.


33/77

The aiu 5ower transfer theore states that aiu 5ower is delivered fro a source

i5edance to load resistance when the load resistance is e/ual to the agnitude of the source

i5edance.

!!


34/77

The aiu 5ower transferred when R s :R L is %a : V2th @ *R L.

CIRCIT $IA7RAM:

!*


35/77

PR+C"$R":

1. Connect the circuit as shown in figure ! 'a) and a55ly a constant source voltage of -V .

2. Connect the volteter and aeter as shown in figure.

!. "y changing the load resistance in ste5s and note the aeter and volt eter readings and

calculate 5ower %:VLA4L

*. %lot the gra5h y ta7ing resistance on J X ais and 5ower on X ais

-. Fserve that the aiu 5ower drawn y the load resistor R L should e e/ual to R s.

T*"+RATICAL CALCLATI+&!:

"GP"CT"$ 7RAP*:

!-


36/77

+!"RVATI+&!:

S.No V IN V (+olts) ,oa- Resistance R ,( ) ,oa- Current I , (mA ) ,oa- Poer

P , / I 2 R ,atts

Bor R th or Rs

S.No.

Rt# or Rs

*#eoretical

Rt# or Rs

*#eoretical

PR"ACATI+&!:

1. Connect the circuit eleents as 5er the circuit diagra2. +void loose connections of the circuit eleents

!. Ta7e the readings carefully and accurately

*. $o not ta5er the circuit eleents.

R"!LT:

!


37/77

VIVA V+C" #"!TI+&!:1. &tate ;aiu %ower Transfer Theore.

2. Dhat is 5owerE

!. Dhat is the relationshi5 etween 5ower and energyE

*. Dhat is the difference etween a $C and a +C voltage sourceE

-. Dhat is currentE

. Dhat is voltage or 5otential differenceE


38/77

H.V"R8ICATI+& +8 T*"V"&I&’! &+RT+&’! T*"+R"M!

!H


39/77

AIM: To verify Thevenin’s =orton’s theores for the given circuit.

APPARAT!:

S.No. Name o& t#e Com'onent S'eci&ications uantity

1Thevenin’s =orton’s

theores trainer 7it# 1

2 $.R.%.&. '(#!() V 1

! +eters'(#-() +

'(#2(()+

1

1* Connecting wires &ingle strand Re/uired

T*"+R,:%

I< The/enin’s Theore' !tate'ent:

BAn) co'@ination of linear @ilateral circuit ele'ents and acti/e sources regardless of the

connection or co'(leit) connected to a gi/en load R L 'a) @e re(laced @) a si'(le two

ter'inal networ4 consisting of a single /oltage source of Vth /olts and single resistance Rth in

series with the /oltage source across the two ter'inals of the load R L . The Vth is the o(en circuit

/oltage 'easured at the two ter'inals of interest with load resistance R L re'o/ed. This /oltage

is also called The/enin’s e=ui/alent /oltage. The R th is the The/enin’s e=ui/alent resistance of the

gi/en networ4 as /iewed through the o(en ter'inals with R L re'o/ed and all the acti/e sources

are re(laced @) their internal resistances. If the internal resistances are not

4nown then inde(endent /oltage sources are to @e re(laced @) the short circuit while the

inde(endent current sources 'ust @e re(laced @) o(en circuitE.

!I


40/77

II< &orton’s Theore' !tate'ent:

BAn) co'@ination of linear @ilateral circuit ele'ents and acti/e sources regardless of the

connection or co'(leit) connected to a gi/en load R L can @e re(laced @) a si'(le two ter'inalnetwor4 consisting of a single current source of I& a'(eres and a single resistance R & in (arallel

with it across the two ter'inals of the R L. The I& is the short circuit current flowing through the

short circuited (ath re(laced instead of R L. It is also called &orton’s current. The R & is the

e=ui/alent resistance of the gi/en networ4 as /iewed through the load ter'inals with R L

re'o/ed and all the acti/e sources are re(laced @) their internal resistances. If the internal

resistances are un4nown then the inde(endent /oltage sources 'ust @e re(laced @) short circuit

*(


41/77

while the inde(endent current sources 'ust @e re(laced @) o(en circuitE.

CIRCIT $IA7RAM:

8or The/enin’s Circuit:

To 8ind Vth:

*1


42/77

To 8ind R th:

To find &orton’s Current:

To find &orton’s Resistance:

*2


43/77


PR+C"$R":

8or The/enin’s theore':

1. Connect the circuit as 5er the circuit diagra.

2. +55ly the $C voltage 1(V fro R%&. 'i.e., at +" side)

!. =ote down the Load current 'IL) fro +eter.

*. =ow reove Load Resistor 'R L) connect a Volteter etween C$, and easure the Voltage 'i.e.

Vth)

-. Reove the &u55ly fro A short the terinals.

. +lso reove the volteter, easure the Resistance at C$ with the hel5 of $igital ;ulti ;eter 'i.e.,

R th)

*!


44/77


45/77

S.No. Rt# 0 R N

*#eoretical

Rt# 0 R N

'ractically

8or I&:

S.No

In'ut Voltae

V (+olts)

I N (am's)

*#eoretical

I N (am's)

Practical

I , (am's)

*#eoretical

I , (am's)

Practical

PR"CATI+&!:

1 Reading ust e ta7en without 5aralla error.

2. ;easuring instruents ust e handled 5ro5erly.

!. +ll connections should e free fro loose contactsR"!LT:

VIVA #"!TI+&!:

1. &tate Thevenin’s Theore.2. Dhat is the condition for reci5rocity for a networ7E

!. Dhat is an inde5endent voltage sourceE

*. Dhat is an inde5endent current sourceE

-. $raw the syols of all the de5endent current and voltage sources.

. Dhat is Thevenin’s voltageE

*-


46/77


47/77

J.MagnetiDation Characteristics of a $.C. !hunt 7enerator

AIM: To draw the F.C.C. and to find the critical resistance 'Rc) of a dc shunt generator.

&AM" PLAT" $"TAIL!:

Motor 7enerator

%ower : M% %ower : KD

+rature voltage : volts +rature voltage : volts

+rature current : a5s +rature current : a5s

*


48/77

Bield voltage : volts Bield voltage : volts

Bield current : a5s Bield current : a5s

&5eed : r5 &5eed : r5

APPARAT!:

S.No. Name Rane *y'e uantity

1 $C Volteter '(#!(()V! Y digital 5anel

ount(1

2 $C +eter '(#2)+! Y digital 5anel

ount(1

! Tacho ;eter '(#2((()r5 digital (1

* Rheostats!( Fhs@1.<

a5s# (2

T*"+R,:

MagnetiDation Cur/e:

The gra5h etween the field current and generated voltage in arature when

load is not connected is called the agneti3ation characteristic of the achine. This is sae as "#M

curve of the aterial used for the 5ole construction. 4n a d.c. generator, for any given s5eed, the

induced ef in the arature is directly 5ro5ortional to the flu 5er 5ole.

Gg :.(

ZN φ J

A

P

Dhere Z is the flu 5er 5ole in weers,

S is the no. of conductors in the arature,

= is the s5eed of the shaft in r5.

% is the no. of 5oles and

+ is the no. of 5arallel 5aths.

*H


49/77

+ : 2 'wave) and + : % 'la5)

+(en circuit characteristics0

The arature is driven at a constant s5eed and the field current is increased gradually fro

3ero to its rated value. The terinal voltage 'VL) at no#load condition is easured at different 4 f values.

The gra5h VL [ 4f is called o5en#circuit characteristic. VL differs fro Gg due to 'a) +rature reaction

voltage dro5 in the arature circuit. 4a is very sall at no#load condition so these effects are negligile.

Mence VL : Gg at no#load condition. Thus, the o5en circuit characteristic is sae as agneti3ation

curve.

Critical 8ield Resistance ;R C


50/77

PR+C"$R":

1. Connect the circuit as shown in the fig.

2. &et the otor field rheostat in iniu resistance 5osition and generator field rheostat in

aiu 5osition.

!. &witch on the su55ly and start the otor with the hel5 of the starter. +dust the s5eed of theotor generator set to the rated s5eed y controlling the otor field resistance. The set s5eed is

to e aintained constant throughout the e5erient with the hel5 of otor field rheostat.

*. =ote down the volteter reading at 3ero field current 'lf ). 4ncrease the field current l f uniforly

in ste5s y changing the generator field rheostat u5to rated voltage of generator, siultaneously

note down the field current 'lf ) and terinal voltage 'G) across the generator arature

terinals.

-. Continue the e5erient till saturation of the field is reached.

. $raw the gra5h etween generated voltage'G) Vs field current'4f ), and draw a tangent to

agneti3ation curve fro origin, it will touch the curve at a 5oint which is ta7en as critical

resistance

-(


51/77

+!"RVATI+& TAL":

S.No. I & (am's) (+olts )

M+$"L 7RAP*:

+s shown in the ra5h0F+0 is the voltage induced due to residual agnetis.

"0 Linear region such that Gg \ 4f

C0 saturation region

-1


52/77

PR"CATI+&!:

1. Loose Connections should e avoided.

. Circuit connections should not e a7e while 5ower is F=

2. Readings of the eters ust e ta7en without 5aralla error.

R"!LT:

VIVA V+C" #"!TI+&!:

1. Dhy the s5eed aintained constant during the e5erientE

2. Dhat is residual agnetisE!. $efine critical resistanceE

*. $efine critical s5eedE

-. Mow do you deterine critical resistance with the hel5 of F.C.C.E

. G5lain agneti3ation curveE


53/77

.!-I&R&"’! T"!T

-!


54/77

AIM: To 5re#deterine the efficiency of a $.C. shunt achine considering it as a generator and as a

otor y 5erforing &winurne’s test.

&AM" PLAT"$"TAIL!:

$.C. !hunt Motor

%ower : KD

&5eed : r5

+rature voltage : volts

Bield voltage : volts

+rature current : a5sBield current : a5s

APPARAT! R"#IR"$:

S.No. Name Rane *y'e uantity.

1 $C Volteter '(#!(()V! Y digit 5anel

ounted(2

2 $C +eter '(#2)+! Y digit 5anel

ounted(1

! $C +eter '(#2()+! Y digit 5anel

ounted(1

*Tacho ;eter

'(#2((()r5 $igital (1

-Rheostats

!( Fhs@1.< a5s # (2

T*"+R,:

This is an indirect test and is a55licale only to shunt or co5ound achine where the field

flu is held fairly constant. The achine is run on no#load. The in5ut current, arature current and the

-*


55/77

su55ly voltage are easured while the otor runs at rated s5eed. The arature and field resistance are

deterined with the hel5 of aeter and volt eter ethods.

Losses in a $C 'achine:

The losses in a $.C. achine can e divided as '1) Constant losses '2) Variale losses, which

change with the load.

Constant losses:

Mechanical Losses: Briction and Dindage losses are called echanical losses. They de5end u5on the

s5eed. + dc shunt achine is asically a constant s5eed achine while wor7ing as a generator or

otor. Mence, the echanical losses are constant.

Iron Losses: Bor a dc shunt achine, the field current hence the flu 5er 5ole is constant '=eglecting

the arature reaction which reduces the net flu in the air ga5). Mence, hysteresis and eddy

current losses 'which are also called as iron losses) reain constant.8ield Co((er Losses: Pnder noral o5erating conditions, the field current of a $.C. shunt achine is

reains constant. Thus, 5ower received y the field circuit 'which is consued as field co55er losses)

is constant.

Constant losses in a dc shunt achine:;echanical losses ? 4ron losses ? Bield Cu. Losses.

Varia@le Losses: The 5ower lost in the arature circuit of a dc achine increases with the increase in

load. Thus, the arature co55er losses are called as variale losses.

+rature Co55er loss : 4a2 R a Datts

Dhere 4a is the current in the arature.

!AMPL" CALCLATI+&!:

+rature co55er losses: 4a2 Ra Datts

Biled co55er losses:4sh2R sh Datts

+rature in5ut:Va 4a

;echanical losses ? iron losses : +rature in5ut X +rature co55er losses.

Total constant losses: ';echanical losses ? iron losses) ? field co55er losses

"fficienc) of a 'otor:

Let us assue that the current drawn y the arature : 4a

;achine o5erates as a otor line current 4L : 4a ? 4sh

--


56/77

4n5ut to the otor : in5ut to the arature ? in5ut to the field:V 4 L

Total losses : Total constant losses ? arature co55er losses

Fut5ut : 4n5ut X Total losses

Fut5ut

Gfficiency η : 1((

4n5ut

"fficienc) of a generator:

Let us assue that the current delivered y the arature : 4a

Dhen the achine o5erates as a generator load current 4L : 4a#4sh

Fut5ut %ower :V 4L

Total losses : Total constant losses ? arature co55er losses

4n5ut : Fut5ut ? Total lossesFut5ut

Gfficiency ηg : 1((

4n5ut

CIRCIT $IA7RAM:

PR+C"$R":

-


57/77

1. ;a7e the connections as shown in figure.

2. &et the otor field rheostat in iniu resistance 5osition and arature rheostat in

aiu resistance 5osition.

!. &tart the otor with the hel5 of starter slowly and ring it to rated s5eed y adusting araturerheostat first then field rheostat.

*. Ta7e the no load readings of s5eed, field current, arature current, field voltage and

arature voltage.

-. &et the rheostats to initial 5osition and sto5 the achine.

. ;easure the arature resistance field resistance at +rature and &hunt field winding

res5ectively with the hel5 of aeter volteter ethod.

+!"RVATI+&!:

At no%load ;self ecited dc 'otor


58/77

CALCLATI+&!:

As a 'otor:

S. No. I ,(A) Poer In'ut

VI , (atts)

Co''er ,osses

Ia2 Ra (atts)

*otal ,osses

(atts)

Poer 3ut'ut

(atts)

&&iciency

(4)

1.

2.

!.

*.

-.

As a 7enerator:

S. No. I ,(A) Poer 3ut'ut

V I,(atts)

Co''er ,osses

Ia2 Ra (atts)

*otal ,osses

(atts)

Poer In'ut

(atts)

&&iciency

(4)

1.

2.

!.

*.

-.

C+&CL!I+&:

• The 5ower re/uired to conduct the test is very less as co5ared to the direct loading test.

-H


59/77

• Constant losses are calculated fro this ethod are used to co5ute the efficiency of dc

achine as a generator and as a otor without actually loading it.

• Mence, this is an econoic ethod.

M+$"L 7RAP*0

$raw the gra5h etween efficiency and Fut5ut %ower of the achine as a otor and as a

generator on the sae gra5h sheet.

R"!LT:

VIVA V+C" #"!TI+&! :

1. Dhat are the advantages of &D4="PR=’& testE2. Dhy &D4="PR=’& test cannot 5erfor on series achinesE G5lain.!. Mow do you otain accurate easureents in this e5erientE*. Coent on the accuracy of &D4="PR=]& test over other ethodsE-. Dhy the &D4="PR=’& test is called as indirect testE. Dhat will ha55en in a otor if arature coil is o5enedE


60/77

1) Fut5ut Vs &5eed

2) Fut5ut Vs Tor/ue

!) Fut5ut Vs 4nduced ef

*) Fut5ut Vs Gfficiency

&AM" PLAT" $"TAIL!:

$.C. !hunt Motor:

%ower : KD

+rature voltage : volts

+rature current : a5s

Bield voltage : volts

Bield current : a5s&5eed : r5

APPARAT! R"#IR"$:

S.No. Name Rane *y'e uantity

1 $C Volteter '(#!(()V! Y digit 5anel

ounted(1

2 $C +eter '(#2()+! Y digit 5anel

ounted

(1

! Tacho ;eter '(#2((()r5 $igital (1* Rheostats !( Fhs@1.< a5s # (1

T*"+R,:

+ dc shunt otor rotates due to the tor/ue develo5ed in the arature when the arature and

field terinals are connected to the dc su55ly. The direction of rotation can e e5lained with the

hel5 of Bleing’s left hand 5rinci5le.

+ counter ef or ac7 ef 'G ) is induced in the arature conductors while the arature 'rotor)

rotating in the agnetic field. The direction of the induced ef can e e5lained with the hel5 of

Bleing’s right hand 5rinci5le and Len3’s law. The induced ef is also called as ac7 ef G .

The e/uation of the otor is V: G ? 4a R a Dhere G :.(

ZN φ J

A

P

(


61/77

4a :a

b

R

E V −

The value of G is 3ero while starting the otor. Mence the voltage across the arature has to e

increase gradually.

The 5ower develo5ed in the rotor 'arature) : G 4a : T A Dhere :.(

2 N Π

4n a dc otor T \ Z 4a where Z: Blu 5roduced y the shunt field 5er 5ole

4a : +rature current

The tor/ue develo5ed in the otor is o55osed y the tor/ues due to

'a) Briction and windage

') Gddy currents and hysteresis and

'c) ;echanical load connected at the shaft.

The otor runs at a stale s5eed when the develo5ed tor/ue and resisting tor/ues alance each

other. Let a sall load e increased, and then the resisting tor/ue increases and otor s5eed falls.

The ac7 ef reduces due to the fall in the s5eed. Mence, the arature current increases

'4a :a

b

R

E V −)

4f Z is assued constant, 'i.e. neglecting the arature reaction) the tor/ue develo5ed y the otor

increases and a new stale s5eed is reached at which the develo5ed tor/ue e/uals the resisting

tor/ue.This is a direct ethod of testing a dc achine. 4t is a si5le ethod of easuring otor

out5ut, s5eed and efficiency etc., at different load conditions a ro5e is would round the 5ulley and its

two ends are attached to two s5ring alances &1 and &2. The tensions 5rovided y the s5ring alances &1

and &2 are T1 and T2 the tensions of the ro5e can e adusted with the hel5 of swivels. The force acting

tangentially on the 5ulley is e/ual to the difference etween the readings of the two s5ring alances in

7g# force.

8+RMLA":

The induced voltage G :V#4a R a and

G : KZ=, Thus, KZ:G @=

V: a55lied voltage,

4a :arature current,

1


62/77

R a :arature resistance.

Total 5ower in5ut to the otor %in :Bield circuit 5ower ? +rature 5ower: Vf 4f ? Va 4a

4f WR’ is the radius of the 5ulley, then tor/ue at the 5ulley is given y

Tshaft : I.H1A 'T1[T2 )AR : 1.-A 'T1[T2) =#

:.(

2 N Π is the angular velocity of the 5ulley, in rad@sec.

Radius of 5ulley R : UU..

;otor out5ut 5ower %out :Tshaft A : 1.-A 'T1[T2)A.(

2 N Π

^ Gfficiency :in

out

P

P J 1((

CIRCIT $IA7RAM:

PR+C"$R":

1. Connect the circuit as shown fig.

2. Kee5 the field regulator R sh at iniu resistance value.

!. Chec7 that the elt on the 5ulley is free so that there is no load on the 5ulley.

2


63/77

*. &tart the otor slowly using the starter.

-. +dust the field current y adusting rheostat so that the otor runs at its rated s5eed.

. +55ly load on the 5ulley gradually in ste5s y tightening the elt around it.


64/77

_ : G : V# 4a R a :

K :ω

b E

Model 7ra(hs0Ar'ature Current !(eed characteristics:

The arature current 4a increases with increase in the load at the shaft. Mence 4a R a dro5

increases and counter ef 'G ) decreases.

G : V#4aR a where R a is arature resistance and G \ Z=, if Z is constant in the shunt otor y

neglecting the arature reaction` the s5eed falls as G falls. 4n a dc otor R a is very sall, hence 4a

R a is a sall value and fall in G with increase in load is sall. Thus, the s5eed falls slightly as 4a

increases.Ar'ature current Tor=ue characteristics:

4f Z is constant, develo5ed tor/ue increases with increase in 4a T: KZ 4a

4n actual condition, Z slightly falls withy increase in 4a due to the effect of arature reaction.

Tor=ue !(eed:

Dith increase in load, 4a and Ta increases since the shunt field Z is constant. The fall in s5eed

is very sall as the 4a R a dro5 is very sall co5ared to V. 4n a dc shunt otor = \φ

b E

+ut(ut "fficienc)

The gra5h etween Fut5ut [ Gfficiency indicates that a tor/ue occurs when arature co55er

losses is e/ual to the constant losses.

*


65/77

PR"CATI+&!:

1. Loose connections are to e avoided.

2. $on’t touch the Circuit connections while 5ower is on.

!. Ta7e the eter Readings without 5aralla error.

*. Cool the 5ulley while the e5erient is 5erfored.-. Dhile easuring the radius of the 5ulley effective radius ust e considered.

R"!LT:

VIVA V+C" #"!TI+&!:

1. Dhy the s5eed falls as load increases for a $C shunt otorE2. Dhat are the a55lications of $C shunt otorsE!. Dhen is the efficiency of the otor aiuE*. Dhat will ha55en when $C shunt otor is started with loadE-. ive the e5ressions for various tor/ues in $C otors.. Dhat is the effect on s5eed if 5art of the field winding is shortedE


66/77

APPARAT!:

S.No. Com'onents *y'e S'eci&icationsuantit

y

1 Transforer &ingle %hase 2 KV+ 1 =o.

2 +.C. +eter ! Y digit 5anel

ounted( X 2( + 1 =o.

! +.C.Volteter ! Y digit 5anel

ounted

'(X-(()V

'(X2(()V

1 =o.

each

*L.%.B

Datteter

$ynaoeter

Ty5e

!KD,

1-(@!((@((V

2.-+@-+

1 =o.

- P.%.BDatteter

$ynaoeter Ty5e

!KD,

1-(@!((@((V

-+@1(+

1 =o.

.+uto

Transforer &ingle %hase

2 KV+, 1( +5s,

2!( Volts1 =o.

T*"+R,:

+ Transforer is a static device which transfers the electrical energy fro one circuit to another

circuit with changes in voltages and current ut without any change in the 5ower and fre/uency. The

transforer wor7s on the 5rinci5le of electroagnetic induction etween two windings 5laced on a

coon agnetic circuit. The two windings are electrically insulated fro each other and also fro

the core.

The losses in transforer are agnetic 'iron) losses and co55er 'ohic) losses. These can e

deterined y 5erforing 'a) o5en circuit test and ') short circuit test. Bro the aove tests, the

efficiency and voltage regulation of a given transforer can e 5redeterined at any given load. The

5ower consued during these tests is very sall co5ared to that in a load test.

6LV side 5araeters are denoted y suffi 1 and MV side 5araeters y suffi 28

+(en circuit Test:


67/77

4n the o5en circuit test, MV side is usually 7e5t o5en and su55ly given to the LV side, as shown

in the figure 1'a) when rated voltage is a55lied to the LV side, the aeter reads the no#load current 4 (

is 2 to -^ of full load current. Mence the co55er losses at no#load are negligile. D( re5resents the

iron or core losses. 4ron losses are the su of hysteresis and eddy current losses.

D( : V(4( Cos Φ(

((

(

(

I V

W COS =Φ ,

4 : 4( &in Φ(,

4D : 4( CosΦ(,

R (1 and J(1 is resistance and lea7age reactance referred to LV side.

R (: VLV @ 4w , J( : VLV @ 4

The sae 5araeters, referred to MV side, will ecoeR (2:72R (1 and J(2: 72 J(1`

Dhere 7 : turns ratio : =o. of turns of MV winding @ =o. of turns of LV winding

!hort Circuit Test:

This test is 5erfored to deterine the e/uivalent resistance and lea7age reactance of thetransforer and co55er losses at full#load condition.

4n this test, usually LV side is shorted and eters are connected on MV side. + variale low

voltage is a55lied to the MV winding with the hel5 of an auto#transforer. This voltage is varied till

the rated current flows in the MV side and LV side. The voltage a55lied is - to 1( 5ercentage of rated

voltage, while the rated current flows in the windings. The watteter indicated the full load co55er

losses and core losses at Vsc. "ut the core losses at this low voltage are negligile as co5ared to the

iron losses at the rate voltage.

Mence, Dsc : Bull load co55er losses

: 422 R 2e/: 421 R 1e/

: 422R (2: 421R (1

S(2 : Vsc @ 4sc and

J(2 : O 'S2(2 X R 2(2)


68/77

R e/2 and Je/2 are referred to MV side.

The sae 5araeters, referred to LV side, will e

R (1: '1 @ 72) R (2 and

J(1 : '1 @ 72) J(2

CIRCIT $IA7RAM!:

͂

PR+C"$R":

;a< +.C. Test :

H


69/77

1. Connect the circuit diagra as shown in the figure.1'a)

2. radually increase the voltage y using the auto#transforer till the volteter reads the

rated voltage ' 11-V) of %riary side.

!. Record the volteter, aeter and L.%.B. watteter readings.

*. The Volteter indicates the no#load Voltage, +eter indicates the no#load current and

Datteter indicates the iron losses

-. +fter noting the values slowly decrease the auto#transforer till the Volteter coes to

3ero 5osition, and &witch off the &u55ly.

;@< !.C. Test :

1. Connect the circuit diagra as shown in the figure1 ').

2. radually increase the auto#transforer till the aeter reads the rated current

'H.+5s) of the transforer on MV side.2 Record the volteter, aeter and P.%.B. watteter readings. The aeter indicates

Bull load Current, Volteter indicates &.C Voltage and watteter indicates co55er

losses of the transforer at full load condition

? +fter noting the values slowly decrease the auto#transforer till the +eter coes to

3ero 5osition and &witch off the su55ly.

+!"RVATI+&!:

+.C. Test:

V 3(Volts) I 3 (Am's) 3 (atts)

!.C. Test:

V SC (Volts) I SC (Am's) SC (atts)

I


70/77

;a< Calculation of "=ui/alent circuit (ara'eters:

Let the transforer e the ste5#u5 transforer

%riary is L. V. side.'V1) , &econdary is M. V. side 'V2)

'i) %araeters calculation fro FC test

cos φ( :oo

o

I V

W

4w : 4( cos φ( 'referred to 5riary) K I I ww @1= 'referred to secondary)

w I

V R

1

( = 'referred to 5riary) 2(1( K R R = 'referred to secondary)

4b : 4( sin φ( 'referred to 5riary) K I I @

1

µ µ =

'referred to secondary)

µ I

V X

1

( = 'referred to 5riary) 2(1( K X X = 'referred to secondary)

K :1

2

V

V

'ii) %araeters calculation fro &C test

2(2

sc

SC

I

W

R =

SC SC

I

V Z =

(2 2

(2

2

(2(2 R Z X −=

2

(2(1 @ K X X = 2(2(1 @ K R R =

2

(2(1 @ K Z Z =

;@< Calculations to find efficienc):

Bor W’ fraction of full load

Cu55er losses : Dsc A ') 2 watts

Bor Y full load

Cu55er losses : Dsc A '1@2)2 watts

Dhere Dsc : full load co55er losses

Constant losses : D( watts

Fut5ut : Y KV+ A cos φ cos φ is 5ower factor ay e assued


71/77

4n5ut : out5ut ? Cu. Loss ? constant loss

^ 1(( x Input

Output efficiency =

;a< Calculation of Regulation at full load:

42 : Load 'KV+) J 1((( @ V2

1((sincos

Re^

2

(22(22 xV

X I R I gulation

φ φ ±=

W?’ for lagging 5ower factors ` W#Wfor leading 5ower factors

M+$"L 7RAP*!:

Gfficiency Vs Fut5ut %ower Regulation Vs %ower factor


72/77

PR"CATI+&!:

1 +void loose connections.

2 $on’t touch the circuit connections while 5ower is on.

. Ta7e the eter readings without 5aralla error.


73/77

1.Load Test on a !ingle Phase Transfor'er

AIM: To deterine the efficiency and voltage regulation of a single %hase Transforer y direct

a55lying of different loads on secondary side of transforer.

APPARAT! R"#IR"$:

S.No. qui'ments *y'e 0 S'eci&ications uantity

1 Transforer 1# ϕ ,2 KV+ 1 =o.

2 +.C. +eter $igital '( X 2() + 1 =o.! +.C.Volteter $igital '(X-(()V 2 =o’s* L.%.B

Datteter $ynaoeter Ty5e,!KD, 1-(@!((@((V

2.-+@-+

1 =o.

- P.%.B Datteter $ynaoeter Ty5e,!KD, 1-(@!((@((V

1 =o.


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-+@1(+. +uto Transforer 1#ϕ,1( +5s,2!( Volts 1 =o.

&AM" PLAT" $"TAIL!0

%ower : KV+L.V &ide Voltage : Volts

M.V &ide Voltage : Volts

L.V &ide current : +5s

M.V &ide current : +5s

Bre/uency : M3

T*"+R,:

+ Transforer is a static device which transfers the electrical energy fro one circuit to

another circuit with changes in voltages and current ut without any change in the fre/uency. The

transforer wor7s on the 5rinci5le of electroagnetic induction etween two windings 5laced on a

coon agnetic circuit. The two windings are electrically insulated fro each other and also

fro the core.

Various easureents are ade y connecting different loads directly on the transforer

and to deterine the efficiency and regulation of transforer at different load conditions. Psually,

this test is 5erfored for low 5ower rating transforer since load is directly a55lied, a55roiating

no assu5tions are needed accuracy of the results is liited only y the accuracy of the

easureents.

Dhen the secondary is loaded the secondary current 42 is setu5. The agnitude and 5hase of 42

with res5ect to V2 is deterined y the characteristics of the load. The secondary current sets u5 its

own f and hence its own flu 2 which is in o55osition to ain 5riary flu which is due to 4(

the secondary a5ere turns =2A42 are 7nown as deagneti3ing a5ere turns .The o55osing secondary

flu 42 wea7ens the 5riary flu Z oentary. Mence 5riary ac7 Gf G1 tends to e reduced. Bor a

oveent V1 gain the u55er hand over G1 and hence causes ore current to flow in 5riary.


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Let the additional 5riary current e 421 .4t is 7nown as load co5onent of 5riary current. This

current is anti 5hase with 421 the additional 5riary f =1A42 sets u5 its own flu Z21 which is in

o55osite to Z2 and is e/ual to its agnitude. Mence the two cancel each other out. &o the agnetic

effects of secondary current 42 are iediately neutrali3ed y the additional 5riary current 421.Mence

whatever the load conditions e, the net flu 5assing through core is a55roiately the sae as no#

load.

CIRCIT $IA7RAM:


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PR+C"$R":

1) Connect the circuit diagra such that the su55ly on LV side and load on MV side as shown the

figure.

2) radually increase the voltage using auto#transforer till the volteter reads the rated voltage

2!(V, on LV side and also record the voltage on MV side.

!) ;aintain the voltage V1 to e constant for all loads.

*) &witch on the load switches one y one record the aeter, volteter and watteter’s

readings. ' the load current should not eceed the rated current, *.H +)

-) +fter noting the values, gradually decrease the load and set the +uto#Transforer 3ero voltage

5osition and &witch off the su55ly.

+@ser/ations for Load TestN La'( load ;(urel) resisti/e<

V1 5 26 V ;Constant<

S.N Primary Secon-ary

4 4 Re.

V 1 (V) I 1 (A) 1(;) V 2(V) I 2(A) 2(;)

^ Gfficiency _ : Fut5ut 5ower J 1((

4n5ut 5ower


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^ Regulation : 'G( X V) J 1((

V

M+$"L 7RAP*!:

Gfficiency Vs Fut5ut %ower Regulation Vs %ower factor

PR"CATI+&!:

1 +void loose connections.

2 $on’t touch the circuit connections while 5ower is on.

! Ta7e the eter readings without 5aralla error.

* Voltage is to e varied gradually till rated current flows.

- Gnsure that the setting of the variac is at 3ero out5ut voltage during starting

R"!LT0

Documents

PEE LAB MANUAL.doc