PDP8/I to OMNIBUS (Subset) Interface for RX808-85/01-04/Rev.01 vk6bqd Page 1 PDP8/I to OMNIBUS (Subset) Interface for RX8 Diagrams for an Implementation on a TC08 Backplane Original

08-85/01-04/Rev.01 vk6bqd Page 1

PDP8/I to OMNIBUS (Subset)Interface for RX8

Diagrams for an Implementation on a TC08 BackplaneOriginal Design (pages 2 to 9) 1985 by Ulrich N. Fierz, reviewed 2004

08-85/01-04/Rev.01 vk6bqd Page 2

Data (1) Signals for 8/I to OMNIBUS Subset

C1

C21U1

D20B1

A1D21

D1

C22 B1A1

A1D22/D2

AR1

DATA00 (L) AC00 (L)

D02/B1BAC00 (H)

C1 BRD (L)

C20P2

BWR (L)

C20J2

D20E1

D1D21

E1

C22 E1D1

B1D22/E2

AS1

DATA01 (L) AC01 (L)

D02/D1BAC01 (H)

D20H1

F1D21

K1

C22 H1F1

F1D22/F2

AU1

DATA02 (L) AC02 (L)

D02/E1BAC02 (H)

D20K1

J1D21

L1

C22 K1J1

H1D22/H2

AV1

DATA03 (L) AC03 (L)

D02/H1BAC03 (H)

D20M1

L1D21

R1

C22 M1L1

M1D22/J2

BR1

DATA04 (L) AC04 (L)

D02/J1BAC04 (H)

D20P1

N1D21

S1

C22 P1N1

N1D22/K2

BS1

DATA05 (L) AC05 (L)

D02/L1BAC05 (H)

C1

J1

P1

D04/B1

D04/D1

D04/E1

D04/H1

D04/J1

D04/L1

Cab

le 0

2 to

8/I

Cab

le 0

4 to

8/I

Modules: D20 : M101, D21 : M623, C22 : M624XX OMNIBUS Signal

08-85/01-04/Rev.01 vk6bqd Page 3

Data (2) Signals for 8/I to OMNIBUS Subset

D20S1

R1D21

H2

C22 S1R1

D2D22/L2

BU1

DATA06 (L) AC06 (L)

D02/M1BAC06 (H)

D20U1

V1D21

J2

C22 U1V1

E2D22/M2

BV1

DATA07 (L) AC07 (L)

D02/P1BAC07 (H)

D20F2

E2D21

N2

C22 F2E2

K2D22/N2

DR1

DATA08 (L) AC08 (L)

D02/S1BAC08 (H)

D20J2

H2D21

P2

C22 J2H2

L2D22/P2

DS1

DATA09 (L) AC09 (L)

D02/D2BAC09 (H)

D20L2

K2D21

U2

C22 L2K2

R2D22/R2

DU1

DATA10 (L) AC10 (L)

D02/E2BAC10 (H)

D20N2

M2D21

V2

C22 N2M2

S2D22/S2

DV1

DATA11 (L) AC11 (L)

D02/H2BAC11 (H)

F2

M2

T2

D04/M1

D04/P1

D04/S1

D04/D2

D04/E2

D04/H2

Cab

le 0

2 to

8/I

Cab

le 0

4 to

8/I

Modules: D20 : M101, D21 : M623, C22 : M624

XX OMNIBUS Signal

08-85/01-04/Rev.01 vk6bqd Page 4

Adress & Control (1) Signals for 8/I to OMNIBUS Subset

D03/H1 AP1BMB03 (L) MD03 (L)

D03/L1 BK1BMB04 (L) MD04 (L)

D03/P1 BL1BMB05 (L) MD05 (L)

D03/D2 BM1BMB06 (L) MD06 (L)

D03/H2 BP1BMB07 (L) MD07 (L)

D03/M2 DK1BMB08 (L) MD08 (L)

C20E1A1D03/S2 DL1

BMB09 (H) MD09 (L)

C20L1F1D03/T2 DM1

BMB10 (H) MD10 (L)

D03/V2 DP1BMB11 (H) MD11 (L)C20

S1M1

Jum

pers

:C

20 :

unus

ed in

puts

to U

1C

22 :

D2

to G

ND

(C2)

C22R2

P2

Cab

les

02 -

04 to

8/I

C22T2

S2

D02/V2 CR1BINIT (H) INITIALIZE (H)

D04/M2

D04/K2

INT RQST (L)

SKIP BUS (L)CP1

CS1SKIP (L)

INT RQST (L)

Mod

ules

:C

20 :

M61

7C

22 :

M62

4C

32 :

M00

2

C32/K2

C32/L2D2

GND C22/C2

XX

OM

NIB

US

Sig

nal

08-85/01-04/Rev.01 vk6bqd Page 5

F9D2

D32D2

E9

E17J1

TP3 (H) D31

C30H2A1 B1E1A1

C32 D2TP3 (H)

F9E2

D32E2

E9

E15F2

TP4 (H) D31CJ2

D1 E1L1F1

C32 E2TP4 (H)

F9H2

D32H2

E9

E18M1

I/O PAUSE (L) D31

D31J1F1 H1S1M1

C32 F2I/O PAUSE (L)

F9K2

D32K2

E9

F12F1

I/O STROBE (H) D31

D31J1L1 M1J2D2

C32 N2

I/O STROBE (H)(used as TP3**)

PDP8/I TC08

new

rib

bon

cabl

e

Jumpers:E9 : B1,C1,D1,H1,J1,K1,N1,P1,R1 to U1F9/D32 : GND to C2, F2, J2

Modules:E9 : M617 (in 8/I)D31 : M101C32 : M002

Control (2) Signals for 8/I to OMNIBUS Subset (new ribbon cable)

C32 H2

C1 ENABLE

XX OMNIBUS Signal

Note: Two empty slots in 8/I used: E9 and F9

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C22CE1 AC CLEAR (L)

A04P2

V2

J2

Control (3) Signals for 8/I to OMNIBUS Subset

Modules:C20 : M617C21 : M113C22 : M624C32 : M002D22 : M002

U2F2C21C21 F1

E2

D1

D22T2

C0 (L)

C20F2

D2

BWR (L)

D21C1

C1 (L)

M2

K2

C20C21

P2BRD (L)

C22C1

CH1

D22U2

A1C1

C21

D2

C31F2

I/O PAUSE** (L)

H1K1

J1

E1

B1

Jumpers:C20 : unused inputs to U1C21 : unused inputs to U1

BV2

C32M2

POWER OK (H)

XX OMNIBUS Signal

Cab

le 0

4 to

8/I

08-85/01-04/Rev.01 vk6bqd Page 7

C31

C31

C31

C31 C31

CD1I/O PAUSE** (L)

F2D2

E2F1

C1A1

B1

D1

E1

K1 K2

D31K1

D31H1

I/O PAUSE (L)

J1 J2

D31M1

I/O STROBE (H)(used as TP3**)

TP3** (H)

CH2

C31 C31L1N1

L2N2+50ns

C30+400nsT2 E1 F1C30

D31B1

TP3 (H)

H2

Timing (1) Signals for 8/I to OMNIBUS Subset

Modules:C30 : M310C31 : M113D31 : M101

M2

J1

pro memoria: C1

XX OMNIBUS Signal

Jumpers:C31 : unused inputs to U1

Del

ay L

ine

I/O PAUSE** FF

H1 H2

08-85/01-04/Rev.01 vk6bqd Page 8

Timing (2) Signals for 8/I to OMNIBUS Subset

450ns

400ns

800ns

100ns

Shortening of original 8/I pulse

as in

8/ETP3** (H)

I/O PAUSE** (L)

TP3 8/I (H)

I/O STROBE 8/I (H)6xx1!

Notes: C0, C1 are gating DATA BUS [BWR (L), BRD (L)] and AC CLEAR, all are basically gated by I/O PAUSE**

[this is the delayed and shortened I/O PAUSE from 8/I]. Most initial problems were caused by TP3** timing. Now this works as follows:

I/O PAUSE** starts approx. 400ns after TP3 8/I [I/O PAUSE** FF] and lasts until the first I/O STROBE pulse8/I occurs [depends on 6xx1 to 6xx4] + approx. 50ns. This allows for TP3** = I/O STROBE to pulse theperipheral just before I/O PAUSE** [and possibly BAC bus data] change state.

TP4 is used as is. BIOP’s [and therefore BMB00 to BMB02] are not used anywhere. OMNIBUS lines intended to drive one or two peripheral cards only, no bus and no cables. No DATA BREAK implemented.

08-85/01-04/Rev.01 vk6bqd Page 9

Module Usage for 8/I to OMNIBUS Subset on TC08

01 02 03 04 05 32313029282726252423222120

A

B

C

D

Cab

le 0

2C

able

02

Cab

le 0

3C

able

03

Cab

le 0

4C

able

04

M61

7M

101

M11

3M

623

M62

4M

002

M00

2N

ew C

able

M11

3M

310

M10

1

OM

NIB

US

Subs

et M

8357

View on wire wrap pins of backplane, all TC08 modules not shown

08-85/01-04/Rev.01 vk6bqd Page 10

Annex: M Modules used (1)

This information copied from “digital logic landbook 1973-74” C 1973

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Documents

PDP8/I to OMNIBUS (Subset) Interface for RX808-85/01-04/Rev.01 vk6bqd Page 1 PDP8/I to OMNIBUS (Subset) Interface for RX8 Diagrams for an Implementation on a TC08 Backplane Original