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Chapter
CombinationalCircuits
10
Microcode
level
Logic gate
level
Electronic device
level
Physics
level
2
1
0
–1
Figure 10.1
Combinational circuit• The output depends only on the input
a
b
c
x
y
In Out
Figure 10.2
Methods to describe a combinational circuit
• Truth table
• Boolean algebraic expression
• Logic diagram
Truth table• Lists the output for every combination of
the input
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
a
0
0
0
0
1
1
1
1
y
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
x
Figure 10.3
a
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
c
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
x
Figure 10.4
Boolean algebra• Three basic operations
‣ Binary OR +
‣ Binary AND •
‣ Unary Complement ´
Ten properties of boolean algebra
• Commutative
• Associative
• Distributive
• Identity
• Complement
CommutativeCOMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Associative
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Distributive
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Identity
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Complement
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Precedence
Highest
Lowest
Operator
Complement
AND
OR
Figure 10.5
Distributive
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Complement
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Associativity
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Duality• To obtain the dual expression
‣ Exchange + and •
‣ Exchange 1 and 0
Idempotent property
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Zero theorem
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Absorption property
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Consensus theorem
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
De Morgan’s law
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b)′ = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Complement theorems
COMPUTER SYSTEMS CHAPTER 10
x + y = y + x(1)
x · y = y · x(2)
(x + y) + z = x + (y + z)(3)
(x · y) · z = x · (y · z)(4)
x + (y · z) = (x + y) · (x + z)(5)
x · (y + z) = (x · y) + (x · z)(6)
x + 0 = x(7)
x · 1 = x(8)
x + (x′) = 1(9)
x · (x′) = 0(10)
x + y · z = (x + y) · (x + z)(11)
x · (y + z) = x · y + x · z(12)
x + x′ = 1(13)
x · x′ = 0(14)
(x + y) + z(15)
x + y + z(16)
x + x = x(17)
x · x = x(18)
x + 1 = 1(19)
x · 0 = 0(20)
x + x · y = x(21)
x · (x + y) = x(22)
x · y + x′ · z + y · z = x · y + x′ · z(23)
(x + y) · (x′ + z) · (y + z) = (x + y) · (x′ + z)(24)
(a · b′) = a′ + b′(25)
(a + b)′ = a′ · b′(26)
(x′)′ = x(27)
1′ = 0(28)
0′ = 1(29)
1
Logic diagrams• An interconnection of logic gates
• Closely resembles the hardware
‣ Gate symbol represents a group of transistors and other electronic components
‣ Lines connecting gate symbols represent wires
a
0
0
1
1
b
0
1
0
1
0
0
0
1
x
(a) AND gate.
x = a . b
a
0
0
1
1
b
0
1
0
1
0
1
1
1
x
(b) OR gate.
x = a + b
a
0
1
1
0
x
(c) Inverter.
x = a
a
b
x
a
b
x
a x
Figure 10.6
a
0
0
1
1
b
0
1
0
1
1
1
1
0
x
(a) NAND gate.
x = (a . b)
a
0
0
1
1
b
0
1
0
1
1
0
0
0
x a
0
0
1
1
b
0
1
0
1
0
1
1
0
x
(b) NOR gate.
x = (a + b)
(c) XOR gate.
x = a b
a
b
x
a
b
x
a
b
x
Figure 10.7
AND inverter. NAND.
x x
( )a ( )b
a
b
a
b
Figure 10.8
Figure 10.9
Precedence
Highest
Lowest
Operator
Complement
AND
XOR
OR
Figure 10.9
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
x
0
0
0
0
0
0
0
1
a
b
c
x = a b c
x
Figure 10.10
Set theory representation
• OR gate is set union
• AND gate is set intersection
• Inverter is set complement
x
x y x y
x y
(a) x (b) x · y
(c) x + x · y
Figure 10.11
Truth table
Boolean expression
Logic diagram
Boolean expression
Logic diagram
Boolean expression
Logic diagram
One-to-one
correspondence
Figure 10.12
Boolean expressions and logic diagrams
• AND gate corresponds to AND operation
• OR gate corresponds to OR operation
• Inverter corresponds to complement operation
a
b
c
b
b c
a + b . c
Figure 10.13
ab bc( + )ab bc a
aba
b
c
b
bc
ab + bc
c
a
(( + a ) )
Figure 10.14
Abbreviated logic diagrams
• Any signal can be duplicated by a junction of two wires
• The complement of any variable can be produced by an inverter
a
b
b
c
a
Figure 10.15
a
d
a
b
c
c
Figure 10.16
2
(a′bc⊕ c + a + d)′
Truth tables and boolean expressions
• Given a truth table, write a boolean expression without parentheses as an OR of several AND terms
• Each AND term corresponds to a 1 in the truth table
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
x
1
1
1
0
1
1
0
1
Figure 10.17
a
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
c
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
Figure 10.18
Two-level circuits• The gate delay is the time is the time it takes
for the output of a gate to respond to a change in its input
• Any combinational circuit can be transformed into an AND-OR circuit or an OR-AND circuit with at most two gate delays (not counting the gate delay of any inverters)
a
b
d
a
c
d
Figure 10.19
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
a
b
c
a
b
c
Figure 10.20
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
AND-OR versusOR-AND
• To transform any expression x to an equivalent OR-AND expression
‣ Transform the complement of x to an AND-OR expression without parentheses using boolean algebra theorems
‣ Use x = (x´)´ and De Morgan’s law
A NOR gate as an inverted
input AND gate.
a
b
c
a
b
c
a
b
c
a
b
c
( )a A NAND gate as an inverted
input OR gate.
( )b
Figure 10.21
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
abc + def = [(abc)′(def)′]
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
The same NAND-NAND circuit
as in part (b).
The equivalent NAND-NAND circuit.( )a An AND-OR circuit.
a
b
c
d
e
f
( )b
a
b
c
d
e
f
( )c
a
b
c
d
e
f
Figure 10.22
The same NAND-NAND circuit
as in part (b).
The equivalent NAND-NAND circuit.( )a An AND-OR circuit.
a
b
c
d
e
f
( )b
a
b
c
d
e
f
( )c
a
b
c
d
e
f
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
a
a
a
Figure 10.23
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a′) = a′
(a + b + c) = [(a + b + c)(d + e + f)]
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c) = [(a + b + c)(d + e + f)]
Figure 10.24
(a) An OR-AND circuit. (b) The equivalent
NOR-NOR circuit.
(c) The same NOR-NOR
circuit as in part (b).
a
b
c
d
e
f
a
b
c
d
e
f
a
b
c
d
e
f
Figure 10.24
Figure 10.24
(a) An OR-AND circuit. (b) The equivalent
NOR-NOR circuit.
(c) The same NOR-NOR
circuit as in part (b).
a
b
c
d
e
f
a
b
c
d
e
f
a
b
c
d
e
f
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
Canonical expressions• A minterm is a term in an AND-OR
expression in which all input variables occur exactly once
• A canonical expression is an OR of minterms in which no two identical minterms appear
• A canonical expression is directly related to a truth table because each minterm in the expression represents a 1 in the truth table
x
0
0
0
1
0
0
1
1
c
0
1
0
1
0
1
0
1
b
0
0
1
1
0
0
1
1
a
0
0
0
0
1
1
1
1
Row
(dec)
0
1
2
3
4
5
6
7
Figure 10.25
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)x
0
0
0
1
0
0
1
1
c
0
1
0
1
0
1
0
1
b
0
0
1
1
0
0
1
1
a
0
0
0
0
1
1
1
1
Row
(dec)
0
1
2
3
4
5
6
7
Figure 10.25
Karnaugh maps• The distance between two minterms is the
number of places in which they differ
• Two minterms are adjacent if the distance between them is one
• A Karnaugh map is a truth table arranged so that adjacent cells represent adjacent minterms
Figure 10.26
(a) The Karnaugh map. (b) The b = 1 region. (c) The c = 0 region.
bc
a
0
1
00 01 11 10
bc
00 01
bc
01 1111 10 00 10
Figure 10.26
Figure 10.26
(a) The Karnaugh map. (b) The b = 1 region. (c) The c = 0 region.
bc
a
0
1
00 01 11 10
bc
00 01
bc
01 1111 10 00 10
Figure 10.27
(a) The Karnaugh map. (b) The minimization.
bc
a
0
1
a
0
1
0
0
0
0
1
0
1
0
00 01 11 10
bc
00 01 11 10
1 1
Figure 10.27
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
Figure 10.28
(a) The Karnaugh map. (b) Region a. (c) Region c .
bc
a
a
0
1 1
00 01 11 10
c
1
Figure 10.28
Figure 10.28
(a) The Karnaugh map. (b) Region a. (c) Region c .
bc
a
a
0
1 1
00 01 11 10
c
1
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
x(a, b, c) = ab′c′ + abc′(30)
= ac′(31)
Figure 10.29
(a) a bc + abc = bc (b) abc + abc = ab (c) x = bc + ab
bc
aa
0
1 11
1
00 01 11 10
c
b
11
11
1 1
Figure 10.29
Figure 10.29
(a) a bc + abc = bc (b) abc + abc = ab (c) x = bc + ab
bc
aa
0
1 11
1
00 01 11 10
c
b
11
11
1 1
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
x(a, b, c) = ab′c′ + abc′(30)
= ac′(31)
x(a, b, c) = a′bc + abc + abc′(32)
= bc + ab(33)
Figure 10.30
bc
a
0
1
0
4
1
5
3
7
2
6
00 01 11 10
Figure 10.30
Figure 10.31
(a) A bad strategy. (b) The result of the bad
strategy.
(c) The correct minimization.
bcb
a
0
1 1
00 01 11 10
1
1 1
1 1
1 1
1 1
1 1
1
c
a
Figure 10.31
Figure 10.31
(a) A bad strategy. (b) The result of the bad
strategy.
(c) The correct minimization.
bcb
a
0
1 1
00 01 11 10
1
1 1
1 1
1 1
1 1
1 1
1
c
a
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
x(a, b, c) = ab′c′ + abc′(30)
= ac′(31)
x(a, b, c) = a′bc + abc + abc′(32)
= bc + ab(33)
x(a, b, c) = Σ(0, 1, 5, 7)(34)
= a′b′ + ac(35)
(a) An incorrect minimization. (b) The correct minimization.
cd
a
0
1
00 01 11 10
1 1 1
1
c
a
b
11
11
1
1
Figure 10.32
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
x(a, b, c) = ab′c′ + abc′(30)
= ac′(31)
x(a, b, c) = a′bc + abc + abc′(32)
= bc + ab(33)
x(a, b, c) = Σ(0, 1, 5, 7)(34)
= a′b′ + ac(35)
x(a, b, c) = Σ(0, 2, 4, 6, 7)(36)
= b′c′ + bc′ + ab(37)
x(a, b, c) = Σ(0, 2, 4, 6, 7)(38)
= c′ + ab(39)
2
(a′bc⊕ c + a + d)′
a′bd′ + a′c′d′
(a + b′ + c′)(a′ + b′ + c)
(abc)′ = a′ + b′ + c′
(a + b + c)′ = a′b′c′
abc + def = [(abc)′(def)′]
(a · a)′ = a′
(a + a)′ = a′
(a + b + c)(d + e + f) = [(a + b + c)′ + (d + e + f)′]′
x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5)
x(a, b, c) = a′bc + a′bc′
x(a, b, c) = a′b
x(a, b, c) = ab′c′ + abc′(30)
= ac′(31)
x(a, b, c) = a′bc + abc + abc′(32)
= bc + ab(33)
x(a, b, c) = Σ(0, 1, 5, 7)(34)
= a′b′ + ac(35)
x(a, b, c) = Σ(0, 2, 4, 6, 7)(36)
= b′c′ + bc′ + ab(37)
x(a, b, c) = Σ(0, 2, 4, 6, 7)(38)
= c′ + ab(39)
00 01 11 10
cd
00
01
ab
(b) The regions where the
variables are 1.
d
a
c
(a) Decimal labels for the
minterms in the Karnaugh map.
1 3 2
4
12
8
5
13
9
7
15
11
6
14
10
11
10
b
0
Figure 10.33
Figure 10.34
ab
00
01
11
10
cd
00 01 11 10
1
11 1
1
11 1
Figure 10.343
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
Figure 10.35
ab
00
01
11
10
cd
00 01 11 10
1
11 1
11 1
Figure 10.35
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
Figure 10.36
cd
ab
00
01
11
10
00 01 11 10
1
1
1
1
1 1
1
1
d
a
c
b
1
1
1
1 1
1
( )a One possible minimization. A different minimization.( )b
Figure 10.36
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
Figure 10.37
1
1
1
1
1 1
1
1
d
a
ab
cdc
b
1
1
1
1
1
( )a A plausible but incorrect
minimization.
A correct minimization.( )b
1 1 1
00 01 11 10
1
1
11
01
00
10
1 1 1
1
1
1
Figure 10.37
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
Figure 10.38
cd
ab
00
01
11
10
00 01 11 10
1
1
1
1
1 1
1
1 1 1
1
1
Figure 10.38
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
a′c + b′c′ + c′d + abd′
Dual Karnaugh maps• To minimize a function in an OR-AND
expression minimize the complement of the function in the AND-OR expression
• Use x = (x´)´ and De Morgan’s law
Figure 10.29
bc
a
0
1
00 01 11 10
1
11
1 1
Figure 10.29(c), 10.39
Figure 10.29
(a) a bc + abc = bc (b) abc + abc = ab (c) x = bc + ab
bc
aa
0
1 11
1
00 01 11 10
c
b
11
11
1 1
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
a′c + b′c′ + c′d + abd′
x = bc + ab
x′ = b′ + a′c′(40)
x = (x′)′(41)
= (b′ + a′c′)′(42)
= b(a + c)(43)
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
a′c + b′c′ + c′d + abd′
x = bc + ab
x′ = b′ + a′c′(40)
x = (x′)′(41)
= (b′ + a′c′)′(42)
= b(a + c)(43)
Don’t-care conditions• If an input combination is never expected to
be present, you can choose to make it 0 or 1, whichever will better minimize the circuit
• A don’t care condition is shown as an X in a Karnaugh map
Figure 10.40
a
0
1
bc
00 01 11 10
Minimizing a function
without don’t-care conditions.
Minimizing the same
function with don’t-care
conditions.
1
1
c
a
b
1
1
11
( )a ( )b
Figure 10.40
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
a′c + b′c′ + c′d + abd′
x = bc + ab
x′ = b′ + a′c′(40)
x = (x′)′(41)
= (b′ + a′c′)′(42)
= b(a + c)(43)
x(a, b, c) = Σ(2, 4, 6)(44)
= bc′ + ac′(45)
x(a, b, c) = Σ(2, 4, 6) + d(0, 7)(46)
= c′(47)
3
x(a, b, c) = c′d + b′d′
x(a, b, c, d) = a′c′d + b′c′ + b′d′
x(a, b, c, d) = c′d′ + bcd + abc′
x(a, b, c, d) = c′d′ + bcd + abd
ac′ + a′c + c′d + a′b′ + bcd′
ac′ + a′d + a′b′ + bcd′
a′c + b′c′ + c′d + abd′
x = bc + ab
x′ = b′ + a′c′(40)
x = (x′)′(41)
= (b′ + a′c′)′(42)
= b(a + c)(43)
x(a, b, c) = Σ(2, 4, 6)(44)
= bc′ + ac′(45)
x(a, b, c) = Σ(2, 4, 6) + d(0, 7)(46)
= c′(47)
Enable lines• An enable line to a combinational device
turns the device on or off
‣ If enable = 0 the output is 0 regardless of any other inputs
‣ If enable = 1 the device performs its function with the output depending on the other inputs
a
x
Logic diagram of
enable gate.
( )a
Enable
a
0
1
Enable = 1
0
1
x
(b) Truth table with the device
turned on.
a
0
1
0
0
x
(c) Truth table with the device
turned off.
Enable = 0
Figure 10.41
a
x
Logic diagram of
enable gate.
( )a
Enable
a
0
1
Enable = 1
0
1
x
(b) Truth table with the device
turned on.
a
0
1
0
0
x
(c) Truth table with the device
turned off.
Enable = 0
a
0
1
Invert = 1
1
0
x
(b) Truth table with the inverter
turned on.
a
0
1
0
1
x
(c) Truth table with the inverter
turned off.
Invert = 0
(a) Logic diagram of the
selective inverter.
Invert
a
x
Figure 10.42
a
0
1
Invert = 1
1
0
x
(b) Truth table with the inverter
turned on.
a
0
1
0
1
x
(c) Truth table with the inverter
turned off.
Invert = 0
(a) Logic diagram of the
selective inverter.
Invert
a
x
Multiplexer• A multiplexer selects one of several data
inputs to be routed to a single data output
• Control lines determine the particular data input to be passed through
(b) !!Truth table.
F
D0
D1
D2
D3
D4
D5
D6
D7
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
D0
D1
D2
D3
D4
D5
D6
D7
F
S2 S1 S0
( )a Block diagram.
Figure 10.43
(b) !!Truth table.
F
D0
D1
D2
D3
D4
D5
D6
D7
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
D0
D1
D2
D3
D4
D5
D6
D7
F
S2 S1 S0
( )a Block diagram.
D
S
S
D
S
S
D
S
S
D
S
S
F
0
0
0
0
0
1
1
1
2
1
3
1
Figure 10.44
Binary decoder• A decoder takes a binary number as input
and sets one of the data output lines to 1 and the rest to 0
• The data line that is set to 1 depends on the value of the binary number that is input
D3
0
0
0
1
D2
0
0
1
0
D1
0
1
0
0
D0
1
0
0
0
S0
0
1
0
1
S1
0
0
1
1
(b)!Truth table.
S1D
D
D
D
0
1
2
3
( )a Block diagram.
S0
Figure 10.45
D3
0
0
0
1
D2
0
0
1
0
D1
0
1
0
0
D0
1
0
0
0
S0
0
1
0
1
S1
0
0
1
1
(b)!Truth table.
S1D
D
D
D
0
1
2
3
( )a Block diagram.
S0
D3
D0
D2
D1
S
S
S
S
S
S
S
S
1
0
1
0
1
0
1
0
'
'
'
'
Figure 10.46
S1D
D
D
D
0
1
2
3
Enable
S0
Figure 10.47
Demultiplexer• A demultiplexer routes a single input value
to one of several output lines
• Control lines determine the data output line to which the input gets routed
D
D
D
D
D
0
1
2
3
S1 S0
( )a Block diagram.
S0
0
1
0
1
S1
0
0
1
1
(b)!Truth table.
D0
D
0
0
0
D1
0
D
0
0
D2
0
0
D
0
D3
0
0
0
D
Figure 10.48
Half adder• The half adder adds the right-most two bits
of a binary number
• Inputs: The two bits
• Outputs: The sum bit and the carry bit
Figure 10.49
(a) Block diagram. (b) Truth table. (c) Implementation.
A B
A B
Sum
Sum
0
0
1
1
0
1
0
1
0
1
1
0
Carry Carry
0
0
0
1
Carry
Sum
A B
Figure 10.49
Full adder• The full adder adds one column of a binary
number
• Inputs: The two bits for that column and the carry bit from the previous column
• Outputs: The sum bit and the carry bit for the next column
(b) Truth table.
Cout
0
0
0
1
0
1
1
1
Sum
0
1
1
0
1
0
0
1
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Cout Cin
( )a Block diagram.
Sum
A B
Figure 10.50
Figure 10.51
A
C
S
B
Cout
Sum
Cin
A
C
S
B
A B
Figure 10.51
Ripple-carry adder• The ripple-carry adder adds two n-bit binary
numbers
• Inputs: The two n-bit binary numbers to be added
• Outputs: The n-bit sum, the C bit for the carry out, and the V bit for signed integer overflow
Figure 10.52
A
S
B
Cout Cout
S3 S2
Cin
A3 B3 A2 B2
V
A
S
B
Cout
S3 S2 S1 S0
Cin
S1
A1 B1
A
S
B
Cout Cin
S0
A0 B0
A
S
B
C
(b) Implementation.
(a) Block diagram.
A3 A2 A1 A0 B3 B2 B1 B0
Cout
V
Figure 10.52
Computing the V bit• You can only get an overflow in one of two
cases
‣ A and B are both positive, and the result is negative
‣ A and B are both negative, and the result is positive
Adder/subtracter• Based on the relation
NEG x = 1 + NOT x
• XOR gates act as selective inverters
• A – B = A + (–B)
Figure 10.53
A
S
B
Cout Cout
S3 S2
Cin
A3 B3 A2 B2
V
A
S
B
Cout
S3 S2 S1 S0
Cin
S1
A1 B1
A
S
B
Cout CoutCin Cin
S0
A0 B0
A
S
B
(b) Implementation.
(a) Block diagram.
A3 A2 A1 A0 B3 B2 B1 B0
Cout
VSub
Sub
Figure 10.53
Arithmetic Logic Unit (ALU)
• Performs 16 different functions
• Inputs: Two n-bit binary numbers, four control lines that determine which function will be executed, and one carry input line
• Outputs: The n-bit result, the NZVC bits
Figure 10.54
A B
Cout
Zout
Cin
V
N
ALUALU
4
Result
Figure 10.54
Figure 10.55
N Zone V Cont(bin) (dec) Result
0
C
C
C
C
0
0
0
0
0
0
C
C
C
C
A<7>
0
V
V
V
V
0
0
0
0
0
0
V
0
0
0
A<6>
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
A<4>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A plus B
A plus B plus Cin
A minus B
A plus B plus Cin
A B
A B
A + B
A + B
A B
A
ASL A
ROL A
ASR A
ROR A
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
A<5>
Status bitsALU control
Figure 10.55
Zout Cout
A plus B plus 1
Figure 10.56
Result
ResultResult
Result
12 Two-Input Multiplexers
N
0 0 0 0 0 0 0 0
Zout V Cout
Cin
V C
V C
N ZN Z V C
A B
01234567891011121314
15
ALU
4 16
Decoder
Computation
Unit
Figure 10.56
15
The multiplexer of Figure 10.56
• If line 15 is 1, Result and NZVC from the left are routed to the output
• If line 15 is 0, Result and NZVC from the right are routed to the output
Figure 10.57
Result
10 12-Input OR Gates
Cin
V C Result V C d e f gE E
AA
A
B
B
A Cin
Cin
012345
14
AB
Logic Unit 14
ROR A
Logic Unit 5
A AND BA Unit Arithmetic Unit
8 8
8
Result V C
Result V C
8
8
EResult V C
8
8
Figure 10.57
Figure 10.58
Result
A
V C
0 0
E
Figure 10.58A Unit
Figure 10.59
Result
C V
A
S
B
Cout Cin
A7 B7 A6 B6
A
S
B
Cout Cin Cout Cin
Cin
A0 B0
A
S
B
C
d
e
f
g
Sub
Figure 10.59Arithmetic Unit
16-bit add
A<low> B<low>
S<low>
A<high> B<high>
S<high>
Cout A plus BA plus B plus Cin Cin
16-bit subtract
A<low> B<low>
D<low>
A<high> B<high>
D<high>
Cout A plus B plus 1A plus B plus Cin Cin
Figure 10.60
f g Sub CFunction d e
1
0
0
0
A plus B
A plus B plus Cin
A minus B
A plus B plus Cin
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
Cin
1
Cin
Figure 10.60
A plus B plus 1
Figure 10.61
a
b
a
bc
(a)
(c)
a
b
(b)
Figure 10.61
Figure 10.62
(a) (b) (c) (d)
Figure 10.62
s = 0
a
b
x
y
s
s = 1
a
b
x
y
s
Figure 10.63
s1 s0 = 00
a
b
x
y
s1
s1 s0 = 10
x
y
s1
s1 s0 = 11
x
y
s1
s1 s0 = 01
a
b
a
b
a
b
x
y
s1s0 s0 s0s0
Figure 10.64
