Upload
dinhhuong
View
247
Download
1
Embed Size (px)
Citation preview
PCI and PCI Variations
Agenda
• Introduction to PCI– PCI Overview– PCI Applications– Different Flavors of PCI– Market Trends
• PCI Technology overview• PCI Solutions
– Spartan-IIE Overview– Spartan-IIE PCI Solutions
• PCI 64-bit/66 Overview– PCI Example Boards
• Summary
PCI Overview
• Peripheral Component Interconnect• Originated in the PC industry• High performance bus that provides a processor
independent data path between the CPU and high-speed peripherals
• Robust interconnect mechanism developed to relieve the I/O bottlenecks
• Used in the multiple high performance peripherals for graphics, full motion video, SCSI, LAN & embedded systems
Vast array of PCI Applications
• PC board applications• Laptops • Servers• Telecom• Networking• Computing• Instrumentation• Video and Image Processing
Emerging Applications RequireHigher PCI Bandwidth
PCI Performance
132 MB/s
528 MB/s
264 MB/s
0
100
200
300
400
500
600
32-bit/33MHz 64-bit/33MHz32-bit/66MHz
64-bit/66MHz
Max
imum
Thr
oug
hput
[M
B/s
] • Mass-Storage/RAID• High-end Printer I/Fs• DSP/Imaging• Gigabit Ethernet• ATM, Fibre Channel
PCI-X [64-bit/133MHz]
PCI [32-bit/33MHz]
PCI [64-bit/66MHz]
Wide Ultra2 SCSI133 Mbytes/sec80 Mbytes/sec
533 Mbytes/secAGP 2X 533 Mbytes/sec
IEEE-1394 400 Mbits/secUSB 12 Mbits/sec
Fibre Channel ~ 1Gbytes/sec
132 Mbytes/secSpec Throughput (max)> 1 Gbytes/sec
PCI Throughput (Max)
• Maximum Usable Bus Bandwidth• 32-bit PCI protocol allows for four byte transfer every clock• If the burst length is infinite, then maximum throughput is
– (4 bytes) * 33.3333MHz = 133 Mbytes/sec (PCI 32-bit/33MHz)
Different Flavors of PCI
PCI/PCI-XPC Local
Bus
PC PCIVariations
Embedded PCIVariations
Mini-PCI AGP
Small PCICardbus
PCI (Slot)
PCI-X (Slot) CompactPCI
PMC
The PCI Market Keeps Growing...
Source: Electronic Trend Publications and IDC
PCI Forecast (sub-set)
00.5
11.5
22.5
33.5
44.5
2001 2002 2003 2004Year
Dol
lars
(bill
ion) Mini-PCI
PCI-XPMCcPCIPCI
PC Local Bus PCI variations PCI-X• PCI-X is an extension of the existing PCI bus interface• The PCI-X spec specifies a bus design that can increase
data throughput to over 1GBp/sec• PCI-X is backward compatible with the existing PCI bus
– PCI-X adapter can operate in a conventional PCI system, and vice-versa
• Used in higher bandwidth applications:– NICs supporting multiple gigabit devices– Routers, Hubs and Switches– RAID Controllers– Clustered Server Interconnects
PC Local Bus PCI variations: PCI-X differences from PCI• PCI-X doubles the throughput to 1056MBp/sec from 528MBp/sec
possible with regular PCI 64/66• PCI-X relaxes the strict timing constraints required by the PCI
64/66 specification, which makes it easier to design• PCI-X improves bus efficiency by enhancing PCI protocol
– Attribute Phase– Split Transactions– Optimized Use of Wait States– Standard Block Size Movements– Improved Parity Error Handling
• PCI-X supports up to four slots at 66MHz as opposed to two with PCI 64/66, two slots at 100MHz and one slot at 133MHz
PC PCI Variations - Cardbus
• Few removals and additions from traditional PCI signals• PCI in a PCMCIA form factor
– PCMCIA 16-bit 5 volt ISA standard– CardBus 32-bit 3.3 volt PCI standard
• Point-to-point• Portable environment
– NICs– Modems– Sound cards– CF adapters
PC PCI Variations: Mini PCI
• New portable PCI proposal• Same electrical and protocols• Different form factor
– Type 1: For full-featured systems that allow increased flexibility in placement via cabling to the I/O connectors
– Type 2: For makers of value-priced notebooks and mobile computing devices, with RJ11 and/or RJ45 connectors that eliminate the cost of the intermediate cable
– Type 3: Designed for ultra-thin notebooks uses SO-DIMM style connectors
• Targeted at Modems and NICs
PC PCI Variations - Small PCI
• Small form factor• 32-bit PCI bus• Aimed at highly integrated peripheral controller
components, peripheral add-in boards, and processor / memory systems
• Less widespread acceptance
PC PCI Variations: AGP
• Advanced Graphics Port• Designed to remove major load from the PCI bus and
improve graphics performance– Specifically for 3-D rendering
• Point-to-Point graphics bus to link graphics engine with main memory
• Higher throughput– No internal competition (point-to-point)– No cache coherence checking– No wait states– Supports long bursts
PC PCI Variations - AGP
• Uses main memory to hold rendering images and moves them fast enough to minimize frame buffer usage– Main memory cheaper than frame memory (DRAM vs. SRAM)– Cuts overall bandwidth requirements as most data is retrieved from main
memory or hard disk– Main memory is easier and cheaper to expand
• Uses 1.5V or 3.3V signaling
Embedded PCI Variations - PMC
• PCI Mezzanine Card• Defines the mechanics of a slim, modular, parallel
mezzanine card family • Uses the logical and electrical layers of the PCI
specification for the local bus• Used where slim, parallel board mounting is required
such as in single-board computer host modules with the addition of expander cards or option cards
• Mainly aimed at industrial applications such as backplane expansion
Embedded PCI Variations CompactPCI• Uses standard PCI specification for devices• Eurocard form factor with unique physical and mechanical
requirements with high-reliability features• Used as backplane with up to eight slots• PCI Industrial Computers Manufacturers Group (PICMG) defines
CompactPCI - Xilinx is member
CompactPCI(Eurocard)Standard PCI Slot
Embedded PCI Variations CompactPCI• Live insertion and removal of cards
– High availability systems• Electrical issues
– Pre-charge signal lines to ~1V– Leakage current important– 4ms from long to short pin– Limited Early Power (2 Amp max)
• Adds Hot Swap Register• Three levels of compliance
– Ready, Friendly, Capable
X8438
Power/Ground
Enable
PCI Signals
Staged pins on backplane
Other Embedded PCI Variations
• PCI (slot)– Local bus for standard PCI cards on passive backplane or
active motherboard– Widespread acceptance in all sorts of embedded applications
• PCI-X (slot)– Local bus for standard PCI-X cards on passive backplane or
active motherboard– Gaining high adoption in high-performance embedded
applications
Technology Overview
Timing
PCI Specification 2.2
PCI Specification 2.2
Mechanical
ProtocolElectrical
PCI Local Bus Architecture
• The PCI Local Bus Specification covers many different requirements for PCI compliance
Basic Bus Architecture
Motherboard
ProcessorSystem
ProcessorSystem
PCI Local BusPCI Local Bus
HostBridgeHost
Bridge3D Sound
Card3D Sound
Card
MPEGVideo
CaptureCard
MPEGVideo
CaptureCard
3DGraphics
Card
3DGraphics
Card100 MbitEthernet
100 MbitEthernet
LANLAN
ExpansionBus
Bridge
ExpansionBus
Bridge
ISA
56KModem
56KModem
AddAdd--in Cardsin Cards
SCSIController
SCSIController
PCI-to-PCI Bridge andPeer-to-Peer
AgentAgent
ProcessorSystem
ProcessorSystem
AgentAgent
PCI L
ocal
Bus B
#0
PCI L
ocal
Bus B
#0
AgentAgent
AgentAgent
Peer-to-PeerHost
BridgeHost
Bridge
PCI Local Bus A #0PCI Local Bus A #0Primary Bus
PCI-to-PCIBridge
PCI-to-PCIBridge
PCI Local Bus A #1PCI Local Bus A #1Secondary Bus
Upstream Transaction
Downstream Transaction
Protocol Compliance
Key Terms
• Initiator– or Master– Owns the bus and initiates the data transfer– Every Initiator must also be a Target
• Target– or Slave– Target of the data transfer (read or write)
• Agent– Any initiator/target or target on the PCI bus
Distributed Address Decoding
AD[31:0]
AgentAgent
DecoderDecoder
AgentAgent
DecoderDecoder
AgentAgent
DecoderDecoder
AgentAgent
DecoderDecoder
InitiatorInitiator BridgeBridge
DecoderDecoder
CS1 AgentAddressDecoder
Agent
Agent
CS0
CS2
Dedicated Address DecodingSeparate Chip Selects generated
by a Central Address Decoder
Distributed Address DecodingProgrammable decoders
Each agent decodes address onPCI bus. The agent reacts if i ts
address is on PCI bus
• PCI uses Distributed Address Decoding
PCI Bandwidth
• Distributed access decode speed effects throughput • Latencies and wait states reduces PCI throughput• Burst size has a big impact on PCI bandwidth
Effect of burst size on PCI bandwidth
020406080
100120140
0 10 20 30 40Double-Word Burst size
Tran
sfer
rate
(M
byte
s/se
c)
Ideal PCI WriteIdeal PCI Read
PCI Bus Arbitration
• Arbitration is the process of providing rights to the PCI bus to one of the PCI agents by the arbiter
• PCI spec does not specify the design of the arbiter, only that it be fair to prevent starvation
• Common arbiters includes Round-Robin, Priority, and Two-level Priority Agent
Central Resource
Agent Agent
Arbiter
REQ#GNT#
REQ#
GNT#
REQ#GN
T#
PCI Arbitration Concept
• Arbitration is “hidden” by current transaction– Reduces arbitration latency
• Receiving GNT# means you will be the next owner of the bus after the bus goes IDLE
• Losing GNT# when you are the bus owner is called Preemption– Does not mean you lose the bus immediately
PCI Commands
With IDSELWith IDSEL
00010010
01000011
01010110
10000111
10011010
11001011
11011110
CBE
1111
Special Cycle0000 Interrupt Acknowledge
Command
I/O ReadI/O Write
ReservedConfiguration ReadConfiguration WriteMemory Read MultipleDual Address CycleMemory Read LineMemory Write and Invalidate
ReservedReserved
Memory ReadMemory WriteReserved
Memory Spaces
• Each PCI target has three memory regions• Memory
– 2 Gbyte max, 16 bytes min– Recommend 4Kbyte min
• I/O– 2 Gbyte max, 4 bytes min– For 80X86 systems, 256 bytes max because of legacy ISA
issues• Configuration
– 256 bytes– First 64 bytes is the Configuration Header– Rest is user defined
PCI Configuration
• Part of “Plug & Play”– Allows add-in cards to be plugged into any slot without
changing jumpers or switches– Card must contain information for the BIOS and/or operating
system• Type of card and device• Memory space requirements• Interrupt requirements
• Configuration Header– First 64 bytes of the configuration space– Contains all the necessary information
Address Size(Hardwired) Base Address
AddressComparator
Address on Bus
Mask Hit
Base Address Registers (BAR)
• Distributed Address Decoding• Two types - memory and I/O• Up to six BARs
– Mix and Match of types• Most applications use one or two• Read returns address size request• Software then writes base address into BAR• Target responsible for tracking address
during burst
Electrical Compliance
Electrical Specification
• Very detailed Electrical Specifications which cover– Device DC characteristics– Device timing requirements– Board level issues
• Electrical Compliance Checklist– Must be filled out for every device– One checklist for 5V signaling and another for 3.3V signaling
• Please refer to PCI specification for details
50pF Load
Far End
HSPICE Simulation of Intel PCI Speedway
Driver End
Reflective Wave Switching
• PCI Bus is unterminated - replies on Reflective Wave Switching• Signal must be valid on the first reflected wave• Detailed Electrical Spec to guarantee proper signal switching
Signaling Environment
• Two different electrical specs– 5V signaling– 3.3V signaling
• Name has nothing to do with the supply voltage!!• 5V signaling is most common• 66MHz is 3.3V signaling only• Some devices can support both - Universal
Signaling Environment - DC Spec
3.3V Devices are OK
All parameters are functions of VDD!
VSS = 0V
Logic HighVOH = 0.9 X VDD = 2.97V
VIL = 0.3 X VDD = 0.99V
VOL = 0.1 X VDD = 0.33V
VDD = 3.3V
VIH = 0.5 X VDD = 1.65V
+3.3V Signaling
Logic Low
Vdd = 5.0V
VOH = 2.4V
VIH = 2.0V
VIL = 0.8V
VOL = 0.55V
Vss = 0V
+5V Signaling
Logic Low
Logic High
I/V Curves
Figure 1. Pull Up V/I Curve for 5 V Signaling Environment
Figure 2. Pull Down V/I Curve for 5 V Signaling Environment
2.2
0.55
3, 6 95 380Current (mA)V
olta
ge
VccPull Down
DC drivepoint
AC drivepoint
testpoint
2.4
1.4
-2 -44 -176Current (mA)
Vol
tage
VccPull Up
DC drivepoint
AC dri vepoint
testpoint
One set of 5v and another for 3.3v Signaling
Clamp Diodes
• Clamp diodes to GND always required• Clamp diodes to VCC required for 3.3 signaling
– Optional for 5V signaling– Protect device I/O structure against large undershoots
and overshoots– Needed to help dampen reflections on the bus
Bad Clamping - 5V Signaling Environment
Vdd = 5.0v Vdd = 3.3v
PCI Bus
Chip InputChip Output
Timing Compliance
33MHz PCI Timing Specification
30ns Bus Cycle Time
11nstval
Max Clock-to-valid
Other Requirements:Hold time : 0nsMin Clock-to-out : 2nsOutput off time : 28ns
All timing Parameters are measured at the package pin
10nstprop
Wave Propagation
7nstsu
Input Setup
2nstskew
Clock skew
66MHz PCI - Timing Comparison
11ns 10ns 7ns 2nstproptval tsu tskew
30ns Bus Cycle Time
Max Clock-to-valid Wave Propagation Input Setup Clock skew
6ns 5ns 3ns 1ns
tproptval tsu tskew
Clk-to-out Wave Prop Setup Clk skew
15ns Bus Cycle Time
Other Requirements:Hold time : 0nsMin Clock-to-out : 2nsOutput off time : 14ns
Why is PCI timing so tough?
PCI Signal
FFLogic
7ns + clock_delay
High Fanout
PCI CLK
11ns - clock_delay
PCI Signal
• PCI handshaking performed every clock cycle => no pipelining• 7ns Setup + clock_delay => 100+ MHz!!• 3ns Setup + clock_delay => 240+ MHz!! [66MHz PCI]• I/O tends to be the slower part of FPGAs
Mechanical Compliance
Add-in Card Design
• Trace length– All 32-bit PCI signals must be no more than 1.5”– All 64-bit extension signals must be no more than 2.0”
• Clock trace must be 2.5” exact! [+/- 0.1”]– Routed to only one load
• PCI Device Requirements– One pin per signal!– Max input capacitance is 10pF
• If device is on motherboard, then 16pF is OK
5V and 3.3V Add-in Cards
• Cards are “keyed” for 5V or 3.3V signaling– Universal cards have both “keys”
5v Key3.3v Key
Face
Plat
e
64-bit ext.
System Issues - Bus Loading
• No PCI spec requirement as to the loading on the bus, but– Must meet the 10ns propagation delay on the bus
• Rule of thumb is “Ten loads maximum for 33MHz”– Motherboard devices count as one load– Each add-in card slot counts as two load– Since most PC motherboards must have two or more PCI
devices, they usually have no more than four slots• More slots are available using PCI-to-PCI bridges or Peer-
to-Peer PCI systems
Spartan-IIE PCI Solutions for Consumer Digital Video
300K GatesDistributed and
Block RAMFast I/O Performance
Spartan-IIE: The Total Solution
More Performance
Feature Rich Time-to-Market
More Gates
Cores Easy Design Flow
Free WebPACK SWFast, Predictable
Routing
DLLsSystem I/OTM (19)
LVDS/LVPECL
CLB
IOB
CLB
CLB
CLB
IOB
IOB IOB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
IOB
BRAM
DLL
DLL IOB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CL
IOB
CL
IOBIOB
IOBIOB
BRAM
DLL
CLB
IOB
CLB CLB
IOB
IOB IOB
BRAMCLB
CLB
CLB
CLB
BRAMCLB
CLB
CLB
CLB
IOBIOB
IOBIOB
IOBIOB
CL
CL
BRAM
IOB CLB
DLL
BRAM
IOB
2ns2ns
2ns
CLB Tiles• Fast, predictable
interconnect
CLBDifferential I/O• 400 Mbps• LVDS• Bus LVDS• LVPECL
IOB
Delay Lock Loops• 200+ MHz performance• 4 DLLs in every device• Deskew 4 system Clks• Zero-delay clock conv.
CLKIN
CLKFB
RST
CLK0CLK90
CLK180CLK270CLK2XCLKDV
LOCKED
DLL
Dual-Port4KbitBRAM Po
rt B
Block RAM• Up to 64Kbits• 200 MHz
BRAM
System I/OTM
• 19 signaling standards• Chip to Backplane• Chip to Memory• Chip to Chip
IOB
Spartan-IIE Technology
7400 Series
CountersAdders
Data PathMemoryControllersuControllers
PCI/PCI-XFECFFT/FIR FiltersIMA (ATM)EncryptionMP3 Decoder
ConsumerSet-Top BoxesDigital TVCable ModemBluetoothHome NetworkingDigital Video
NetworkingxDSL ModemsLine Cards
ComputersGraphic CardsPrinters
Bio-Medical, Industrial
Perfo
rman
ce &
Den
sity
1980s 1990s 2000s
FPGA Application Trends
Source: Microprocessor Report
High Performance Moves Beyond Enterprise Networking
Digital Video Requires High DSP & Interconnectivity Performance
Flexibility - Interconnectivity
• Plethora of interconnectivity standards– Video standards
• VGA, SVGA, XGA, SXGA, UXGA, WXGA– System interfaces/buses
• LVDS, PCI/PCI-X, AGP, processor– High speed video memory
• HSTL, SSTL-based SRAM, DRAM solutions– High speed video interfacing standards
• IEEE-1394, IEEE-1355, USB 2.0, wireless – Preferences and options vary by geography
PCI Solutions Today
• Standard PCI Chips– Specialized on PCI– Price $15-$35– Offers complete solution
• Reference designs, boards, drivers, application notes
– Limitations• Extra PLD(s) often required for glue logic
– A standard PCI chip is a bridge to a specific bus• Cannot be customized or upgraded
– Limited performance in some applications
PCI Solutions Today
• ASICs with PCI core– Usual ASIC issues– High NRE– No flexibility (essential for fully compliant PCI)– Long development time
Xilinx has a Rich PCI Heritage
100
1000
10000
1994 1996 1998 2000 2002
Aggr
egat
e Ban
dwid
th M
b/se
c
500
5000
50000
Internet Backbone
32-bit33MHz
64-bit66MHz
64-bit66MHz
64-bit133MHz
Roadmap
2.5 Gbps Ultra 320 SCSI
2GbpsFibre Channel
10 GbpsFibre Channel Ethernet
40 GbpsEthernet
1 GbpsFibre Channel Ethernet
Xilinx PCI Performance
Xilinx PCI in End Applications
• Xilinx PCI Solutions are used in a Wide-Array of Applications – Processor Bus to PCI Bus Conversions– Data Encryption/Decryption– High Speed Networking– Digital Video Applications– I/O Communications Ports– Memory Interfaces– High Speed Data Input/Output (Acquisition)– Multimedia Communications– And many many more!!!
Spartan-IIE PCI Solution Overview• 64-bit PCI solution
– Supports 66MHz PCI• 32-bit PCI solution
– Supports up to 66MHz PCI Designs• Customizable asynchronous FIFO reference
designs– Integrate seamlessly with PCI cores
Spartan-IIE PCI Customer Benefits• Reduces cost over PCI ASSPs
– Cost savings of more than 50%• Integrate and replace system functions
– PLL/DLL clock management devices– SSTL-3/HSTL translators– LVDS– Backplane logic and drivers– External memory devices– System & caches controllers
• Significant time-to-market advantage
ASSP Replacement & Integration
PCI PCI ASSPASSP
Glue Logic
System & Memory Controllers, DLLs, Level Translators ($20)
External PLD PCI Master I/F ($5)
Memory ($9)
Standard Chip PCI Master I/F ($15)
*Supported Devices XC2S50E
XC2S100E XC2S150E XC2S200E XC2S300E
Real-PCI from Xilinx
• Real Compliance– Guarantees Setup, Hold and Min/Max Clock-to-Out timing
• Real Flexibility– Supports a wide range of Spartan-II devices allowing for easy
device migration– Back-end decoupled from the PCI Interface to allow
customization without affecting PCI timing• Real Performance
– Zero-wait state – Up to 528MBps sustained throughput
• Real Availability - Right Here Right Now!
Spartan-IIE LogiCORE PCI Block Diagram
Modular ArchitectureBest Flexibility and Predictability
PCI PCI
FIFO(s)User Design
Up to 25,000System Gates
User Design
Up to 25,000System GatesDMA(s)
PCI
Back
end
Inte
rface
Proven core with predictable timing
De-coupled “Soft” Reference Designs for easy customization
On-chip scalable, dual-port FIFOs
Xilinx low-cost Spartan-IIE FPGA
Supporting Reference Designs
• Asynchronous FIFOs and DMA Controller• Power Management Module
User DesignUp to 135,000 System Gates
Power Management Module
Asynchronous FIFOs
Custom DMA Controller
Real-PCIInterface
PCI 64 PCI 32Us
er I
nter
face
PCI B
us
PCI - A Successful Programmable Solution
0.5
1
0.1
External PLD7K Gates
External DLLs, memories, Controllers and translators
Standard Chip
Relat
ive C
ompo
nent
Cos
t
PCI ASSPPCI Master
and Slave I/F
XC2S50E-5 PQ20835K Gates Extra
LogicPCI
Master I/F
Solution <$5 per silicon
basis
Solution <$5 per silicon
basis
Spartan-IIE FPGAs Lower
Overall System Cost
The 64-bit/66 MHz PCI Solution
The Xilinx PCI64/66 Solution
• Solves timing issues– Enabled by Spartan-II/Spartan-IIE, Virtex/Virtex-E/Virtex-II– Guaranteed through Smart-IP
• No performance limitations– Full 64-bit data path– Zero wait-state burst
• Implemented in standard FPGAs– Best flexibility– Off-the-shelf devices– Large-scale manufacturing - low cost– Excellent testability– Cutting edge process technologies
The Real 64/66 PCI from Xilinx
PCI64/66Zero wait-state
FIFO(s)
User Design
DMA(s)
64-b
it Int
erfa
ceReal Performance• Compliant zero wait-state at 66MHz• Full 64-bit data path
Real Compliance• PCI v2.2 Initiator and Target• Guaranteed timing
Real Flexibility• Uses standard Spartan-IIE FPGA• Back-end de-coupled from core
260,000 gates in XC2S300E
64-b
it, 66
MHz
PCI
Predictable and Flexible
• Only PCI core for FPGAs with guaranteed timing – Including 2ns clock-to-out min timing, and 0 ns hold – FPGA characterized together with core– Pre-defined critical placement and routing
• First parameterizable PCI core– Configurable on the web
• First core with modular architecture– Core de-coupled from back-end design– Back-end customizable without affecting PCI timing
Real Compliance to PCI v2.2 -Protocol, Timing and Electrical• PCI64 core is based on PCI32
– Has been used in over 1,000 customer designs– Many are fully compliant add-in boards
• Timing guaranteed through Smart-IP• Protocol verified with internal testbench
– simulates over 6 million PCI cycles• Meets the electrical PCI specification
– Fast multi-standard System I/OTM interface allows a single I/O per PCI signal - required by the PCI spec
The Real 64/66 PCI Guarantees The Critical Path
• The critical path is equivalent to• Uses Xilinx unique Smart-IP technology to guarantee min, max & hold time
– Core and silicon characterized together
PCI Signal
FFLogic
PCI CLK
PCI Signal20 loads 72 loads
3ns0ns
Setup:Hold time:
6ns2ns
Clk-out max: Clk-out min:
The Real 64/66 PCI: Summary
• Real Compliance - guaranteed timing• Real Flexibility - implemented in standard
Spartan-IIE FPGAs• Real Performance - full 528 Mbytes/sec• Real Availability - downloadable from Xilinx web
site now
Spartan-IIE PCI Solutions
* PCI32: 66 MHz design available using Xilinx XPERTs or Design Services
PCI Over the Internet
• All design files are released on WebLINX
• Instant access of new releases and updates
• Intuitive GUI generates guaranteed design files
• Verified for– Synopsys– Synplicity– MTI– Cadence Verilog XL
PCI Training Classes
• Two day PCI course– Basic PCI concepts – Xilinx PCI solution – Designing with Xilinx PCI– Design debug
• Provide worldwide access to certified PCI experts that can provide– Support for targeting additional devices– Implementation of additional features– Complete turnkey integration
• Xilinx design center
MULTI VIDEO DESIGN
PCI Expertise
Xilinx PCI Board Examples
"With the Real 64/66 PCI products fromXilinx, we were able to implement a fully compliant PCI interface – plus other functions such as direct memory access (DMA), 4 dual-port FIFOs, and 200,000 gates of our own unique design – in a single device,” said John Beck Principal Engineer, DOME Imaging, Inc. "After evaluating different solutions in the market, we found thatonly Xilinx could meet the demanding requirements for full 66MHz PCI compliance.”
High-resolution displaycontroller for the medical
imaging market. Handles transfers of over 500 MB/s from the host.
High-Performance Color Copier InterfaceHigh-Performance Color Copier Interface
EDOX Document Server• Fully compliant PCI board• PCI and back-end: Xilinx
(Bloomington, Minnesota)
Graphics Accelerator PCI boards
• Fully compliant PCI boards• PCI and back-end: Xilinx• More: 14x Analog Devices DSP processors
(Huntsville, AL)
TDZ 2000
PCI Summary
• Recognized as the industry leader in PCI solutions– Over 1,200 proven working designs
• Xilinx offers rich support for PCI– Real Compliance - guaranteed timing– Real Flexibility - industry’s most flexible PCI solution– Real Performance - full 528Mbytes/sec– Real Availability - download from Xilinx web site now
• Xilinx PCI with Spartan-IIE cost-effectively meets needs of digital convergence market