PCI Express Multi-Channel DMA Interface2014.12.15

UG-01160 Subscribe Send Feedback

The PCI Express® DMA Multi-Channel Controller Example Design provides multi-channel support forthe Stratix® V Avalon® Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core. Up to eightexternal DMA controllers drive DMA descriptors to the PCI Express Multi-Channel DMA AvalonStreaming (Avalon-ST) sink interfaces. The PCI Express Multi-Channel DMA arbitrates between thedescriptor queues, taking into account the request priority and the weight. The Data Mover is a module inthe soft-logic bridge in the Stratix V Avalon-MM DMA for PCI Express IP Core.

Figure 1: PCI Express Multi-Channel DMA Interface Example Design System-Level Block Diagram

PCI Express Multi-Channel DMA Interface Data Mover

PCIeHard IPG3X8

Avalon Streaming256 bits PCIe TLP

Avalon-MM DMA for PCI Express

Mstr

Mstr

Rd & Wr Sub-DescriptorsSinkSrc

Slave

Sink SrcCompletion Status

Rd & Wr Descriptors0Sink

DMAController0

Src

Sink

DMAController7

Control Register Access

SrcCompletion Status0

Rd & Wr Descriptors7SinkSrc

SinkCompletion Status7

Src

Memory

Avalon-MM 256 bits

Slave

Slave

Avalon-MM 256 bits

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified astrademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

ISO9001:2008Registered

www.altera.com101 Innovation Drive, San Jose, CA 95134

Preliminary

Figure 2: PCI Express Multi-Channel DMA Interface Internals Block Diagram

Original ID 0 Mapped to > 0 - 7Original ID 1 Mapped to > 8 - 15Original ID 2 Mapped to > 16 - 23Original ID 3 Mapped to > 24 - 31Original ID 4 Mapped to > 32-39

Original ID 31 Mapped to > 248 - 255

Priority Queue 1

Priority Queue 0

Priority ID Dest Source Length End Orig. ID Sub-ID Dest Source Length

Status Queue

4XFragmentation

Priority Sort

Channel 1

4XFragmentation

Priority Sort

Channel 0

4X4XFragmentation

Priority Sort

Channel 7

DescriptorRemoval

Multi-ChannelControl Registers

(Abort, pause)

Status toController

Avalon-MMSlave

Scheduler

CompletionStatus Counter 16xCompletion

Status Counter 16xCompletionStatus Counter 16xCompletion

Status Counters

Descriptorto Data Mover

Status fromData Mover

Multi-Channel Adapter

Slave

The PCI Express Multi-Channel DMA Interface Example Design performs the following functions:

• Stores up to four outstanding descriptors for each channel before deasserting the ready signal• Divides each descriptor into subdescriptors with a payload size of 512 bytes• Arbitrates between two priority queues based on the Channel Priority Weight• Tracks the completion status of the 32 possible outstanding descriptors• Forwards completion status to the DMA Controllers• Removes descriptors from internal queues on successful completion and in response to a requests

received on its Avalon-MM Control register interface• When multi-function support is enabled, maps function numbers to channel numbers.

2 PCI Express Multi-Channel DMA InterfaceUG-01160

2014.12.15

Altera Corporation PCI Express Multi-Channel DMA Interface

Send Feedback

Preliminary

Note: The PCI Express Multi-Channel DMA Interface Example Design is preliminary in the currentrelease. Both the programming model and top-level signals may change in subsequent releases.

Device Family Support

Table 1: Device Family Support

Device Family Support

Stratix V Final. The IP core is verified with final timingmodels. The IP core meets all functional and timingrequirements for the device family and can be usedin production designs.

Other device families No support.

ParametersThe PCIe® Multi-Channel DMA Interface Example Design has three parameters that you can specify tocustomize its function.

Table 2: Parameteres

Parameter Name Value Description

Number of channels 2, 4, 8 Specifies the number of channels.Channel priority weight 0, 4, 8 The arbiter uses the Channel priority weight in combina‐

tion with the descriptor priority bit to calculate the ratio oftransmission between priority queues.

Descriptor width 161, 169 Specifies the width of the descriptor. When you select 169,the low-order 8 bits specify the function number for variantswith SR-IOV enabled.

PCIe Multi-Channel DMA InterfacesThe PCIe Multi-Channel DMA Interface Example Design interfaces receive DMA descriptors on up toeight Descriptor Controller Avalon-ST RX interfaces. It drives the selected descriptor to the Data Moverusing its single Descriptor Avalon-ST TX interface. The Data Mover drives status to the PCIe Multi-Channel DMA on the Descriptor Status Avalon-ST RX interface. The PCIe Multi-Channel DMA forwardsstatus to the DMA controllers on its Descriptor Status Avalon-ST source interfaces. An Avalon-MM slaveinterface allows DMA controllers to remove descriptors from the PCIe Multi-Channel DMA internalqueues.

UG-011602014.12.15 Device Family Support 3

PCI Express Multi-Channel DMA Interface Altera Corporation

Send Feedback

Preliminary

DescInstr0_i[168 or 160:0]DescInstrValid0_iDescInstrReady0_o

DescInstr7_i[167:0]DescInstrValid7_iDescInstrReady7_o

DmaTxData0_o[31:0]DmaTxValid0_o

DmaTxData7_o[31:0]DmaTxValid7_o

MCSlaveChipSelect_iMCSlaveWrite_iMCSlaveAddress_i[13:0]MCSlaveWriteData_i[31:0]MCSlaveWaitRequect_o

clk_irstn_i

DmaRxData_o[159:0]DmaRxValid_oDmaRxReady_i

PCI Express Multi-Channel DMA Controller IP Core

ControlRegister

Descriptor Controller0

RX

Completion Status0

CompletionStatus7

Descriptor Status RX

Descriptor TX

Descriptor Controller7

RX

DmaTxData_i[31:0]DmaTxValid_i

Related InformationAvalon Interface Specifications

PCIe Multi-Channel DMA Descriptor Interfaces

Table 3: Descriptor Controller RX Interface

This is an Avalon-ST sink interface. It is synchronous to clk_i.Signal Name Direction Description

DescInstr<n>i[168 or

160:0]

Input Write descriptor or data moving instruction. When SR-IOV is enabled, the bus has the following layout:

• [168:161]: Function number• [160]: Priority• [159:0]: Descriptor

Otherwise, the bus has the following layout:

• [160]: Priority• [159:0] Descriptor

This is the format that the Data Mover included in theAvalon-MM DMA for PCI Express requires.

4 PCIe Multi-Channel DMA Descriptor InterfacesUG-01160

2014.12.15

Altera Corporation PCI Express Multi-Channel DMA Interface

Send Feedback

Preliminary

Signal Name Direction Description

DescInstrValid<n> _i Input When asserted, indicates that DescInstr<n>_i is valid.

DescInstrReady<n> _o Output When asserted, indicates that the channel can acceptnew descriptors. The ready latency on this interface is 0cycles. The Multi-Channel DMA Controller stores dataon the rising edge of clock whenever DescInstr-Ready<n> and DescInstrValid<n> are both asserted.

Table 4: Descriptor Status Interface

This is an Avalon-ST source interface.Signal Name Direction Description

DmaTxData<n>_o[31:0] Output Specifies the status for the descriptor ID specified. Thefollowing fields are defined:

• [31:14]: Reserved• [13:12]: Status code

• 2'b00: Descriptor completed successfully• 2'b01: Descriptor removal completed successfully• 2'b10: Descriptor partially removed• 2'b11: Descriptor removal failed

• [11:8]: Reserved• [7:0]: Descriptor ID whose status is being reported

DmaTxValid<n>_o Output When asserted, indicates that DmaTxData<n>_o[31:0]is valid. This interface does not have a ready input. Therequesting controller must be able to store datawhenever DmaTxValid<n> is asserted.

Control Register InterfaceTo cancel a pending descriptor, a DMA controller writes the descriptor ID to the Avalon-MM slaveinterface. The Mulit-Channel DMA Interface IP Core drives the status of this request on the DescriptorStatus interface of the requesting controller.

Table 5: Control Register Interface

This is an Avalon-MM slave interface. It is synchronous to clk_i.Signal Name Direction Description

MCSlaveChipSelect_i Input When asserted, the other signals in this interface aredriving valid data.

MCSlaveWrite_i Input Asserted to perform a write.MCSlaveAddress_i[13:0] Input Specifies the address of the Control Register Avalon-

MM slave interface.

UG-011602014.12.15 Control Register Interface 5

PCI Express Multi-Channel DMA Interface Altera Corporation

Send Feedback

Preliminary

Signal Name Direction Description

MCSlaveWriteData_

i[31:0]

Input Specifies the ID for the of the descriptor being deleted.The status of this request is reported on the appropriateControl Status interface.

Note: When removal of a descriptor is requested,internal logic searches the pipeline andbuffers for the descriptor ID. It may not findthe ID requested. The requesting controllermust manage appropriately, based on thestatus reported on the Control Statusinterface.

MCSlaveWaitRequest_o Input When asserted, this interface is not ready to acceptcommands.

Descriptor TX Interface

Table 6: Descriptor TX Interface to Data Mover

This is an Avalon-ST source interface. It is synchronous to clk_i.Signal Name Direction Description

DmaRxData_o[167 or

159:0]

Output The DMA Multi-Channel Controller drives descriptordata to the Data Mover on this Avalon-ST sourceinterface. (It uses priority bit[160] internally and doesnot drive it to the Data Mover.

DmaRxValid_o Output When asserted, the data on DmaRxData_o is valid.

DmaRxReady_i Input When asserted, the Data Mover is ready to accept newdescriptors. The ready latency on this interface is 3cycles. Consequently, the DMA Multi-ChannelController must stop driving valid data within 3 cyclesof the deassertion of DmaRxReady_i.

6 Descriptor TX InterfaceUG-01160

2014.12.15

Altera Corporation PCI Express Multi-Channel DMA Interface

Send Feedback

Preliminary

Table 7: Descriptor Status Interface

This is an Avalon-ST sink interface. the

Signal Name Direction Description

DmaTxData_i[31:0] Input The Data Mover drives status to the DMA Multi-Channel Controller on this Avalon-ST interface.Specifies the status for the descriptor ID specified. Thefollowing fields are defined:

• [31:14]: Reserved. All 0s.• [13:12]: Status cod.e

• 2'b00: Descriptor completed successfully.• 2'b01: Descriptor removal completed successfully.• 2'b10: Descriptor partially removed. Part of the

descriptor has already been processed. Thecontroller must include logic to process partialcompletion data.

• 2'b11: Descriptor removal failed.• [11:8]: Reserved. All 0s.• [7:0]: Descriptor ID whose status is being reported.

DmaTxValid_i_i Input When asserted, indicates that DmaTxData_i[31:0] isvalid.

Example DesignYou can download a Qsys example design that illustrates the use of this component from the installdirectory, <install_dir>ip/altera/altera_pcie/altera_pcie_hip_256_avmm/channelizer/example_design/.

This example design includes the following Qsys files:

• mc_top_g3x8_4ch.qsys—This is the top-level Qsys file that connects the DUT and APPS components.• sriov_mcdma_app_g3x8_256b.qsys—This Qsys system connects an example Avalon-MM DMA for PCI

Express with Single Root I/O Virtualization (SR-IOV) to read and write descriptor controllers andSRAM.

• rddc_mc_256b.qsys—This Qsys system connects four read descriptor controllers the the PCI ExpressDMA Multi-Channnel Controller IP Core.

• wrdc_mc_256b.qsys—This Qsys system connects four write descriptor controllers the the PCI ExpressDMA Multi-Channnel Controller IP Core.

UG-011602014.12.15 Example Design 7

PCI Express Multi-Channel DMA Interface Altera Corporation

Send Feedback

Preliminary

Figure 3: Qsys Sub-System with Four Write Descriptor Controllers and the DMA Multi-ChannnelController

Revision HistoryDate Version Changes

2014.12.15 14.1 • Initial Release.

8 Revision HistoryUG-01160

2014.12.15

Altera Corporation PCI Express Multi-Channel DMA Interface

Send Feedback

Preliminary