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Version 1.0 Keysight - PCIe Gen 3.0 CEM RX Test MOI – SIG Page 1 of 92

07/02/2015

PCI Express 3.0 CEM RX Physical Layer Test

Method of Implementation for Keysight J-BERT M8020A and N4903B

High Performance BERTs


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Keysight Disclaimer The scope of this document is to provide a step by step guide to perform a manual and

automated PCIe gen 3.0 CEM receiver (RX) test calibration and receiver test.

It is not in the scope of this document to explain the reasons or theory behind the calibration

procedure. The application note “How to Pass Receiver Test According to PCI Express 3.0

CEM Specification with Add-In Cards and Motherboards” pub number 5990-9208EN does an

excellent job in providing the background behind the PCIe 3 CEM spec calibration procedures.

All product names are trademarks, registered trademarks, or service marks of their respective

owners.

DISCLAIMER

The information in this document refers to PCI Express Architecture PHY Test Specification,

revision 3.0 from June 6, 2013.

It is advised to check the latest version of the specifications and if it differs from those

mentioned above, check for possible changes.


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PCI-SIG Disclaimer All product names are trademarks, registered trademarks, or service marks of their respective

owners.

The PCI-SIG disclaims all warranties and liability for the use of this document and the

information contained herein and assumes no responsibility for any errors that may appear in

this document, nor does the PCI-SIG make a commitment to update the information contained

herein.

Contact the PCI-SIG office to obtain the latest revision of this document

Questions regarding this document or membership in the PCI-SIG may be forwarded to:

PCI-SIG 3855 SW 153rd Drive Beaverton, OR, 97006 Phone: 503-619-0569 Fax: 503-644-6708

e-mail [email protected] http://www.pcisig.com

DISCLAIMER

This document is provided "as is" with no warranties whatsoever, including any warranty of

merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise

arising out of any proposal, specification, or sample. The PCI-SIG disclaims all liability for

infringement of proprietary rights, relating to use of information in this specification. No license,

express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.

All product names are trademarks, registered trademarks, or servicemarks of their respective

owners.

Copyright © 1999, 2000, 2003, 2005, 2006, 2012 PCI-SIG


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Contents Keysight Disclaimer ................................................................................................................... 2

PCI-SIG Disclaimer .................................................................................................................... 3

Contents .................................................................................................................................... 4

Tables ........................................................................................................................................ 6

Revision History ......................................................................................................................... 7

1 Overview ............................................................................................................................. 8

2 Instrumentation ................................................................................................................... 9

2.1 BERT system ............................................................................................................... 9

2.2 Oscilloscope ................................................................................................................ 9

2.3 Fixtures .......................................................................................................................10

2.4 BERT Error Detector Equalization ...............................................................................10

2.5 Couplers, Cables, Adapters, Terminations and DC-Blocks .........................................11

3 Software ............................................................................................................................12

3.1 SIGTEST ....................................................................................................................12

3.2 N5990A-301 PCIe Link Training Suite.........................................................................12

4 Calibration ..........................................................................................................................13

4.1 Calibration Procedure .................................................................................................13

4.2 Calibration Setup ........................................................................................................14

4.2.1 Calibration Setup for Add-In Card RX Test ..........................................................14

4.2.2 Calibration for System RX Test ............................................................................15

4.3 Calibration Values .......................................................................................................16

4.4 J-BERT Setup .............................................................................................................17

4.4.1 J-BERT N4903B Setup ........................................................................................17

4.4.2 J-BERT M8020A ..................................................................................................21

4.5 De-emphasis Compensation and Amplitude Cal .........................................................24

4.5.1 De-emphasis Definition according to PCI Express ...............................................25

4.5.2 Nomenclature for J-BERT de-emphasis and preshoot: ........................................25

4.5.3 Calculation of Va, Vb, Vc based on settings Vd, pre-shoot and de-emphasis .........25

4.5.4 RT-Scope Setup ..................................................................................................26

4.5.5 Amplitude Calibration ...........................................................................................27

4.5.6 De-Emphasis and Pre-Shoot Calibration ..............................................................28

4.6 Random Jitter (RJ) Pre-Calibration .............................................................................35


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4.6.1 J-BERT Setup ......................................................................................................35

4.6.2 RT-Scope Setup ..................................................................................................37

4.6.3 RJ Measurement .................................................................................................37

4.7 Sinusoidal Jitter (SJ) Pre-Calibration ..........................................................................41

4.7.1 J-BERT Setup ......................................................................................................41

4.7.2 RT-Scope Setup ..................................................................................................43

4.7.3 SJ Measurement ..................................................................................................44

4.8 Differential Mode Sinusoidal Interference (DM-SI) Pre-Calibration ..............................49

4.8.1 J-BERT Setup ......................................................................................................49

4.8.2 RT-Scope Setup ..................................................................................................52

4.8.3 DM-SI adjustment ................................................................................................53

4.9 Pre-Calibration Results (for DSAX 93204A) ................................................................54

4.10 Eye Height (EH) and Eye Width (EW) Calibration .......................................................55

4.10.1 J-BERT Setup ......................................................................................................55

4.10.2 RT-Scope Setup ..................................................................................................57

4.10.3 Eye Height (EH) and Eye Width (EW) Measurement ...........................................58

4.10.4 Search for Target EW and EH .............................................................................60

5 Receiver Test .....................................................................................................................61

5.1 Test Setup ..................................................................................................................62

5.1.1 Test Setup for Add-In Card RX Test ....................................................................62

5.1.2 Test Setup for System RX Test ............................................................................64

5.2 Pattern Generator Clocking .........................................................................................65

5.2.1 AIC ......................................................................................................................65

5.2.2 System.................................................................................................................66

5.3 Error Detector Clocking ...............................................................................................68

5.3.1 Error Detector Clocking for J-BERT N4903B based Setup ...................................68

5.3.2 Error Detector Clocking for J-BERT M8020A based Setup ..................................71

5.4 DUT Training ..............................................................................................................73

5.4.1 DUT Training using Static Training Sequence......................................................73

5.4.2 DUT Training using Interactive Link Training .......................................................77

5.5 Error Counter Setup ....................................................................................................80

5.5.1 Error Counter Setup J-BERT N4903B based Setup .............................................80

5.5.2 Error Counter Setup J-BERT M8020A based Setup.............................................80


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5.5.3 SKP OS Filtering ..................................................................................................81

5.6 Test Procedure for Test 2.8 and 2.9 ............................................................................82

6 Calibration and Test Flow Chart .........................................................................................85

7 Automated Receiver Test Software ....................................................................................86

7.1 Test Station Configuration ...........................................................................................86

7.2 DUT Configuration ......................................................................................................87

7.3 Calibration ..................................................................................................................88

7.4 Receiver Tests ............................................................................................................91

7.5 TX EQ Matrix Scan .....................................................................................................92

7.6 Equalization Scan .......................................................................................................92

Tables Table 4.3.1: PCIe 3.0 8GT/s RX Calibration Targets .................................................................16

Table 4.5.1: TX EQ Presets and Corresponding Va, Vb and Vc Levels .......................................28

Table 4.9.1: Pre-Calibration Results ..........................................................................................54

Table 4.10.1: Pre-Calibration Values as Starting Point for EH and EW Search .........................60

Table 4.10.2: EW and EH for Stress Signal based on Pre-Calibration .......................................60

Table 4.10.3: Final Stress Settings for a Possible Compliance Point .........................................60

Table 5.1.1: PCIe 3.0 8GT/s Receiver Compliance Tests .........................................................61


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Revision History Version Date Summary of Change(s) Contributors

0.9 03/11/2015 Based on Agilent RX Test MOI for PCIe 3.0

Updated to Keysight

Added J-BERT M8020A

Changed most scope screenshots to new scope GUI

Thorsten Götzelmann

1.0RC1 06/10/2015 V1.0 Release Candidate 1 Thorsten Götzelmann

1.0 07/02/2015 V1.0 for PCISIG webpage Thorsten Götzelmann


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1 Overview This document provides a method of implementation for the receiver test calibration and

receiver tests defined in the PCI Express Architecture PHY Test Specification Revision 3.0.

The related specifications are:

PCI Express Base Specification Revision 3.0, Ver. 1.0

PCI Express Card Electromechanical Specification Revision 3.0, Ver. 1.0

PCI Express Architecture PHY Test Specification Revision 3.0, Ver. 1.0

A manual calibration and test procedure is covered in detail in chapter 4. Due to the complexity

and its time consuming nature of the calibration a calibration and test automation is highly

recommended. Keysight’s N5990A Test Automation Platform is used for workshop testing. It is

covered in chapter 7.


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2 Instrumentation

2.1 BERT system

The BERT system consists of either a Keysight J-BERT N4903B High-Performance Serial

BERT in combination with a N4916B De-Emphasis Signal Converter and a N4880A reference

clock multiplier (reference clock multiplier is required for system test only) or a Keysight J-BERT

M8020A High-Performance BERT.

BERT solution based on the J-BERT N4903B:

N4903B with following options:

N4903B-C13 – 12.5G BERT

N4903B-J10 – Jitter injection

N4903B-J11 – SSC generation

N4903B-J20 – Interference channel

N4903B-A02 – SKP OS filter. Only needed if device under test repositions or

modifies SKP OS

N4916B with option STD and N4915A-010 cable kit

N4880A reference clock multiplier. Only for system test

BERT solution based on the J-BERT M8020A:

M8020A-BU1 – Bundle consisting of 5 slot AXIe chassis and controller card with USB

option and AXIe PC module or M8020A-BU2 – Bundle consisting of 5 slot AXIe chassis

and controller card with USB option (requires external PC to control M8020A system)

M8070A-0TP – System SW for M8000A Series – transportable license or M8070A-0NP

– System SW for M8000 Series – network license

M8041A-C16 – 16.2G BERT module

M8041A-0G3 – Jitter Sources

M8041A-0G4 – De-emphasis

M8041A-0G7 – Interference Sources

M8041A-0S2 – SKP OS Filtering. Only needed if device under test repositions or

modifies SKP OS

M8041A-0A3 – Analyzer Equalizer. Only for system test

M8041A-0G6 – Reference Clock Multiplier. Only for system test

M8041A-0S1 – Interactive Link Training for PCIe - recommended

2.2 Oscilloscope

The Keysight DSAX / DSOX series oscilloscope with at least 25GHz bandwidth can be used for

the calibration of the receiver stress signal.


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2.3 Fixtures

The PCI-SIG offers fixtures for PCIe gen3.

CBB – compliance base board

Riser – the riser is attached to the CBB and simulates together with the CBB a worst case

server scenario

CLB – compliance load board. The compliance load board is available as x4/x8 and x1/x16

CLB. The x4/x8 CLB is the one used in this document

2.4 BERT Error Detector Equalization

Due to the long trace lengths existing on systems, it might be necessary to use a equalizer for

the error detector of the BERT system. Option M8041A-0A3 provides a CTLE on the J-BERT

M8020A data inputs. In case of the J-BERT N4903B a PCIe repeater might be used in the data

return to the BERT error detector. The Texas Instruments / National Semiconductor

DS80PCI800EVK is widely used for this purpose.

CBB-riser card connected with CBB main board

CLB plugged into CBB-main board


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2.5 Couplers, Cables, Adapters, Terminations and DC-Blocks

Matched cable pairs

SMA (m) to SMA (m) – N4903B-J20 Interference Plug-In to N4916B De-Emphasis signal

converter, e.g. Keysight part number N4871A or M8041A-801. Only for J-BERT N4903B

based systems.

SMA (m) to SMA (m) – Texas Instruments / National Semiconductor repeater to J-BERT

N4903B error detector, e.g. Keysight part number N4871A or M8041A-801. (only in

some cases for J-BERT N4903B but not required for J-BERT M8020A)

SMP (f) to SMA (m) – 100MHz ref clock to / from J-BERT N4903B or M8020A pattern

trigger output from CLB / to CBB, e.g. Keysight part number N4235-61602 or Astrolabs

Minibend® S

SMP (f) to SMA (m) – data connection to DUT RX, e.g. Keysight part number N4235-

61602 or Astrolabs Minibend® S

SMP (f) to SMA (m) – data connection from DUT TX, e.g. Keysight part number N4235-

61602 or Astrolabs Minibend® S

Cables

1x SMA(m) to SMA(m) 3ft cable for system test (system test) in case of J-BERT N4903B

DC blocks

2x DC blocks for data connection to DUT RX, e.g. Keysight part number N9398C

TTC. Only required for J-BERT M8020A

2x 10GHz low pass filters Tektronix product number PSPL5935-10GHz-292JP

Asymmetric couplers. Only required for J-BERT N4903B.

2x z-matched pick-off, e.g. Tektronix product number PSPL5372

2x 3.5mm(m) to 3.5mm(m) adapter, e.g. Keysight product number 83059A

Adapters

14x 2.4mm(m) to 3.5mm(f) adapter, e.g. Keysight product number 11901C or N4911A-

002. Only for J-BERT N4903B

2x SMP(m) to 3.5mm(f) adapter to connect SMP cables to DSOX /DSAX scope

Terminations

11x SMA(m) 50Ohm termination, e.g. Keysight product number N4911A-004


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3 Software

3.1 SIGTEST

This document uses SIGTEST 3.2.0.

3.2 N5990A-301 PCIe Link Training Suite

The N5990A-301 PCIe Link Training Suite is used to generate the training sequences for

N4903B J-BERT to train the device under test (DUT) into loopback.


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4 Calibration

4.1 Calibration Procedure

The calibration of the stress test signal consists of multiple steps.

De-emphasis signal calibration at SMP connector

Pre-calibration of RJ

Pre-calibration of SJ

Pre-calibration of DM-SI

Eye width and eye height calibration


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4.2 Calibration Setup

Although the calibration procedure is the same for add-in card receiver stress test calibration

and system receiver stress test calibration the calibration setup differs.

4.2.1 Calibration Setup for Add-In Card RX Test

Terminate all unused 2.4mm connectors of J-BERT N4903B.

Terminate all unused data and clock connections of J-BERT M8020A


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4.2.2 Calibration for System RX Test


Terminate all unused data and clock connections of J-BERT M8020A.


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4.3 Calibration Values

Parameter Min Max Unit SigTest

Technology Template

Vpp 800 mV N/A N/A

RJ (Random Jitter) 1.5 1.7 psrms PCI_3_0_RX_CAL PCIE_3_8GB_Rx_Sj_CAL

SJ (Sinusoidal Jitter) @ 100 MHz

12.5 13.5 pspp PCI_3_0_RX_CAL PCIE_3_8GB_Rx_Sj_CAL

Differential Mode Sinusoidal Interference at 2.1 GHz

14 16 mVpp N/A N/A

VRX-EH-8G

Eye Height AIC: 44 to 46

System: 45 to 50

mV PCI_3_0_RX_CAL AIC: PCIE_3_8GB_RX CARD_CAL_MULTI_CTLE_DFE_EMBED01

System: PCIE_3_8GB_RX SYS_CAL_MULTI_CTLE_DFE_ EMBED01

TRX-EW-8G

Eye Width AIC: 39.25 to

41.25

System: 43 to 45

ps PCI_3_0_RX_CAL AIC: PCIE_3_8GB_RX CARD_CAL_MULTI_CTLE_DFE_EMBED01

System: PCIE_3_8GB_RX SYS_CAL_MULTI_CTLE_DFE_ EMBED01

Table 4.3.1: PCIe 3.0 8GT/s RX Calibration Targets


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4.4 J-BERT Setup

4.4.1 J-BERT N4903B Setup

4.4.1.1 N4916B De-Emphasis Signal Converter Activate N4916B de-emphasis signal converter

Perform timing adjustment for N4916B

1. Press “Load Calibration Setting” once

2. Connect main clock out normal to ED clock in

3. Select Input Timing Setup to 1. Do NOT press “Load Calibration Setting”

4. Perform Auto Align of ED

5. Start error count by pressing the start button once and wait until the accumulation is

finished.


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6. Switch to Accumulated Results and note the recorded BER

7. Repeat steps 3 to 6 for all 6 input timing settings.

8. One or two input timing settings will show a BER>0. Choose the input timing setting

which is the furthest away from the failing input timing settings, e.g. 2 failed choose 5.

4.4.1.2 Pattern setup Different patterns are used during the calibration. J-BERT offers a pattern sequencer allowing

setup of all patterns at once and toggling the patterns.


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4.4.1.3 Data and Clock Outputs Terminate all unused 2.4mm outputs

Set the trigger output function to sequence trigger

Set main clock out and trigger out to the below values


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Set data output and aux data output to below values

Activate DM-SI but set 0V amplitude

Activate SSC, PJ1 and RJ but set all to 0% deviation / 0mUI amplitude


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4.4.2 J-BERT M8020A

Recall instrument state Factory PCIe3 PCI_Express_8G_Cal

4.4.2.1 Pattern Setup Open the Sequence Editor

Each pattern required for a calibration step is part of the PgSequence

Toggle to the next pattern with the Break function

4.4.2.2 Data and Clock Outputs Data Out of channel 1 is used for receiver testing in this document

In the Channel 1 Data Out 1 properties section set:

Coupling to AC

Offset to 0V

Amplitude to 400mV

Preset Register to 4

Pre-Cursor1 to 0dB

Pre-Cursor1 Sign to positive

Post-Cursor1 to 0dB

Post-Cursor1 Sign to negative


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Set Channel 1 Data Out 1 impairments to:

LF Jitter PJ to Active

LF Jitter PJ Amplitude to 0mUI

LF Jitter PJ Frequency to 1kHz

Interference DMI to Active

Interference DMI Amplitude to 0mV

Interference DMI Source to High Frequency

Interference High Frequency to 2.1GHz

HF Jitter PJ1 to Active

HF Jitter PJ1 Amplitude to 0mUI

HF Jitter PJ1 Frequency to 100MHz

HF Jitter RJ to Active

HF Jitter RJ Amplitude to 0mUIrms

HF Jitter RJ Low Pass Filter to 1GHz

HF Jitter TJ High Pass to 10MHz

HF Jitter RJ sRJ Low Pass Filter to Off


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Trigger Out is used to trigger the RT-scope for the calibration while it is used as reference

clock output for AICs for testing

Set Trigger Out to

Amplitude to 500mV

Offset 0mV

Operation Mode to Subrate Clock

Divider to 256


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4.5 De-emphasis Compensation and Amplitude Cal

This calibration is done at the end of the SMA to SMP cables feeding the signal into the CBB / CLB. Use SMP to SMA adapters on the scope.

Pattern consists of 64x clk/2 cycles and at least one clk/128 cycle. More clk/128 are better

Use pattern trigger

Measurement is done on differential signal

No embedded channels

Calibration is done for P4 (0dB pre, 0dB post1), P7 (3.5dB pre, -6dB post1), P0 (0dB pre, -6dB post), P8 (3.5dB pre, -3.5dB post) and all pre-sets used in the receiver stress test measurement

The target peak to peak amplitude is 800mV differential

The target accuracy is +/- 0.2dB

When using a real-time scope a small number of averages is recommended

Either a histogram based method or cursor based method to measure the different amplitudes can be applied. Do not use the scope built-in pp measurements. Use educated averaging for cursor based measurements and in case of Vb use the first 4 bits of the of the Vb level only.


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4.5.1 De-emphasis Definition according to PCI Express

4.5.2 Nomenclature for J-BERT de-emphasis and preshoot:

De-emphasis post1 Preshoot pre vd amplitude

4.5.3 Calculation of Va, Vb, Vc based on settings Vd, pre-shoot and de-

emphasis

va = |c0| + |c1| - |c2| c0..main cursor

vb = |c0| - |c1| - |c2| c1..post cursor

vc = |c0| - |c1| + |c2| c2..pre cursor

vd = |c0| + |c1| + |c2|

c0 = vd (1 + r1r2) / (2 (1 - r1 + r1r2)) r1 = 10(post1 / 20)

c1 = vd (1 - r1) / (2 (1 - r1 + r1r2)) r2 = 10(pre / 20)

c2 = vd r1(r2 - 1) / (2 (1 - r1 + r1r2))

va = vd / (1 - r1 + r1r2)

vb = vd r1 / (1 - r1 + r1r2)

vc = vd r1r2 / (1 - r1 + r1r2)


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4.5.4 RT-Scope Setup

use differential channel 1-3

use J-BERT’s trigger out signal to trigger scope via channel 4

use 256 averages

if a rt-scope with a bandwidth <20MHz is used, be sure to not measure the amplitude based

on artifacts as a result of the lower bandwidth

Use a histogram or cursor based method to measure the peak to peak amplitude


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4.5.5 Amplitude Calibration

Adjust peak to peak amplitude to 400mV single ended / 800mV differential by changing the

data output amplitude of J-BERT.

J-BERT N4903B Based Setup

J-BERT M8020A Based Setup


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4.5.6 De-Emphasis and Pre-Shoot Calibration

Since the de-emphasis is defined at the SMP connectors of the CBB / CLB it has to be

calibrated and cannot just be set for the N4903B based setup.

Amplitude, pre-shoot (pre) and de-emphasis (post) have to be adjusted to below table. De-

Emphasis Presets for 800mV Amplitude, target accuracy for the de-emphasis cal is +/-

0.2dB.

Preset number Post [dB] Pre [dB] va vb vc

P0 -6 0 800 401 401

P1 -3.5 0 800 535 535

P2 -4.4 0 800 482 482

P3 -2.5 0 800 600 600

P4 0 0 800 800 800

P5 0 1.9 643 643 800

P6 0 2.5 600 600 800

P7 -6 3.5 641 321 480

P8 -3.5 3.5 601 402 601

P9 0 3.5 535 535 800

Table 4.5.1: TX EQ Presets and Corresponding Va, Vb and Vc Levels


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4.5.6.1 P7 Example for M8020A based setup va:

vb:


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vc:

Vpp:


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va = 615mV, vb = 305mV and vc = 457mV Measured pre of 3.5dB and post of -6.1dB

within target range


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4.5.6.2 P7 Example for N4903B based setup va:

vb:


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vc:

vpp:


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va = 645.6mV, vb = 325.3mV and vc = 460.3mV Measured pre of 3.0dB and post of -6.0dB

within target range


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4.6 Random Jitter (RJ) Pre-Calibration


The pattern used is clk/2 (1010)

SIGTEST is used to measure RJ. SIGTEST requires a 16M / 80GSa/s waveform capture.

Target value is 1.5psrms to 1.7psrms

4.6.1 J-BERT Setup

Toggle to the pattern sequencer block 2 containing the clk/2 pattern pressing the <Break>

button

Set amplitude and de-emphasis to the values previously determined for P4

Activate SSC with 0% deviation and PJ with 0mUI amplitude

Enable PJ1 but set to 0mUI

Activate RJ and set to 12mUIrms (1.5psrms)

Enable 10MHz High Pass filter


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Use Differential measurement on the scope

Set to 80GSa/s

Deactivate Sin(x)/x Interpolation

Deactivate averaging

Set memory depth to manual 16Mpts

4.6.3 RJ Measurement

Make a single waveform capture

Save waveform: All Data, Binary Data Files

Load waveform capture into SIGTEST

Set differential


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No embedding

Set test mode to CEM

Set SIGTEST to

Technology: PCIE_3_0_RX_CAL

Template file: PCIE_3_8GB_CEM_Rx_Sj_CAL

Press “Test” to get the result screen

Adjust RJ on the J-BERT if necessary and repeat the measurement until RJ is within

1.5psrms to 1.7psrms. J-BERT’s factory RJ cal is very good but the intrinsic jitter of J-BERT is

not included. A good practice is to make waveform captures for 12mUI, 11.5mUI and 11mUI

RJrms settings.


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J-BERT Setting of 12mUI J-BERT Setting of 14.5mUI

The 14.5mUI setting is within target range and is used for RJ pre-cal.

Remark:

It can be useful to generate a RJ pre-calibration table/graph since RJ will be adjusted for the

final eye height (EH) and eye width (EW) calibration. The 0mUI / 0ps RJ point should be ignored

in case a linear trend line is calculated.

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500

RJ

rms

[ps]

me

asu

red

RJ rms set on J-BERT [ps]

RJ measured RMS [ps]

0.888*(RJ set)+0.335

min spec


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Instead of running SIGTest manually for every waveform use a .bat file:

<"<path to SigTest.exe>" /d "<path to waveform files>" /t

"PCIE_3_0_RX_CAL\PCIE_3_8GB_CEM_Rx_Sj_CAL.dat" /o RxCalResults.txt /s *.bin>

for instance:

<"C:\Program Files\SigTest 3.2.2\SigTest.exe" /d "C:\SIGTest waveforms\PreCal\RJ" /t

"PCIE_3_0_RX_CAL\PCIE_3_8GB_CEM_Rx_Sj_CAL.dat" /o RxCalResults.txt /s *.bin>

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

0 5 10 15 20 25

RJ r

ms

[ps]

me

asu

red

RJ rms set on J-BERT [mUI]

RJ measured RMS [ps]

0.111*(RJ set)+0.335

min spec


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4.7 Sinusoidal Jitter (SJ) Pre-Calibration


The pattern used is the PCIe 3.0 Compliance Pattern for lane 0

SIGTEST is used to measure SJ via total jitter (TJ). It is measurement in two steps. First the baseline TJ1 is measured with SJ set to 0ps followed by a TJ2 measurement with SJ set to target amplitude. The delta between TJ2 and TJ1 is the SJ number. SIGTEST requires an 8M / 40GSa/s waveform capture.

SJ is at 100MHz

Target value for SJ is 12.5ps to 13.5ps

4.7.1 J-BERT Setup

Use the break button to toggle to the pattern sequencer block containing the PCIe 3.0

compliance pattern for lane 0




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Activate RJ and set to 0mUIrms (0psrms)

Enable PJ1 with 100MHz and 0mUI (0ps)


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Use Differential measurement on the scope

Set to 80GSa/s





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4.7.3 SJ Measurement

SJ is not measured directly with SIGTEST. A two-step approach is used. First the baseline

TJ has to be measured

Set J-BERT’s PJ1 to 0mUI



Load waveform capture into SIGTEST

Set differential

No embedding



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Set SIGTEST to

Technology: PCIE_3_0_RX_CAL

Template file: PCIE_3_8GB_CEM_Rx_Sj_CAL

Press “Test” to get the result screen

Record the baseline TJbase. The <Max Peak to Peak Jitter(ps)> value from SIGTEST’s

result panel is used to determine TJ


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In this case TJbase = 12.25ps.

Now determine TJ with SJ being present

1. Set PJ1 on J-BERT to 100mUI (12.5ps)


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2. Save the waveform, process in SIGTEST with the same settings and record Max Peak to

Peak Jitter as TJ100.


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In this case TJ100 = 25.20ps.

3. SJ100 = TJ100 – TJbase = 25.20ps – 12.25ps = 12.95ps

4. Adjust PJ on the J-BERT if necessary until SJ is between 12.5ps and 13.5ps and repeat

steps 1 to 3 with adjusted PJ amplitude.


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4.8 Differential Mode Sinusoidal Interference (DM-SI) Pre-Calibration

This calibration is done with CBB and CLB in the signal path. System calibration as well as add-in card calibration for DM-SI is using the calibration setup for add-in cards. Please see calibration setup section.

The pattern used is PAUSE0 for N4903B and static low for M8020A, a pattern consisting of zeroes only

SIGTEST is not used for the measurement. Instead a marker measurement on the scope is used. A rt-scope as well as a sampling scope is possible.

Target value for DM-SI is 14mV to 16mV

4.8.1 J-BERT Setup

Toggle to the pattern sequencer block containing the Pause0 / static low




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Activate RJ and set to 0mUIrms (0psrms)

Enable PJ1 with 100MHz and 0mUI (0ps)


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Set sinusoidal interference to 2.1GHz and a starting amplitude of 45mV for N4903B based

setup and 12mV for M8020A based setup


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Use Differential measurement on the scope but readjust scale for channel 1 and channel 3

to 2.5mV per division and for the differential signal

Set to 80GSa/s (in case of a DSA use 40GSa/s)




Set acquisition bandwidth to manual 8GHz

Set horizontal scale to 21µs


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4.8.3 DM-SI adjustment

Use V p-p measurement to measure the DM-SI amplitude

Adjust the amplitude for DM-SI on J-BERT until amplitude reading is between 14mV and

15mV.

Remark:

DM-SI is a parameter which has to be adjusted for the final eye height (EH) and eye width (EW)

cal. Therefore it makes sense to generate a cal table / graph for DM-SI Set DM-SI measured

which covers DM-SI values beyond the pre-calibration goals. It makes sense to cover 2 times

to 3 times the pre-calibration range.


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4.9 Pre-Calibration Results (for DSAX 93204A)

The pre-calibration results will differ between setups and instruments but can be used as

starting values.

Description Settings on J-BERT N4903B Settings on J-BERT M8020A

De-emphasis and amplitude settings on J-BERT:

P4: 1012mV diff, post1: -0.5dB, pre: 0dB P7: 1038mV diff, post1: -7.3dB, pre: 3.6dB

P4: 710mV diff, post1: -0 dB, pre: 0dB

P7: 710mV diff, post1: -6B, pre: 3.5dB

RJ setting on J-BERT 14.5mUI 12.5mUI

SJ setting on J-BERT 100mUI 109mUI

DM-SI setting on J-BERT

75mV 9mV

Table 4.9.1: Pre-Calibration Results


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4.10 Eye Height (EH) and Eye Width (EW) Calibration

The actual calibration of the stress test signal is based on eye height (EH) and eye width (EW)

measurements with SIGTEST with embedding of the remaining channel and reference package

model after the CBB/CLB and all stress impairments activated. CTLE needs to be fixed. For

AIC stress test calibration use setup according to setup diagram 4.2.1 and for system stress test

calibration use setup according to diagram 4.2.2.

4.10.1 J-BERT Setup

Toggle to the pattern sequencer block containing the PCIe 3.0 compliance pattern for lane 0


Activate SSC with 0% deviation

Activate RJ and set pre-calibrated value

Enable PJ1 with 100MHz and set to pre-calibrated value


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Activate DM-SI and set to pre-calibrated value


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Use Differential measurement on the scope. Ensure proper scaling of channel 1 and 3 as

well as differential signal!

Set to 80GSa/s




Set bandwidth to 16.2GHz or higher


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4.10.3 Eye Height (EH) and Eye Width (EW) Measurement

1. Save five individual waveform captures



EH and EW readings in SIGTEST can vary widely between different waveform captures

of the same signal, therefore take at least three waveform captures and average the EW

and EH results.

2. All waveform captures need to be analyzed with fixed CTLE settings with SIGTEST for

CTLE setting 7. Use a batch file for this

Activate embedding “/e”

Technology: PCIE_3_0_RXCAL

Template file:

For systems:

PCIE_3_8GB_Rx_CEM_SYS_CAL

For AIC:

PCIE_3_8GB_Rx_CEM_CARD_CAL


Command prompt: < "<path to sigtest.exe>" /e /d "<path to waveform captures>" /t

"PCIE_3_0_RX_CAL\<template>.dat" /o EH_EW_Results.txt /s *.bin>

for example for AIC cal:

< "C:\Program Files (x86)\SigTest 3.2.2\SigTest.exe" /e /d "C:\PCIe

gen3\CEM\SIGTEST waveforms" /t

"PCIE_3_0_RX_CAL\PCIE_3_8GB_Rx_CEM_CARD_CAL.dat" /o RxCalResults.txt /s

*.bin>

Check result file for eye height column <Composit Eye Height>, unit is [V], and check

corresponding eye width column <Min Eye Width>, unit is [ps].


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3. Adjust RJ and DM-SI on the J-BERT if necessary and repeat steps 1 to 3 until EW and EH

are within range:

Add-in card calibration:

EW 39.25ps to 41.25ps

EH 44.00mV to 46.00mV

System calibration:

EW 43.00ps to 45.00ps

EH 45.00mV to 50.00mV


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4.10.4 Search for Target EW and EH

It can be necessary to increase DM-SI as well as RJ to much higher values than determined in

the pre-calibration to achieve the target EW and EH range. Following is an example for an EW

and EH calibration for an AIC test using a x4/x8 CLB.

Measure EW and EH as described above for pre-calibration values.



P7: 1038mV diff, post1: -7.3dB, pre: 3.6dB


RJ setting on J-BERT 14.5mUI 12.5mUI



75mV 9mV

Table 4.10.1: Pre-Calibration Values as Starting Point for EH and EW Search

Example SIGTEST (CTLE 7) measurements for EW and EH for pre-calibration values for J-

BERT N4903B based setup are:

Waveform Capture Eye Width(EW) Eye Height (EH)

1 53.0ps 56.9mV

2 54.1ps 57.2mV

3 54.0ps 58.7mV

4 54.0ps 58.7mV

5 54.6ps 58.7mV

Average 53.9ps 58.0mV

Target range 39.25ps to 41.25ps 41.00mV to 46.00mV

Table 4.10.2: EW and EH for Stress Signal based on Pre-Calibration

EW and EH are significantly off. Both DM-SI and RJ affect EW as well as EH. DM-SI and RJ

have to be adjusted to get EW and EH within target range.

Possible J-BERT settings for this example which would achieve a compliant EW

and EH



P7: 1038mV diff, post1: -7.3dB, pre: 3.6dB


RJ setting on J-BERT 19.5mUI 25mUI



200mV 22mV

Table 4.10.3: Final Stress Settings for a Possible Compliance Point


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5 Receiver Test Unlike the PCIe gen 3 base specification the PCIe gen 3 CEM specification describes one

receiver test only.

The receiver test is performed with the calibrated eye height (EH) and eye width (EW). The SJ

frequency is kept constant at 100MHz. The long channel receiver preset tests for P7 and P8

have to be passed with a maximum bit error rate of 10-4 bits and are for AICs only. AICs as well

as systems have to pass with a maximum of one error within 1012 bits for one de-emphasis

setting of choice on gen3 CLB (system) or gen3 CBB + riser (AIC). If the best pre-shoot and de-

emphasis combination is unknown an equalization scan as shown in section 7.6 can be

performed to determine good TX eq settings.

The short channel test replaces the gen3 CBB + riser with a gen2 CBB. This test is FYI only

and only for AICs. Presets P1, P7 and P8 are tested for a bit error rate of better than 10-4.

De-Emphasis Setting Test Criteria Comments

Preset P1 (AIC short channel test only)

Bit error rate better or equal 10

-4 The target bit error rate is so high that an accumulation period with hundreds of thousands of errors is possible. A 2s accumulation period would observe so many errors for a system with an error rate of 10

-4 that the measured Bit Error Ratio is

approximately the system bit error rate.

Preset P7 (AIC only)

Preset P8 (AIC only)

Choice of DUT provider Maximum of 1 error in 10

12 compared bits

Set an accumulation period of 125s

Table 5.1.1: PCIe 3.0 8GT/s Receiver Compliance Tests


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5.1 Test Setup

The test setups for add-in cards (AIC) and main boards (systems / platforms) differ in the used

fixtures and in the clocking.

5.1.1 Test Setup for Add-In Card RX Test


Terminate all unused data and clock outputs of the J-BERT M8020A.

It is important that all CBB lanes lanes are unterminated. Early versions of the CBB did have

termination resistors on lanes which were not equipped with SMP connectors. Those

termination reisistors have to be removed or the respective pins on the AIC have to be isolated.


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5.1.1.1 Termination Resistor Check / Removal


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5.1.2 Test Setup for System RX Test

Terminate all unused 2.4mm connectors of J-BERT N4903B

Terminate all unused data and clock outputs of the J-BERT M8020A..


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5.2 Pattern Generator Clocking

5.2.1 AIC

In case of AIC testing the J-BERT is the clock master. J-BERT is supplying next data signals as

well as 100MHz reference clock to the CBB. Make sure that the CBB reference clock switch is

set to external reference clock (REFCLK).

PG clock source:

Use the internal clock source

Reference clock settings:

Use the Trigger / Reference Clock Output

Use an offset of 400mV and amplitude of 500mV for the reference clock.

Set a divider of 80 for the Trigger Output


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5.2.2 System

When testing systems the test equipment needs to be synchronous to the system under test

since there is no possibility to force the system under test to run on the reference provided by

the test equipment. In other words the test equipment needs to be able to synchronize to the

100MHz reference clock of the system under test. The preferred method is to use a reference

clock multiplier which has a PLL bandwidth characteristic within the PCI Express gen 3

specification. Make sure that the CLB reference clock switch is set to measure reference clock

(REF CLK MEAS).

5.2.2.1 Clocking of J-BERT N4903B based Setup for Systems Keysight developed the N4880A reference clock multiplier to multiply the 100MHz reference

clock to an acceptable input clock for the J-BERT N4903B pattern generator for PCIe 2.5GT/s,

5GT/s and 8GT/s. For PCIe 8GT/s the N4880A allows running J-BERT on a full rate clock

derived from the 100MHz clock of the system under test enabling testing in presence of SSC. It

allows a separation of the BERT’s PG and ED systems too allowing for more convenient testing.

This includes training of system under tests into test mode since a clock independent of the

transmit speed of the system under test is always provided to the PG.

Connect 100MHz reference clock derived from system under test via CLB to N4880A ref

clock in

Select PCIe gen3, 8000 MHz clock frequency, in the N4880A GUI

Select external clock mode on J-BERT’s PG Bit Rate Setup screen


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If no SSC is active the PG will measure a clock frequency of around 8Gb/s. If a 5000ppm

down spread SSC is active, the PG will measure a clock frequency of around 7.98Gb/s.

5.2.2.2 Clocking of J-BERT M8020A based Setup for Systems The J-BERT M8020A BERT system with M8041A BERT module offers a built-in reference clock

multiplier.

Select Clock Multiplier as clock source in Synthesizer properties

Set Reference Frequency by executing the Measure function

Set Bandwidth to 5MHz

Set multiplier to 80

Set divider to 1


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5.3 Error Detector Clocking

5.3.1 Error Detector Clocking for J-BERT N4903B based Setup

The J-BERT N4903B Error Detector (ED) can be clocked either using the built-in CDR or via an

external clock derived from the main clock out of the pattern generator or from the N4880A

reference clock multiplier using a power divider in case of system test. While the CDR offers

the advantage of being able to track TX jitter of the device under test dependent on loop

bandwidth and peaking settings of the CDR the use of the external clock on the ED provides the

faster auto align. If the CDR is used for clocking it is important to enable or disable SSC

tracking on the CDR dependent if SSC is present on the device under test transmit signal.

5.3.1.1 J-BERT N4903B ED Clock from BERT PG Connect PG main clock out normal to ED clk in and terminate unused main clock output (-).

Set main clock out to 500mV amplitude and 0V offset

Enable external ED clocking in the ED clock setup screen


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5.3.1.2 J-BERT N4903B ED Clock from N4880A Reference Clock Multiplier –

works for PCIe gen 3 only Use a standard 6dB power divider to connect N4880A clock output to PG clk in and ED clk

in

Enable external ED clocking in the ED clock setup screen

5.3.1.3 J-BERT N4903B ED Clock from built-in CDR Select Clock Data Recovery in ED Clock Setup Screen

Set expected data rate to 8Gb/s

Set loop bandwidth to 8MHz

Set fine adjust to 0

Set transition density to 50%

If SSC on DUT TX signal is deactivated:

Uncheck SSC tracking

Set peaking to 0dB

If SSC is enabled on DUT TX signal:


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Enable SSC tracking

Choose correct spread direction. In most cases this will be a down spread. If in doubt

measure SSC spread direction and deviation on RT scope

Set expected SSC deviation

Dependent on the DUT TX output jitter characteristics the CDR loop bandwidth and peaking

might need to be adjusted to get largest eye opening on BERT ED. In case of unexpected

bit errors it is recommended to activate bit recovery mode if installed and to perform an

output timing measurement. The eye height needs to be at least 50mV. If this is not the

case use a repeater and choose correct CTLE settings for the received TX signal. If eye

height is sufficient but if there is no eye margin left at 10-12, adjusting CDR loop bandwidth

and/or peaking are recommended.


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5.3.2 Error Detector Clocking for J-BERT M8020A based Setup

Each error detector (ED) of the M8041A/51A BERT modules of the J-BERT M8020A BERT

system offers a built-in CDR which is used to clock the ED. The CDR offers a 1st order or 2nd

order loop order.

5.3.2.1 J-BERT M8020A CDR Settings in Absence of SSC Set CDR properties in the analyzer parameters CDR section to:

50% transition density

1nd loop order

5MHz loop bandwidth


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5.3.2.2 J-BERT M8020A CDR Settings in Presence of SSC Set CDR properties in the analyzer parameters CDR section to:

50% transition density

2nd loop order

10MHz loop bandwidth

1dB peaking


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5.4 DUT Training

DUTs can be trained by using a static training sequence or by using an interactive link training

in case of the J-BERT M8020A BERT system.

5.4.1 DUT Training using Static Training Sequence

It is highly recommended to use the N5990A-301 PCIe Link Training Suite to setup J-BERT with

the necessary loop back training sequence for the PCIe gen3 device.

The N5990A-301 PCIe Link Training Suite offers two different methods to manipulate the

training sequence. The graphical setup screen is recommended for less experienced users.

Select PCI Express Training Parameters

Set PCIe revision to Gen3 (8.0 GT/s)

Press “Edit Parameters” to get into the sequence screen


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Make necessary changes to the sequence according to the device requirements. A good

starting point are the two Preset Defaults:

CTS Parameters – sequence according to specification

Optimized Parameters – optimized sequence based on workshop experience

it might be necessary to increase the idle time during speed negotiation if the device

under test does not go to 8Gb/s

it might be helpful to enable a manual trigger to start the sequence in J-BERT’s GUI if

the device does enter TX compliance mode or doesn’t get out of polling

The N5990A PCIe Link Training Suite offers a script mode in case a DUT requires

something special which cannot be adjusted in the sequence screen


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It is recommended to use “Apply Pattern Only” after the setup has been calibrated


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5.4.2 DUT Training using Interactive Link Training

The J-BERT M8041A module of the J-BERT M8020A BERT system offers a Link Training

Status State Machine (LTSSM) to train DUTs interactively into loopback. The LTSSM requires

license M8041A-0S1. The LTSSM is represented through three pattern sequence blocks.

4. LinkTrainingDown

This block brings the link down

5. Wait

This block is an idle block an is exit by the break command

6. LinkTrainingUp

This block trains the link from 2.5GT/s to 8GT/s, executes the link eq training and gets the

DUT into loopback. If successful the block exits to the next block. If unsuccessful it

branches back into the LinkTrainingDown block

The link can be trained up through all phases of the link equalization training or the LTSSM can

be setup to bypass phase 2 and phase 3. For tests 2.3, 2.4, 2.7, 2.8 and 2.9 the LTSSM needs

to be setup to bypass phase 2 and phase 3 of the link eq training while tests 2.10 and 2.11

require the full link eq training.


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5.4.2.1 LTSSM Setup for AIC Link Training Parameters:

DUT: Add In Card

Lane: 0

Link: 0

Link Equalization: Bypass (tests 2.3, 2.4 and 2.8) or Full (test 2.10)

Start Preset: P7 or P8 – this is the start preset for the J-BERT M8020A

DUT Preset Hint: Reserved

DUT Initial Preset: Start preset request for the AIC.

For tests 2.3, 2.4 and 2.8 this is the preset at which the test is executed.

DUT Target Preset: This is the preset which is requested from the AIC during phase 3

Setting example for Tests 2.3, 2.4 and 2.8: Setting example for test 2.10:


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5.4.2.2 LTSSM Setup for System Link Training Parameters:

DUT: System Board

Lane: 0

Link: n/a

Link Equalization: Bypass (tests 2.7 and 2.9) or Full (test 2.11)

Start Preset: n/a

DUT Preset Hint: n/a

DUT Initial Preset: n/a

DUT Target Preset: This is the preset which is requested from the system

Setting example for Tests 2.7 and 2.9: Setting example for test 2.11:


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5.5 Error Counter Setup

5.5.1 Error Counter Setup J-BERT N4903B based Setup

The error counter is setup via the ED accumulation setup

Set activation mode to single and period to time and 2s for the bit error rate 10-4 tests and 125s

for the max 1 error in 1012 bit test.

5.5.2 Error Counter Setup J-BERT M8020A based Setup

The Error Ratio measurement in the Measurements drop down menu is used to start the error

counter measurement.

Parameters for error ratio measurement:

Select the analyzer which is connected to the DUT

Set Accumulation End to Full Duration

Choose Fixed Time as Accumulation Duration

Set Accumulation Fixed Time to 125s


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5.5.3 SKP OS Filtering

The J-BERT M8020A based PCIe 8GT/s test setup will always filter SKP OS as long as the

128b/130b pattern type is used on the error detector. This pattern type is used for all PCIe

8GT/s default instrument states which are included in the M8070A SW. The N5990A Test

Automation will use the same pattern type if configured for PCIe 8GT/s testing.

SKP OS filtering for the J-BERT N4903B based setup needs to be activated if the device under

test is changing SKP OS.

To activate SKP OS filtering go to menu ED Error Ratio and change the Error Ratio

selection from Bit Comparison to Bit Comparison without PCIe 3 SKP OS. This functionality is

available for N4903Bs equipped with option A02 and FW version 7.4 or higher.


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5.6 Test Procedure for Test 2.8 and 2.9

7. Configure test setup according to chapter 5.1 without connecting the DUT

8. Configure DUT Training sequence and upload trainings sequence as described in chapter

5.4

9. Set up accumulation period as described in chapter 5.5 for the max 1 error in 1012 bits test

10. Set J-BERT to the stress test values determined in chapter 4 for “DUT provider chosen de-

emphasis setting”

11. Set up J-BERT ED and PG clocking as described in chapter 5.2 and chapter 5.3. For

system test setup the ED clocking first before setting the PG clocking to external.

12. Turn off outputs

13. Connect DUT

14. Turn on outputs

15. Train DUT by resetting the pattern sequence or advancing from block 0 to block 1 if a

sequence is used which waits in block 0

16. Perform an AutoAlign

17. If J-BERT BER display doesn’t show a BER of < 10-4 confirm that training was successful. If

not, modify trainings sequence accordingly and retrain DUT.

18. Start accumulation if BER display shows a BER of 0


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19. If no more than one errors have been counted the DUT passed this test

20. Repeat steps 7 to 16 with calibration settings for (P1), P7 and P8 and change the

accumulation time to 2s according to chapter 5.5. If the recorded Bit Error Ratio in the

accumulated results screen is better than 10-4 the DUT passed this test.


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6 Calibration and Test Flow Chart


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7 Automated Receiver Test Software

7.1 Test Station Configuration

In a first step the test instrument required for the RX tests have to be selected.

In the final step the VISA addresses of the instruments must be assigned and the connections

to the instruments can be tested.


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7.2 DUT Configuration

Before the Calibration and RX Tests can be executed the DUT has to be configured. It has to be

specified if the DUT is an Add-In Card or System and if it is Gen1 / Gen2 or Gen3.

Additional parameters can be changed in a separate dialog. These parameters are:

Channels: Compliance Base Board rev.2 or riser card with CBB rev3

DUT Type: Only for Systems if the DUT is a PCIe Switch. In this case the switch will be

supplied with the 100MHz reference clock by the J-BERT:

Oscilloscope connection type for calibration: direct connections or differential probe on

different oscilloscope channels.

The PCIe Link Training settings file used for loopback training. If the default loopback

training does not work DUT specific training file can be exported with PCIe Link Training

Suite and used by this software.

Error detector CDR settings.


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7.3 Calibration

There are two types of calibration procedures. The first group of calibration procedures has to

be done right behind the pick-off tees:

Equalization Preset Calibration: Calibrates Presets P0 to P7.

Equalization Custom Preset Calibration: Calibrates customer defined pre-shoot / de-

emphasis combinations.


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Random Jitter Calibration: Calibrates RJ over a range:

Sinusoidal Jitter Calibration: Calibrates SJ with different frequencies over a range:

The second group of calibrations has to be done for Add-In Cards with CBB3 riser card

(channel), CBB3, and the Tx output of the CLB3. For Systems the CLB3 has to be used as

channel and the TX outputs of the CBB3 to probe the signal.

DM Sinusoidal Interference Calibration

Eye Height and Eye Width calibration: measures EH and EW for different DMSI and RJ

values. It is used to provide search parameters for the Compliance Eye Calibration.


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Compliance Eye Calibration. This Calibration calculates the right DMSI and RJ values to

obtain the compliance EH and EW using the EH/EW cal data and measures EH and EW. If

EH and EW is not within the specification for the compliance Rx test it will be adjusted. This

can take several steps. When EH and EW meet the specification the RJ and DMSI values

are stored as calibration data.


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7.4 Receiver Tests

There are two groups of Gen3 Rx tests. The first group is done with CBB/CLB rev3. The second

group with CBB/CLB rev2 using the calibration data from the first group.

The RX tests are:

Rx Preset Compliance Test

Mandatory compliance test for Add-In Cards. BER must be below 10-4 for P7 and P8.

Rx Compliance Test

Mandatory compliance test for Add-In Cards and Systems. DUT must run for 125s with

maximum 1 error at one preset.

Sensitivity Rx Test. Characterization Test.

EH is closed step by step by increasing DMSI until DUT generates errors

Jitter Tolerance Rx Test

Characterization Test. SJ is increased step by step until DUT generates errors. This is done

for multiple frequencies.


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7.5 TX EQ Matrix Scan

The TX EQ matrix scan measurement tests all tx eq settings in a brute force method. It is

possible to define the search range of the TX EQ matrix as well as the ber depth and if the DUT

should be retrained per matrix field or not.

7.6 Equalization Scan

Eye height is adjusted for a BER of 10-9. Post cursor as well as pre cursor is swept and ber is

recorded. This measurement can be used as an indicator for a good pre cursor / post cursor

combination for the compliance test.

Documents

PCI Express 3.0 CEM RX Physical Layer Test Method of ...read.pudn.com/downloads794/doc/project/3133918/PCIe Gen 3 CEM RX test... · automated PCIe gen 3.0 CEM receiver (RX) test calibration