PCI Express* 2.0Platform ImplementationsMahesh WaghIntel CorporationMember, PCIe Protocol Workgroup

Today’s TopicsPCIe* Architecture Overview

PCIe 2.0 Update

Future of PCIe Architecture

Call to Action

Signaling bump to 5GFLR, completion TO, etc

Address Translation Services (ATS)Device sharing for Single/Multi-Root (SR/MR)

Performance/power-optimized interface to hostProtocol and SW extensions

New Extensions

IOV

PCIe 2.0

Today’s Focus

PCIe Architecture Overview

PCIe 2.0 Update5GT/s Speed Increase

Link Speed ManagementLink Bandwidth Notification MechanismFunction Level Reset (FLR)Access Control Services (ACS)Completion Timeout Control

Retracted: Trusted Configuration Space (TCS)

PCIe 2.0 (5G)Tight budgets remove all guard bands!All interconnect components specified for enhanced interoperability

PCIe 1.0a: TransmitterPCIe 1.1: PCIe 1.0a + Reference ClockPCIe 2.0: PCIe 1.1 + Channel + Receiver

CEM specification provides electrical interoperability for system board/add-in card

Channel

Transmitter ReceiverPLL PLLTxpins

Rxpins

Coupling caps

ReferenceClock

100MHz

PCIe 2.0 LTSSM ExtensionsExtensions Explanation Benefits

Speed Negotiation Capability to upgrade or downgrade link speed

RAS (improved link uptime), dynamic link speed optimization, power savings (25%+)

Compliance Speed Programmable as well as in-band mechanism to select compliance pattern speed

Flexibility to perform compliance testing at multiple speeds with low cost

Electrical Idle Entry and Exit

Protocol changes to facilitate circuit design

Enhanced robustness, yield, power savings, ease of design (TTM)

Link Width Up-configure

Capability to increase the link width up to the initial trained link width

Power savings

Compliance Entry/Exit

Device Configuration despite link failures

High availability, enhanced robustness

Link Speed ManagementDefault: Trains to the greatest common speed

Software can set an upper bound on the speedHardware can limit speed for link reliability

Hardware is permitted to change the speed autonomously

E.g.: Power managementSoftware can disable

New mechanism supporting software control for entering/exiting Compliance Mode

Link Speed ControlsLink Capability register

Maximum Link Speed field renamed to

Supported Link SpeedsLink Status register

Link Speed field renamed to Current

Link Speed(New) Link Control 2

registerHardware Autonomous

Speed Disable bitEnter Compliance bit

Target Link Speed field

Bandwidth NotificationMechanism for PCIe-aware software to be notified when link bandwidth changes

E.g.: Link retrains to a lower bandwidth due to reliability problemE.g.: Hardware-autonomous link retraining

Logically coupled with Link Speed ManagementRequired for all Root Ports and downstream Switch Ports that support wider than x1 and/or multiple link speeds

BW Notification MechanismLink Capability register

Link Bandwidth Notification Capability bit

Link Control registerLink Autonomous

Bandwidth Interrupt Enable bit

Link Bandwidth Management Interrupt

Enable bitHardware Autonomous

Width Disable bitLink Status register

Link Autonomous Bandwidth Status bit

Link Bandwidth Management Status bit

Function Level ResetNew type of reset

Existing resets may (but not required to) reset function internalsFLR definition requires function internal reset

SW initiated function-specific reset

RESET “FAMILY TREE”

FLRConventional

Cold / Warm(PERST#)

HotS.B.R.

FLR DetailsEndpoints only

All types: Legacy, native, integrated

Register interface simpleImplementation and effects potentially complex

Resets internal function-specific state

Not all architected registers are reset

Hardware initialized (HwInit), BIOS set, etc

F0 F1 F2PCIe EPs

FLR

Access Control ServicesFor downstream ports and multi-function devicesNew Extended Capability and Status/Mask/Severity bits in AERSource validation

Downstream ports range check Requester ID BusNum in upstream Request TLPs

Peer-to-peer controlsDetermine whether to forward directly, block, or redirect peer-to-peer requests to the RC for access validation

ACS considered for functionality defined by the Address Translation Services (ATS) specification

Completion TimeoutRequired: Architected Disable Bit

“Turns off” timeoutNot to be used in normal operation

Optional: Completion Timeout Programmability

Devices indicate supported ranges from the four bins definedTwo selectable ranges for each bin

4s to 64s

250ms to 4s10ms

to 250ms50us

to 10ms

Future Of PCI Express Architecture

Factors Driving PCIe FutureMulti-Everything!

CPUs, multi-core, operating systemsDevice virtualization and sharingMultiple graphics cards

Higher PerformanceNext generation graphics, storage, networking, and fabricsEmerging applications: Math, visualization, content processing, etcNeed for more connectivity: Flexible interconnect width/speedLower power

Technology AdvancesSi processHigh volume manufacturingMaterials

PCIe is the interconnect of choice

OS+LIB/APIs

OS Bus Driver, Cfg, PM, RAS

Link

Applications SW

Device Driver

Math

Visualization

Content Proc.

Signaling Speed Upgrade

Power State Management

BW, Latency and Efficiency

Synch. and Data Exchange

Protocol

Physical

General IO

Communication

OS

PCI SW Model

Device I/F

Apps

PCIe

PCIe Architecture Evolution

Call To ActionInnovate and differentiate your products with PCI Express 2.0 industry specification

Contribute to the evolution of PCI Express architecture

Visit www.pcisig.com for PCI Express specification updates

Additional ResourcesWeb Resources: www.pcisig.com

Related Sessions SYS-T311 – PCI I/O Virtualization Standards – Implementation