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2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements Prelab 4 due Friday Decide on System Improvements Next week: Demo closedloop Voltage Regulation Begin PCB Layout ASAP.  Designs due Wed. Mar 21 st .

PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Page 1: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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1

PCB Layout

ECE 482 Lecture 10

February 28, 2014

Announcements

• Prelab 4 due Friday

– Decide on System Improvements

• Next week: 

– Demo closed‐loop Voltage Regulation

– Begin PCB Layout ASAP.  Designs due Wed. Mar 21st.

Page 2: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Lab 4: PCB Layout

6‐step Trapezoidal Motor Control

Page 3: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Circuit Connections

Page 4: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Basic PCB Layout Concepts

• Trace Resistances

• Kelvin Sensing

• Loop Inductances / Decoupling

• Ground Plane / Return Currents

• Partitioning

Trace Resistance

Page 5: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Trace Sizing Rough Guidelines

Kelvin Sensing

Page 6: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Trace Capacitance

High Impedance Nodes and Capacitive Coupling

Page 7: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Capacitive Shielding

Trace Inductance

Page 8: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Loop Inductances

Loop Inductance: Experiment

Page 9: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Loop Inductance: Experiment

Loop Inductance: Experiment

Page 10: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Page 11: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Op‐amp Pulsed Decoupling

Page 12: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Star‐Grounding Vs. Daisy Chain

Gate Drive Signal Routing

Page 13: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Buck Example Bridge Layout

Example Bridge Layout 

#2

Page 14: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Example Layout Experimental Results

Example Layout #1

Example Layout #2

Gate Drive Resistors

• Inclusion of gate drive resistors slows switching transitions and thus reduces high frequency content in signals

Page 15: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Decoupling Capacitance

Decoupling

Page 16: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Capacitor Packaging

Ground Plane

• Benefits:

– Common reference voltage

– Shielding

– Heat dissipation

– Reduced inductance (increased capacitance)

• Resist urge to cut ground plane as much as possible; consider paths of return currents when cuts are unavoidable

Page 17: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Ground Currents

Acceptable Cuts in Ground Plane

• Cuts that are necessary should be kept short and out of the path of any significant (high frequency) return paths

• Cuts can be used effectively for isolation, and to reduce noise coupled between digital/analog/power circuitry

• Reducing parasitic capacitance in sensitive signal locations (i.e. op‐amp circuitry)

Page 18: PCB Layout - University of Tennesseeweb.eecs.utk.edu/~dcostine/ECE482/Spring2014/lectures/L10_slides.… · 2/27/2014 1 PCB Layout ECE 482 Lecture 10 February 28, 2014 Announcements

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Partitioning

Effective Ground Plane Cuts