PC720 User Manual - Advanced RF & DSP Solutions · UM030 PC720 User Manual r1.10 . UM030 . ... 4 x GTX 33 LVDS or 66 SE JTAG JTAG ... 8 of 37 4.3 GTX Signals MGTXTX[3..0]_115

UM030 PC720 User Manual r1.10

UM030 www.abaco.com page 1 of 37

PC720 User Manual

Abaco Systems

Support Portal

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© Abaco Systems 2017

http://www.abaco.com/

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Revision History Document Revision

Changes Author Peer Review

Quality Approval

Date

r1.0 Initial release N/A N/A N/A 2013-07-01

r1.1 Corrected board dimensions N/A N/A N/A 2013-11-26

r1.2 The SW1 function was wrong and has been corrected. ON and OFF were swapped. Added the PERST# pin location and note about the inversion of this signal.

N/A N/A N/A 2014-03-26

1.3 Reworded descriptions and fixed typos throughout

N/A N/A N/A 2014-03-27

1.4 Fixed pinout of Secondary Interface connecter, Table 6. The FMC168 option (-4) is only valid for PC720 revision 1.2 and above.

N/A N/A N/A 2014-06-05

1.5 Removed change tracking and comments from the Word version of the document

N/A N/A N/A 2014-11-18

1.6 Added details for changes to support a heat sink on the sFMC720

N/A N/A N/A 2015-01-02

1.7 Fixed the ddr3 partnumber to reflect the actual partnumber used (MT41 instead of MT14)

N/A N/A N/A 2015-01-05

1.8 Added option (-5) for fmc230 on secondary side in Table 6.

N/A N/A N/A 2016-01-06

1.9 Added LED status BNO IvK JDS 2016-11-29

1.10 Added note to Appendix C about no guaranteed flash upload using iMPACT Rebranding

Ivk JRo Ivk 2017-03-29




Table of Contents 1 Acronyms and related documents ............................................................................. 4

1.1 Acronyms ................................................................................................................ 4 1.2 Related Documents ................................................................................................. 4

2 Installation ................................................................................................................... 4 2.1 Requirements and handling instructions .................................................................. 4

3 General Description ..................................................................................................... 5 4 Design .......................................................................................................................... 6

4.1 Physical specifications ............................................................................................ 6 4.1.1 Board Dimensions ............................................................................................ 6 4.1.2 Front Panel ...................................................................................................... 6

4.2 I2C Bus Architecture ............................................................................................... 6 4.3 GTX Signals ............................................................................................................ 8 4.4 Primary FMC Interface ............................................................................................ 8 4.5 Secondary FMC Interface ......................................................................................11 4.6 DDR3 Memory .......................................................................................................15 4.7 Clock Tree ..............................................................................................................17

4.7.1 Architecture .....................................................................................................17 4.8 Power Supply .........................................................................................................18 4.9 Fans .......................................................................................................................19 4.10 FPGA Configuration ...............................................................................................19

4.10.1 CPLD JTAG Chain ..........................................................................................19 4.10.2 SPI Flash ........................................................................................................20 4.10.3 CPLD ..............................................................................................................21

4.11 PCIe Interface ........................................................................................................21 4.12 LED status .............................................................................................................23

5 Environment ................................................................................................................23 5.1 Temperature ..........................................................................................................23 5.2 Cooling ...................................................................................................................23

5.2.1 Convection cooling (Standard Option) .............................................................23 5.2.2 Heat Sink cooling (Enhanced FPGA Cooling Option) ......................................24

6 Safety...........................................................................................................................24 7 EMC .............................................................................................................................24 8 Warranty ......................................................................................................................24 Appendix A FPGA Pin Mapping ....................................................................................25 Appendix B PCIe Interface Pinout .................................................................................26 Appendix C FLASH programming using iMPACT ............................................................27 Appendix D Final PC720 Assembly ...................................................................................36




1 Acronyms and related documents

1.1 Acronyms Table 1: Glossary

FBGA Fineline Ball Grid Array FMC FPGA Mezzanine Card

FPGA Field Programmable Gate Array JTAG Join Test Action Group LED Light Emitting Diode

LVDS Low Voltage Differential Signaling MGT Multi-Gigabit Transceiver MSB Most Significant Bit(s) PCB Printed Circuit Board PCI Peripheral Component Interconnect

PCIe PCI Express

1.2 Related Documents • FPGA Mezzanine Card (FMC) standard ANSI/VITA 57.1-2010 • PCI Express Card Electromechanical Specification Revision 2.0 • PCI Express 225W/300W High Power Card Electromechanical Specification Revision

1.0

2 Installation

2.1 Requirements and handling instructions • The PC720 must be installed in a PCI Express 8x connector slot minimum. • The Primary FMC can support up to 3.3V on VADJ/VIO_B. • The Secondary FMC can support up to 1.8V on VADJ/VIO_B. • Prevent electrostatic discharge by observing ESD precautions when handling the

card.




3 General Description The PC720 is a high-performance, half-size PCI Express card with advanced Digital Signal Processing (DSP) capabilities and multiple I/O options. The PC720 offers various direct on-board interface options (2x FMC sites) that are closely coupled to the Kintex-7 and 1GB of DDR3 SDRAM. It is an excellent choice for high-performance applications that require large band signals digitization or generation through the use of accelerated frequency-domain algorithms or video applications that are bandwidth hungry. The PCIe interface can support up to eight high-speed GTX signals, with four primary signals and an additional four signals if they are not required for the secondary or primary FMC interface. The primary method of communication between the FPGA FMCs is by LVDS. The primary FMC is full High Pin-count (HPC) compliant for the LVDS signals, and supports up to four high speed lanes. The secondary FMC is a Low pin-count FMC site with optional support for four high speed lanes.

FMCxxx(Primary)

CPLD

PCIe Switch

PCIe Gen2x8 or x4 PC

Ie

Kintex-7 XC7K160TXC7K325TXC7K410T

FFG676

clocks

XC2C256 CPLDCP132

DDR3 SDRAM512MB

(256Mbx16)

DDR3 SDRAM512MB

(256Mbx16)

256 MbSerial flashs25fl256p

microSD slot

80 L

VDS

or 1

60 S

E

FMC (HPC)VITA 57.1

PCIe

Inte

rface

4x G

TX

4x G

TX

8x GTX

FMCxxx(Secondary)

FMC (LPC)VITA 57.1

4x G

TX

33 L

VDS

or 6

6 SE

JTAG

JTAG

JTAG

2 LVDS or 4 SE

PCIe Switch

4x G

TX

Figure 1: PC720 Block Diagram




4 Design

4.1 Physical specifications

4.1.1 Board Dimensions The PC720 card complies with the PCIe Electromechanical Specifications standard except for the board width which is 205 mm instead of 167 mm. In addition, the restricted component height on the secondary side will not be compliant if a secondary FMC is used. In that case, the adjacent slot on the secondary side cannot be used, as it will be occupied by the secondary FMC. Excluding the PCIe interface, the PC720 is 205mm x 106.65mm. With only an FMC mounted on the Primary side, the PC720 consumes only one slot in a system. Please refer to Appendix D Final PC720 Assembly for more details. NOTE: In some cases, the cooling fans can conflict with the adjacent slot as well. Contact sales for detailed information.

4.1.2 Front Panel Both the Primary and Secondary FMCs have front panel I/Os available on the PCI Express card. Only the secondary FMC has its I/Os on the adjacent slot.

4.2 I2C Bus Architecture The PC720 contains an I2C bus that interfaces to the FPGA, all FMCs, the on-board CPLD, and the PCIe SMBus on the PCIe connector. A NXP PCA9548A I2C mux is used to switch the clock and data lines between all the interfaces. With the I2C bus architecture, the bus master is considered the FPGA. From that point, it is possible to gain access to the PC720 CPLD, which controls the PCIe switch, the VADJ regulator that goes to the Secondary FMC, and the four most significant bits of the LA pins of the same Secondary FMC connector. The hardware selectable address lines [A2:A0] of the PCA9548A are all grounded. Therefore, the PCA9548A slave address is found in Figure 2. Table 2 shows the I2C channels connected to PCA9548A.

1 1 1 0 0 0 0 R/W

Figure 2: PCA9548A Slave address for PC720.

SC#, SD# Connected to

Control Register Bits B3 B2 B1 B0

0 Primary FMC X X X 1 1 Secondary FMC X X 1 X 2 PC720 CPLD X 1 X X 3 PCI Express 1 X X X

Table 2: I2C channel of PCA9548A




FMCxxx(Primary)

Kintex-7 FPGA

XC2C256 CPLDCP132

EEPROM

FMC (HPC)VITA 57.1

PCIe

Inte

rface

SMCL,SMDAT

FMCxxx(Secondary)

FMC (LPC)VITA 57.1

SCL, SDA

SCL,

SD

A

SCL,

SD

A

SCL, SDA

I2C CTL x 2

PCA9548A

PC720 CPLD

GA0

, GA1

GA0

GA1

SCL,SDA

Figure 3: I2C bus Architecture




4.3 GTX Signals

MGTXTX[3..0]_115

MGTXRX[3..0]_115

MGTXTX[3..0]_116

MGTXRX[3..0]_116SW1

Secondary FMC

PER[0..3]

PET[0..3]

PER[4..7]

PET[4..7]

Primary FMC

SW2

IN

OU

TA OU

TB

IN

OUTA

OU

TB

DP[3..0]DP[3..0]

PCIeFPGA

Figure 4: GTX Architecture

The PC720 supports eight GTX signals from bank 115 and 116. Four GTX signals from bank 115 connect to PCIe interface. The other four GTX signals from bank 116 connect to the PCIe interface, the Primary FMC, or the Secondary FMC. The signals from bank 116 can be changed either manually using the DIP switches (SW1 and SW2) or using PCIe_CTL signals from the CPLD. SW 1 and 2 are off by default, which means CPLD controls the switches. Please refer to Figure 10 for the switch location. The default CPLD design does not actively drive these signals, which means they are pulled high. With the default CPLD code, the SW1 and SW2 function will be as described in Table 3. Note that PC720 r1.0 does not have a SW2. The GTX signals connect to either the PCIe interface or the Secondary FMC.

Source SW1 SW2 Connect to

SEC_DP_M2C/C2M [3..0] (Bank 116)

off X PCIe

on on Secondary FMC

on off Primary FMC

Table 3: SW Configuration

4.4 Primary FMC Interface The Kintex-7 FPGA interfaces to an FPGA Mezzanine Card (FMC) via a high pin count (HPC) VITA 57.1 site. Differential routing is applied with matched delay on all pairs. The FMC site provides flexibility for adding analog and/or digital I/O via customer developed, third party, or Abaco Systems FMC boards. Abaco Systems offers a wide variety of FMC cards that can be used on the PC720.




ASP-

1344

86-0

1(F

MC

Carr

ier)

JTAG XilinxXC2C256-7FT256C

CPLD

PrimaryFMC

FPGA(Metal Shielding)

Figure 5: Primary side of the PC720 with FMC attached.

FPGA Pin Net Name

FMC HPC FPGA

Pin Net Name FMC HPC

Pin Number Pin Name Pin

Number Pin Name

F23 CLK0_M2C_N H5 CLK0_M2C_N AF22 HA_N04 F8 HA04_N

G22 CLK0_M2C_P H4 CLK0_M2C_P AE22 HA_P04 F7 HA04_P

F24 CLK1_M2C_N G3 CLK1_M2C_N AE21 HA_N05 E7 HA05_N

G24 CLK1_M2C_P G2 CLK1_M2C_P AD21 HA_P05 E6 HA05_P

R23 CLK2_BIDIR_N K5 CLK2_BIDIR_N AC22 HA_N06 K11 HA06_N

R22 CLK2_BIDIR_P K4 CLK2_BIDIR_P AB22 HA_P06 K10 HA06_P

N23 CLK3_BIDIR_N J3 CLK3_BIDIR_N W24 HA_N07 J10 HA07_N

P23 CLK3_BIDIR_P J2 CLK3_BIDIR_P W23 HA_P07 J9 HA07_P

N22 LA_N00_CC G7 LA00_N_CC AE25 HA_N08 F11 HA08_N

N21 LA_P00_CC G6 LA00_P_CC AD25 HA_P08 F10 HA08_P

P21 LA_N01_CC D9 LA01_N_CC W21 HA_N09 E10 HA09_N

R21 LA_P01_CC D8 LA01_P_CC V21 HA_P09 E9 HA09_P

T25 LA_N02 H8 LA02_N Y21 HA_N10 K14 HA10_N

T24 LA_P02 H7 LA02_P W20 HA_P10 K13 HA10_P

P18 LA_N03 G10 LA03_N Y26 HA_N11 J13 HA11_N

R18 LA_P03 G9 LA03_P Y25 HA_P11 J12 HA11_P

N17 LA_N04 H11 LA04_N AE26 HA_N12 F14 HA12_N

P16 LA_P04 H10 LA04_P AD26 HA_P12 F13 HA12_P

U20 LA_N05 D12 LA05_N AF23 HA_N13 E13 HA13_N

U19 LA_P05 D11 LA05_P AE23 HA_P13 E12 HA13_P

T17 LA_N06 C11 LA06_N V22 HA_N14 J16 HA14_N




U17 LA_P06 C10 LA06_P U22 HA_P14 J15 HA14_P

P20 LA_N07 H14 LA07_N AF25 HA_N15 F17 HA15_N

P19 LA_P07 H13 LA07_P AF24 HA_P15 F16 HA15_P

N24 LA_N08 G13 LA08_N AC26 HA_N16 E16 HA16_N

P24 LA_P08 G12 LA08_P AB26 HA_P16 E15 HA16_P

R20 LA_N09 D15 LA09_N AA22 HA_N17_CC K17 HA17_N_CC

T20 LA_P09 D14 LA09_P Y22 HA_P17_CC K16 HA17_P_CC

R17 LA_N10 C15 LA10_N W26 HA_N18_CC J19 HA18_N

R16 LA_P10 C14 LA10_P W25 HA_P18_CC J18 HA18_P

L24 LA_N11 H17 LA11_N AC21 HA_N19 F20 HA19_N

M24 LA_P11 H16 LA11_P AB21 HA_P19 F19 HA19_P

M20 LA_N12 G16 LA12_N AB25 HA_N20 E19 HA20_N

N19 LA_P12 G15 LA12_P AA25 HA_P20 E18 HA20_P

T23 LA_N13 D18 LA13_N V26 HA_N21 K20 HA21_N

T22 LA_P13 D17 LA13_P U26 HA_P21 K19 HA21_P

M19 LA_N14 C19 LA14_N V24 HA_N22 J22 HA22_N

N18 LA_P14 C18 LA14_P V23 HA_P22 J21 HA22_P

M26 LA_N15 H20 LA15_N U25 HA_N23 K23 HA23_N

N26 LA_P15 H19 LA15_P U24 HA_P23 K22 HA23_P

M22 LA_N16 G19 LA16_N E17 HB_N00_CC K26 HB00_N_CC

M21 LA_P16 G18 LA16_P F17 HB_P00_CC K25 HB00_P_CC

E23 LA_N17_CC D21 LA17_N_CC F15 HB_N01 J25 HB01_N

F22 LA_P17_CC D20 LA17_P_CC G15 HB_P01 J24 HB01_P

D24 LA_N18_CC C23 LA18_N_CC J19 HB_N02 F23 HB02_N

D23 LA_P18_CC C22 LA18_P_CC J18 HB_P02 F22 HB02_P

K22 LA_N19 H23 LA19_N K18 HB_N03 E22 HB03_N

L22 LA_P19 H22 LA19_P L17 HB_P03 E21 HB03_P

A24 LA_N20 G22 LA20_N L18 HB_N04 F26 HB04_N

A23 LA_P20 G21 LA20_P M17 HB_P04 F25 HB04_P

J25 LA_N21 H26 LA21_N K17 HB_N05 E25 HB05_N

J24 LA_P21 H25 LA21_P K16 HB_P05 E24 HB05_P

C26 LA_N22 G25 LA22_N D18 HB_N06_CC K29 HB06_N_CC

D26 LA_P22 G24 LA22_P E18 HB_P06_CC K28 HB06_P_CC

C22 LA_N23 D24 LA23_N D20 HB_N07 J28 HB07_N

D21 LA_P23 D23 LA23_P D19 HB_P07 J27 HB07_P

H24 LA_N24 H29 LA24_N L20 HB_N08 F29 HB08_N

H23 LA_P24 H28 LA24_P L19 HB_P08 F28 HB08_P

H22 LA_N25 G28 LA25_N F20 HB_N09 E28 HB09_N

J21 LA_P25 G27 LA25_P G19 HB_P09 E27 HB09_P

A20 LA_N26 D27 LA26_N A17 HB_N10 K32 HB10_N

B20 LA_P26 D26 LA26_P B17 HB_P10 K31 HB10_P




E22 LA_N27 C27 LA27_N C18 HB_N11 J31 HB11_N

E21 LA_P27 C26 LA27_P C17 HB_P11 J30 HB11_P

H26 LA_N28 H32 LA28_N J16 HB_N12 F32 HB12_N

J26 LA_P28 H31 LA28_P J15 HB_P12 F31 HB12_P

J23 LA_N29 G31 LA29_N E20 HB_N13 E31 HB13_N

K23 LA_P29 G30 LA29_P F19 HB_P13 E30 HB13_P

B21 LA_N30 H35 LA30_N B19 HB_N14 K35 HB14_N

C21 LA_P30 H34 LA30_P C19 HB_P14 K34 HB14_P

G21 LA_N31 G34 LA31_N B16 HB_N15 J34 HB15_N

H21 LA_P31 G33 LA31_P C16 HB_P15 J33 HB15_P

E26 LA_N32 H38 LA32_N G16 HB_N16 F35 HB16_N

F25 LA_P32 H37 LA32_P H16 HB_P16 F34 HB16_P

A22 LA_N33 G37 LA33_N H18 HB_N17_CC K38 HB17_N_CC

B22 LA_P33 G36 LA33_P H17 HB_P17_CC K37 HB17_P_CC

AA24 HA_N00_CC F5 HA00_N_CC A19 HB_N18 J37 HB18_N

Y23 HA_P00_CC F4 HA00_P_CC A18 HB_P18 J36 HB18_P

AC24 HA_N01_CC E3 HA01_N_CC G20 HB_N19 E34 HB19_N

AC23 HA_P01_CC E2 HA01_P_CC H19 HB_P19 E33 HB19_P

AD24 HA_N02 K8 HA02_N E16 HB_N20 F38 HB20_N

AD23 HA_P02 K7 HA02_P E15 HB_P20 F37 HB20_P

AB24 HA_N03 J7 HA03_N F18 HB_N21 E37 HB21_N

AA23 HA_P03 J6 HA03_P G17 HB_P21 E36 HB21_P

K6 GBTCLK1_M2C_P D4 GBTCLK0_M2C_P

K5 GBTCLK1_M2C_N D5 GBTCLK0_M2C_N

F2 SEC_DP0_M2C_P C6 DP0_M2C_P G4 SEC_DP0_C2M_P C2 DP0_C2M_P

F1 SEC_DP0_M2C_N C7 DP0_M2C_N G3 SEC_DP0_C2M_N C3 DP0_C2M_N

D2 SEC_DP1_M2C_P A2 DP1_M2C_P E4 SEC_DP1_C2M_P A22 DP1_C2M_P

D1 SEC_DP1_M2C_N A3 DP1_M2C_N E3 SEC_DP1_C2M_N A23 DP1_C2M_N

B2 SEC_DP2_M2C_P A6 DP2_M2C_P C4 SEC_DP2_C2M_P A26 DP2_C2M_P

B1 SEC_DP2_M2C_N A7 DP2_M2C_N C3 SEC_DP2_C2M_N A27 DP2_C2M_N

A4 SEC_DP3_M2C_P A10 DP3_M2C_P B6 SEC_DP3_C2M_P A30 DP3_C2M_P

A3 SEC_DP3_M2C_N A11 DP3_M2C_N B5 SEC_DP3_C2M_N A31 DP3_C2M_N

Table 4: Primary FMC Pinout

4.5 Secondary FMC Interface The PC720 offers a secondary FMC connector which connects four MGT signals and up to 32 LVDS signals. The secondary FMC acts as a supplemental FMC and is accessible through a PC-FMC-ADAPTER (not by default included). The secondary FMC is a Low Pin Count (LPC) FMC site with limitations.




ERM8-

SunonUF3H3-700

(3V-DC 17x17x3mm)

SunonUF3H3-700

(3V-DC 17x17x3mm)

FMCCarrier

SecondaryFMC

Figure 6: Secondary FMC with adapter card

The limitations depend on the FMC specified at the time of ordering. Table 5 lists the limitations per FMC type. In addition in all configurations the following signals are not available to the FPGA:

- PRSNT_M2C_L - PG_M2C - PG_C2M

For FPGA pin mapping information, first find the adapter type in Table 5 and then refer to the applicable column in Table 6.

Table 5. Limitations on secondary FMC site per FMC type

FMC specified at time of order:

Adapter Type: Limitations:

No FMC specified PC_FMC_ADAPTER-1 CLK1_M2C_P/N not available

LA32_P/N not available

LA33_P/N not available

FMC150, FMC151 PC_FMC_ADAPTER-0 External trigger input not available

Monitoring interrupt not available

FMC30RF PC_FMC_ADAPTER-1 None

FMC112 PC_FMC_ADAPTER-1 External trigger input not available

External trigger output not available



1 Customers with a PC720 r1.1 or earlier received a PC-FMC-ADAPTER-1 which does not offer




FMC122 PC_FMC_ADAPTER-2 Bit 0 not connected (7 bit instead of 8 bit)

(no limitation when DMUX 1:1 mode is used)

FMC10x PC_FMC_ADAPTER-3 None


Clk_to_FPGA not available

DAC1 not available

Table 6. FPGA Pinout per PC_FMC_ADAPTER type FPGA pin per PC_FMC_ADAPTER FMC Signal FMC Pin -0 -1 -2 -3 -4 -5 CLK0_M2C_N H5 AD18 AD18 AD18 NC NC NC CLK0_M2C_P H4 AC18 AC18 AC18 NC NC NC CLK1_M2C_N G3 NC NC NC AD18 NC NC CLK1_M2C_P G2 NC NC NC AC18 NC NC LA00_N_CC G7 AC17 AC17 AC17 AC17 AC17 AC17 LA00_P_CC G6 AB17 AB17 AB17 AB17 AB17 AB17 LA01_N_CC D9 W14 W14 NC NC W14 W14 LA01_P_CC D8 V14 V14 NC NC V14 V14 LA02_N H8 V19 V19 V19 V19 V19 V19 LA02_P H7 V18 V18 V18 V18 V18 V18 LA03_N G10 W16 W16 W16 W16 W16 W16 LA03_P G9 W15 W15 W15 W15 W15 W15 LA04_N H11 W19 W19 W19 W19 W19 W19 LA04_P H10 W18 W18 W18 W18 W18 W18 LA05_N D12 V17 V17 V17 V17 V17 V17 LA05_P D11 V16 V16 V16 V16 V16 V16 LA06_N C11 Y18 Y18 Y18 Y18 Y18 Y18 LA06_P C10 Y17 Y17 Y17 Y17 Y17 Y17 LA07_N H14 AB20 AB20 AB20 AB20 AB20 AB20 LA07_P H13 AB19 AB19 AB19 AB19 AB19 AB19 LA08_N G13 AD19 AD19 AD19 AD19 AD19 AD19 LA08_P G12 AC19 AC19 AC19 AC19 AC19 AC19 LA09_N D15 AA20 AA20 AA20 AA20 AA20 AA20 LA09_P D14 AA19 AA19 AA19 AA19 AA19 AA19 LA10_N C15 AE20 AE20 AE20 AE20 AE20 AE20 LA10_P C14 AD20 AD20 AD20 AD20 AD20 AD20 LA11_N H17 AB15 AB15 AB15 AB15 AB15 AB15 LA11_P H16 AB14 AB14 AB14 AB14 AB14 AB14 LA12_N G16 AD14 AD14 AD14 AD14 AD14 AD14 LA12_P G15 AC14 AC14 AC14 AC14 AC14 AC14

channel H on FMC168.




LA13_N D18 AA15 AA15 AA15 AA15 AA15 AA15 LA13_P D17 AA14 AA14 AA14 AA14 AA14 AA14 LA14_N C19 AE15 AE15 AE15 AE15 AE15 AE15 LA14_P C18 AD15 AD15 AD15 AD15 AD15 AD15 LA15_N H20 AF20 AF20 AF20 AF20 AF20 AF20 LA15_P H19 AF19 AF19 AF19 AF19 AF19 AF19 LA16_N G19 AE16 AE16 AE16 AE16 AE16 AE16 LA16_P G18 AD16 AD16 AD16 AD16 AD16 AD16 LA17_N_CC D21 AC16 AC16 AC16 AC16 NC AC16 LA17_P_CC D20 AB16 AB16 AB16 AB16 NC AB16 LA18_N_CC C23 AA18 AA18 NC NC AA18 AA18 LA18_P_CC C22 AA17 AA17 NC NC AA17 AA17 LA19_N H23 AF18 AF18 AF18 AF18 AF18 AF18 LA19_P H22 AE18 AE18 AE18 AE18 AE18 AE18 LA20_N G22 Y16 Y16 Y16 Y16 Y16 Y16 LA20_P G21 Y15 Y15 Y15 Y15 Y15 Y15 LA21_N H26 AF17 AF17 AF17 AF17 AF17 AF17 LA21_P H25 AE17 AE17 AE17 AE17 AE17 AE17 LA22_N G25 AF15 AF15 AF15 AF15 AF15 AF15 LA22_P G24 AF14 AF14 AF14 AF14 AF14 AF14 LA23_N D24 G14 G14 G14 G14 G14 G14 LA23_P D23 H14 H14 H14 H14 H14 H14 LA24_N H29 H13 H13 H13 H13 H13 H13 LA24_P H28 J13 J13 J13 J13 J13 J13 LA25_N G28 E12 E12 E12 E12 E12 E12 LA25_P G27 E13 E13 E13 E13 E13 E13 LA26_N D27 D13 D13 D13 D13 D13 D13 LA26_P D26 D14 D14 D14 D14 D14 D14 LA27_N C27 F13 F13 F13 F13 F13 F13 LA27_P C26 F14 F14 F14 F14 F14 F14 LA28_N H32 A14 A14 A14 A14 A14 A14 LA28_P H31 B14 B14 B14 B14 B14 B14 LA29_N G31 C13 C13 C13 C13 C13 C13 LA29_P G30 C14 C14 C14 C14 C14 C14 LA30_N H35 A15 A15 A15 A15 A15 A15 LA30_P H34 B15 B15 B15 B15 B15 B15 LA31_N G34 NC A12 A12 A12 A12 A12 LA31_P G33 F13 A13 A13 A13 A13 A13 LA32_N H38 NC NC W14 W14 AC16 AD18 LA32_P H37 A12 NC V14 V14 AB16 AC18 LA33_N G37 NC NC AA18 AA18 AD18 NC LA33_P G36 A13 NC AA17 AA17 AC18 NC DP0_C2M_N C3 G3 G3 G3 G3 G3 G3 DP0_C2M_P C2 G4 G4 G4 G4 G4 G4




DP0_M2C_N C7 F1 F1 F1 F1 F1 F1 DP0_M2C_P C6 F2 F2 F2 F2 F2 F2 DP1_C2M_N A23 E3 E3 E3 E3 E3 E3 DP1_C2M_P A22 E4 E4 E4 E4 E4 E4 DP1_M2C_N A3 D1 D1 D1 D1 D1 D1 DP1_M2C_P A2 D2 D2 D2 D2 D2 D2 DP2_C2M_N A27 C3 C3 C3 C3 C3 C3 DP2_C2M_P A26 C4 C4 C4 C4 C4 C4 DP2_M2C_N A7 B1 B1 B1 B1 B1 B1 DP2_M2C_P A6 B2 B2 B2 B2 B2 B2 DP3_C2M_N A31 B5 B5 B5 B5 B5 B5 DP3_C2M_P A30 B6 B6 B6 B6 B6 B6 DP3_M2C_N A11 A3 A3 A3 A3 A3 A3 DP3_M2C_P A10 A4 A4 A4 A4 A4 A4 GBTCLK0_M2C_N D5 F5 F5 F5 F5 F5 F5 GBTCLK0_M2C_P D4 F6 F6 F6 F6 F6 F6

4.6 DDR3 Memory Two DDR3 memory devices interface to the Kintex-7 through its Banks 33 and 34. The memory interface is tested at 400 MHz. Selecting a faster FPGA speed grade allows higher frequencies. The DDR3 memory devices used are the Micron MT41J256M16-HA-15EIT:E.

DDR3 #1

FPGA

DDR3_DM[1..0]

DDR3_DQS_P/N[1..0]

DDR3 #2

DDR3_DQ[15..0]

DDR3_DM[3..2]

DDR3_DQS_P/N[3..2]

DDR3_DQ[31..16]

DDR3_CK_P/NDDR3_CS_NDDR3_CKEDDR3_ODT

DDR3_BA[2..0]DDR3_RAS_NDDR3_CAS_NDDR3_WE_N

DDR3_RESET_N

Figure 7: PC720 DDR3 Diagram

FPGA DDR3 #1 FPGA DDR3 #2

Net Name Pin Pin Net Name Pin Pin




DDR3_DM[0] U6 E7 DDR3_DM[2] AA4 E7

DDR3_DM[1] Y3 D3 DDR3_DM[3] AD4 D3

DDR3_DQS_P[0] W6 F3 DDR3_DQS_P[2] AA5 F3

DDR3_DQS_N[0] W5 G3 DDR3_DQS_N[2] AB5 G3

DDR3_DQS_P[1] AB1 C7 DDR3_DQS_P[3] AF5 C7

DDR3_DQS_N[1] AC1 B7 DDR3_DQS_N[3] AF4 B7

DDR3_DQ[0] U5 E3 DDR3_DQ[16] AB4 E3

DDR3_DQ[1] U2 F7 DDR3_DQ[17] AC4 F7

DDR3_DQ[2] U1 F2 DDR3_DQ[18] AC3 F2

DDR3_DQ[3] V3 F8 DDR3_DQ[19] AB6 F8

DDR3_DQ[4] W3 H3 DDR3_DQ[20] AC6 H3

DDR3_DQ[5] U7 H8 DDR3_DQ[21] Y6 H8

DDR3_DQ[6] V6 G2 DDR3_DQ[22] Y5 G2

DDR3_DQ[7] V4 H7 DDR3_DQ[23] AD6 H7

DDR3_DQ[8] Y2 D7 DDR3_DQ[24] AD1 D7

DDR3_DQ[9] V2 C3 DDR3_DQ[25] AE1 C3

DDR3_DQ[10] V1 C8 DDR3_DQ[26] AE3 C8

DDR3_DQ[11] W1 C2 DDR3_DQ[27] AE2 C2

DDR3_DQ[12] Y1 A7 DDR3_DQ[28] AE6 A7

DDR3_DQ[13] AB2 A2 DDR3_DQ[29] AE5 A2

DDR3_DQ[14] AC2 B8 DDR3_DQ[30] AF3 B8

DDR3_DQ[15] AA3 A3 DDR3_DQ[31] AF2 A3

Shared Resources to Memory Devices

DDR3_CK_P W10 J7 J7

DDR3_CK_N W9 K7 K7

DDR3_CS_N AD9 L2 L2

DDR3_CKE AA10 K9 K9

DDR3_ODT AB10 K1 K1

DDR3_ADDR[14] V11 T7 T7

DDR3_ADDR[13] W11 T3 T3

DDR3_ADDR[12] V8 N7 N7

DDR3_ADDR[11] V7 R7 R7

DDR3_ADDR[10] Y8 L7 L7

DDR3_ADDR[9] Y7 R3 R3

DDR3_ADDR[8] Y11 T8 T8




DDR3_ADDR[7] Y10 R2 R2

DDR3_ADDR[6] V9 R8 R8

DDR3_ADDR[5] W8 P2 P2

DDR3_ADDR[4] AE7 P8 P8

DDR3_ADDR[3] AF7 N2 N2

DDR3_ADDR[2] AA8 P3 P3

DDR3_ADDR[1] AA7 P7 P7

DDR3_ADDR[0] AC8 N3 N3

DDR3_BA[2] AD8 M3 M3

DDR3_BA[1] AB7 N8 N8

DDR3_BA[0] AC7 M2 M2

DDR3_RAS_N AA9 J3 J3

DDR3_CAS_N AB9 K3 K3

DDR3_WE_N AC9 L3 L3

DDR3_RESET_N AA2 T2 T2

Table 7: PC720 DDR3 interface

4.7 Clock Tree

4.7.1 Architecture The PC720 uses a 50 MHz single-ended oscillator to support the CPLD functionality. Furthermore, the FPGA receives clock signals that originate from the two FMCs and the PCIe connector. The clock signals between the Secondary FMC and the FPGA are restricted in voltage so as not to damage the FPGA pins. The voltage levels are limited to 1.8V LVCMOS or LVDS signalling levels.




Kintex-7

SiT8004133 MHzOscillator

VITA 57.1FMC

GBTCLK0

MGTREFCL0P/N_115

MGTREFCL1P/N_115

CLK0_M2C

CLK1_M2C

CLK2_BIDIR_x

CLK3_BIDIR_x

IO_L13x_T2_MRCC_14

IO_L15x_T2_DQS_xxxxxxx_14

IO_L14x_T2_SRCC_14


MGTREFCL0P/N_116

MGTREFCL1P/N_116

SecondaryInterface

EXT_GBTCLK0_M2C_x


CCLK_0

IO_L13x_T2_MRCC_33 IO_L13x_T2_MRCC_16IO_L15x_T2_DQS_32 CLK0_M2C

13_x_MRCC_Bank16

SPIFlash256Mb

SCK

IO_L9x_T1_DQS_xxx_14

EMCCLK

PCIe

PC720CPLD 50 Mhz

XC2C256 CPLDCP132

(SYS_CLK)

Figure 8: PC720 Clock Architecture

FPGA Pin Net name Bank FPGA Pin Net name Bank

H5 GBTCLK0_M2C_N 115 F23 CLK0_M2C_N 14

H6 GBTCLK0_M2C_P 115 G22 CLK0_M2C_P 14

K5 GBTCLK1_M2C_N 115 F24 CLK1_M2C_N 14

K6 GBTCLK1_M2C_P 115 G24 CLK1_M2C_P 14

D5 MGTREFCL0_N_116 116 R23 CLK2_BIDIR_N 13

D6 MGTREFCL0_P_116 116 R22 CLK2_BIDIR_P 13

F5 SEC_GBTCLK1_M2C_N 116 N23 CLK3_BIDIR_N 13

F6 SEC_GBTCLK1_M2C_P 116 P23 CLK3_BIDIR_P 13

AC11 SYS_CLK_N 33 B20 EMCCLK 14

AB11 SYS_CLK_P 33 C8 CCLK 0

AD18 SEC_CLK0_M2C_N 32

AC18 SEC_CLK0_M2C_P 32

Table 8: Clock Pinout

4.8 Power Supply Power is supplied to the PC720 through the PCIe connector (default). It is then distributed to the Primary and Secondary FMCs.




Optionally, it is possible use a PCIe 2x4 auxiliary power connector. Contact sales for more information. The power rails supplied by the PCIe connector are 12V, 3.3V and 3.3Vaux.

Power Rail Current Tolerance Capacitive Load

+3.3 V 3.0 A (max) ±9% 1000 µF +12 V 5.5 A (max) ±8% 1000 µF

+3.3Vaux 375 mA (max) ±9% 150 µF Table 9: PCIe Connector Power Supply Rail

Abaco Systems recommends using the PCIe connector as a main power source.

4.9 Fans In addition to supporting the FMCs and FPGA, the PC720 can support up to three fans: one 30x30mm fan for the FPGA and DDR3 memories and two 17x17mm fans for the primary and secondary FMCs. The PC-FMC-ADAPTER card can also use fans for additional airflow.

4.10 FPGA Configuration

4.10.1 CPLD JTAG Chain The JTAG chain on the PC720 is available for configuration and debugging purposes. The PC720 CPLD is used as JTAG control logic between the PCIe connector, the JTAG connector (Molex), two FMC connectors, and FPGA. CPLD detects the signals of each connector and determines the correct JTAG chain. Xilinx Platform USB-II is required to configure the FPGA. How to program the FPGA?

- Connect a Xilinx Platform USB-II to the host computer. - Connect a Xilinx JTAG RIBBON cable between JTAG RIBBON connector on PC720

and Xilinx Platform USB-II. - Open iMPACT and initialize the JTAG chain.




PC720 FPGA

PCIe

Con

nect

or

SecondaryFMC

PrimaryFMC

4.7k

3.3V

FMC Connector (HPC)

D30TDI

D31TDO

D29TCK

D33TM

S

H2PRSN

T_M2C_L

ERF8/ERM8-30Interfaces to FMC Connector

12TDI

16TDO

4TCK

8TM

S

24PRSN

T_M2C_L

JTAG

Con

nect

or(M

olex

)

6TCK

4TMS

10TDI

8TDO

A6TDI

A7TDO

A5TCK

A8TMS

4.7k

3.3V

PC720CPLD

JTAG Connector

(Press-Fit)

xTCK

xTMS

xTDI

xTDO

13PGND

4.7k

3.3V

XC2C256 CPLDCP132

TMS

TCK

TDI

TDO

TDI

TDO

Figure 9: JTAG chain design

JTAGRIBBONCONN

JTAGHeader

SW2SW1

Figure 10: Connector and Switch locations

4.10.2 SPI Flash The 256Mb SPI serial flash is used to store the Kintex-7 FPGA image. It is possible to program the flash directly from the JTAG chain using Xilinx tool “iMPACT”. Please refer to Appendix C FLASH programming using iMPACT for details on configuring the SPI flash using this tool. Additionally, Abaco Systems offers a reference design that allows configuration of the flash over the PCI express connector using the Abaco Systems software tools. Refer to the software getting started guide for information how to configure the flash over the PCI Express bus.




Please note that the FPGA will configure itself using master SPI mode. The ISE bitstream generation settings target a master SPI clock of 3 MHz by default. The PC720 supports a maximum master SPI clock of 16 MHz when the SPI falling edge mode is also selected. For the fastest possible power on configuration time, the bitstream compression should also be enabled. NOTE: power up configuration can take between two and eight seconds depending on your FPGA image size and the configuration clock frequency. In some cases this is not fast enough to ensure proper detection of the FPGA by the host computer. You can: - try to slow down the BIOS - restart / reset the computer after the FPGA has loaded from flash.

4.10.3 CPLD The CPLD uses its own JTAG chain, by way of the press-fit interface, in order to be programmed. The default factory program provides the CPLD with several functions: a buffer and multiplexer for the JTAG chain to the PCIe interface and FMC interfaces; control of the VADJ regulator for the Secondary FMC; control of the PCIe switch for the high-speed signals from the FPGA Secondary Connector; and an interface to the LA32_P/N and LA33_P/N signals of the Secondary FMC. Within the CPLD, an I2C core is used to control the enable pin of the VADJ regulator and adjust its values, as well as to control the PCIe switch. With this capability, the FPGA can then control these devices by way of the CPLD. The I2C is also used to read and write to the LA32 and LA33 bits of the Secondary FMC. How to program the CPLD?

- This should not be done without contacting Abaco Systems. - Connect a Xilinx Platform USB-II to the host computer. - Connect a Xilinx JTAG cable between JTAG header and Xilinx Platform USB-II. - Open iMPACT and initialize the JTAG chain.

4.11 PCIe Interface The Kintex-7 devices can support the PCIe x1, x2, and x4 Gen2 lane widths on all the devices. Furthermore, FPGA devices that are not -1 parts can support x8 Gen 2. From the FPGA, the high-speed (DP) signals will start at DP0 for the x1 up to DP3 for the x4 lanes. For the x8




capability, the high-speed signals on the Secondary connector are accessed using the PCIe switch (SW1). The signals from the PCIe switch can be changed either manually using the DIP switch or using PCIe_CTL signals from the CPLD. SW1 is off by default, which means PCIe_CTL is pulled-up high and all 8 lanes connect to the PCIe card edge connector.

FPGA Pin PCIe Bank FPGA Pin PCIe (SW1: OFF) Bank

H5 REFCLK_P 115 G3 PETn4 116 H6 REFCLK_N 115 G4 PETp4 116 J3 PETn3 115 F1 PERn4 116 J4 PETp3 115 F2 PERp4 116 H1 PERn3 115 E3 PETn5 116 H2 PERp3 115 E4 PETp5 116 L3 PETn2 115 D1 PERn5 116 L4 PETp2 115 D2 PERp5 116 K1 PERn2 115 C3 PETn6 116 K2 PERp2 115 C4 PETp6 116 N3 PETn1 115 B1 PERn6 116 N4 PETp1 115 B2 PERp6 116 M1 PERn1 115 B5 PETn7 116 M2 PERp1 115 B6 PETp7 116 R3 PETn0 115 A3 PERn7 116 R4 PETp0 115 A4 PERp7 116 P1 PERn0 115 P2 PERp0 115 K21 PERST#1 14

Table 10: PCIe Pinout

NOTE 1: the PERST# signal from the card edge connector is inverted before it arrives at the FPGA. The signal therefore must be inverted before connecting it to a default PCI Express core.




4.12 LED status The LED status on the board inside the shielding are solely for Abaco Systems testing purposes, do not draw conclusions based on the status of these LEDs.

DS1 (red)

ON: Power Good Blinking: Power not Good OFF: CPLD in reset

DS2 (red)

ON: Vadj secondary side Power Good OFF: CPLD in reset

DS3 (red)

ON: power on secondary side disabled OFF: power on secondary side enabled (can be ignored for PC720 without a secondary side)

DS4 (red)

Blinking: CPLD in reset Not blinking: CPLD not in reset

DS5 (green)

ON: 12V Power Good OFF: 12V Power Not Good

DS6 (green)

ON: 12V_AUX Power Good OFF: 12V_AUX Power Not Good

DS7 (green)

ON: 3.3V Power Good OFF: 3.3V Power Not Good

DS8 (green)

ON: 3.3V_AUX Power Good OFF: 3.3V_AUX Power Not Good

5 Environment

5.1 Temperature Operating temperature

• -40°C to +85°C (Industrial) Storage temperature:

• -40°C to +120°C

5.2 Cooling

5.2.1 Convection cooling (Standard Option) Underneath all the FMCs on the secondary side of the PC720, 3-V fans are used to cool devices. Because the adapter card restricts fan height for the Primary and Secondary FMCs, the fan height is set to 3 mm. Two fan locations are present under both FMCs to allow for air flow and/or an additional fan to be placed. Each fan uses about 37 mA (.10W) to create 0.57 CFM.




A 30mm x 30mm fan is used for the FPGA. The 12-V fan uses approximately 100 mA (1.2W) to create 5.0 CFM. The fans for the FPGA and the Primary FMC are mounted to the PC720. The fan to the Secondary FMC is mounted to the PC-FMC-ADAPTER. Abaco Systems’s warranty does not cover boards on which the maximum allowed temperature has been exceeded.

5.2.2 Heat Sink cooling (Enhanced FPGA Cooling Option) For applications where the on-board FPGA requires additional cooling, a heat sink is available. To support the heat sink, the 30mm x 30mm FAN must be moved to the bottom side of the PC720. It is important to note that making this change to the PC720 assembly will cause a violation of the PCIe specifications with regard to the bottom side maximum component height. The PCIe specification allows components with a maximum height of 2.67mm, the actual height of the FAN will be approximately 7-8mm (see Appendix D Final PC720 Assembly for details). Careful examination of clearances will be required if another card must be installed in the host system next to the PC720. The heat sink option needs to be specified at the time of order.

6 Safety This module presents no hazard to the user.

7 EMC This module is designed to operate within an enclosed host system built to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system.

8 Warranty

Hardware Software/Firmware

Basic Warranty (included) 1 Year from Date of Shipment 90 Days from Date of Shipment

Extended Warranty (optional)

2 Years from Date of Shipment Year from Date of Shipment




Appendix A FPGA Pin Mapping

Secondary FMC

ConnectorBank 32 (HP)

Secondary FMC ConnectorBank 116 (MGT) – DP (optionally to PCIe or primary FMC)

Bank 16 (HR)

Primary FMCConnector

Bank 12-HBBank 14 – Configuration

Banks 13, 14, 15 – LA, HA

PCIeConnectorBank 115 (MGT)

DDR3 512MBBank 34 (HP) – DDR3 DQ

Bank 33 (HP) – DDR3 ADDR, CTL




Appendix B PCIe Interface Pinout Pin # Side B Side A Pin # Side B Side A

1 +12V PRSNT1# 25 GND PERp2 2 +12V +12V 26 GND PERn2 3 +12V +12V 27 PETp3 GND 4 GND GND 28 PETn3 GND

5 SMCLK JTAG2 (TCK) 29 GND PERp3

6 SMDAT JTAG3 (TDI) 30 RSVD PERn3

7 GND JTAG4 (TDO) 31 PRSNT2# GND

8 +3.3V JTAG5 (TMS) 32 GND RSVD

9 JTAG1 (TRST#) +3.3V 33 PETp4 RSVD

10 3.3VAUX +3.3V 34 PETn4 GND 11 WAKE# PERST# 35 GND PERp4

36 GND PERn4 12 RSVD GND 37 PETp5 GND 13 GND REFCLK+ 38 PETn5 GND 14 PETp0 REFCLK- 39 GND PERp5 15 PETn0 GND 40 GND PERn5 16 GND PERp0 41 PETp6 RSVD 17 PRSNT2# PERn0 42 PETn6 GND 18 GND GND 43 GND PERp6 19 PETp1 RSVD 44 GND PERn6 20 PETn1 GND 45 PETp7 GND 21 GND PERp1 46 PETn7 GND 22 GND PERn1 47 GND PERp7 23 PETp2 GND 48 PRSNT2# PERn7 24 PETn2 GND 49 GND GND




Appendix C FLASH programming using iMPACT NOTE: flash programming using iMPACT is not guaranteed to work since the CPLD sits between the FPGA and the configuration flash (refer to Figure 1). This setup does not follow the recommended configuration schemes provided by Xilinx. iMPACT loads an enhanced programming file into the FPGA that allows access to the flash, and the user will not have any control over the timing of this enhanced bit file. A fault condition might appear during the programming because the CPLD has an effect on the timing of the SPI interface to the flash device. Therefore Abaco Systems recommends to use the PC720 Board Support Package to program a .hex file into the flash.

Choose the SPI flash and select configure single FPGA Press the green arrow.

Choose 256M as the number of storage bits from the pull down menu.Press the green arrow.




Choose the name and location for your PROM filePress the OK button

Press OK




Browse to the bit file you want to program to the flashPress the Open button

Press the No button

Double-click on the generate file in the iMPACT Processes window.




Double- click the boundary scan in the iMPACT Flows window

Right-click and choose initialize chain




Press the No button

Press the Cancel button




Right-click on the SPI/BPI? Field and choose the Add SPI/BPI Flash option

Browse to the MCS file and press Open




Choose the S25FL256S PROM and Press OK

Select the FLASHRight-click on the FLASH Choose Program




Press OK

Wait approximately 15 minutes




Wait approximately 15 minutes

It should show Programmed successfully




Appendix D Final PC720 Assembly

1.57

10.0

0

PC720 with Primary FMC

1.57

10.0

0

8.00

MAX

PC720 with Primary FMC and Enhanced FPGA Cooling




20.3

2

7.00 1.75

33.5

2

10.0

01.

57

10.0

0

PC720 with Primary FMC and Secondary FMC using PC-FMC-ADAPTER
