A PROJECT REPORT ON

“PC BASED ROBO”

Submitted in partial fulfillment of requirement for the award of degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

By

RAMAKRISHNA RAJU.M (08D15A0409)

RAVI CHANDRA REDDY.B (07D11A04A3)

SAI VARMA.A (07D11A0463)

SREENIVASULU REDDY .S.T (07D11A0472)

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

TRR ENGINEERING COLLEGE

(AFFILIATED TO J.N.T.U HYDERABAD)

Inole (V) Patancheru (M) Medak (Dist)

HYDERABAD

2007 - 2011

1 | P a g e

TRR ENGINEERING COLLEGE(AFFILIATED TO J.N.T.U HYDERABAD)

Inole (V) Patancheru (M) Medak (Dist)HYDERABAD

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATEThis is to certify that the project work entitled “PC BASED

ROBO” was being submitted by RAMAKRISHNA RAJU.M

(08D15A0409), RAVI CHANDRA REDDY.B (07D11A04A3), SAI

VARMA.A (07D11A0463) SREENIVASULU.S.T (07D11A0472), in

partial fulfillment of the requirement for the award of degree of bachelor

of Technology in Electronics and Communication Engineering from

Jawaharlal Nehru Technology University – Hyderabad. The results

embodied in this project have not been submitted to any other University

or Institution of the award of any Degree or Diploma.

Prof. C ASHOK KUMAR

Internal Supervisor & Head of the Department.

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ACKNOWLEDGEMENT

Our heartfelt thanks to our principal Prof. Dr. ANIL KUMAR for having

provided us the necessary infrastructure required for the successful completion of our

project.

We acknowledge our gratitude to Prof. C. ASHOK KUMAR, Head of the

Department, Electronics and Communication Engineering, for the constant guidance

and encouragement.

We thank our internal guide Prof.MADHANNA, for his help and

invigorating suggestions extended with immense care throughout our work.

Our sincere thanks to all of the teaching and non – teaching staff for extending

their support and cooperation for the completion of our project.

RAMAKRISHNA RAJU.M (08D15A0409)

RAVI CHANDRA REDDY.B (07D11A04A3)

SAI VARMA.A (07D11A0463)

SREENIVASULU.S.T (07D11A0472)

3 | P a g e

A PROJECT REPORT ON

“PC BASED ROBO”

Submitted in partial fulfillment of requirement for the award of degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

By

RAMAKRISHNA RAJU.M (08D15A0409)

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

TRR ENGINEERING COLLEGE

(AFFILIATED TO J.N.T.U HYDERABAD)

Inole (V) Patancheru (M) Medak (Dist)

HYDERABAD

2007 - 2011

4 | P a g e

TRR ENGINEERING COLLEGE(AFFILIATED TO J.N.T.U HYDERABAD)

Inole (V) Patancheru (M) Medak (Dist)HYDERABAD

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATEThis is to certify that the project work entitled “PC BASED

ROBO” was being submitted by RAMAKRISHNA RAJU.M

(08D15A0409), in partial fulfillment of the requirement for the award of

degree of bachelor of Technology in Electronics and Communication

Engineering from Jawaharlal Nehru Technology University – Hyderabad.

The results embodied in this project have not been submitted to any other

University or Institution of the award of any Degree or Diploma.

Prof. C ASHOK KUMAR

Internal Supervisor & Head of the Department.

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CONTENTS

ABSTRACT

CHAPTER-1-------------------------------------------------------------------1-2

INTRODUCTION TO EMBEDDED SYSTEMS

1.1Examples of Embedded Systems

CHAPTER-II--------------------------------------------------------------------3-7

2.1 MICROCONTROLLER VERSUS MICROPROCESSOR

2.2 MICROCONTROLLERS FOR EMBEDDED SYSTEMS

2.3 Typical Microcontroller Architecture and Features

2.4 The UART: What it is and how it works

2.5 Synchronous Serial Transmission

2.6Asynchronous Serial Transmission

CHAPTER-3------------------------------------------------------------------8-22

MICROCONTROLLER PIN CONFIGURATION

3.1 The ATmega8 provides the following prominent features

3.2 Pin Descriptions

3.3RESET

3.4 I/O PORTS

3.5 Ports as general purpose I/O

3.6 8-bit Timer/Counter Register Description

3.7 8-bit Timer/Counter

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CHAPTER – 4----------------------------------------------------23-25

4.1 POWER SUPPLY DIAGRAM:

4.2 CIRCUIT FEATURES

4.3 BLOCK DIAGRAM

4.4 EXAMPLE CIRCUIT DIAGRAM

CHAPTER-5-----------------------------------------------------26-31

5.1 Circuit Description and operation

5.2 Interface

5.3 Data transmission

5.4 Schematic Diagram

5.5 Hardware Specification

5.6 Software tool

5.7 Advantages

5.8 Disadvantages

5.9 Applications

CHAPTER-6-------------------------------------------------------------32-34

Test procedure for EMXcore SBC V.1

CHAPTER-7------------------------------------------------------35-40

CODING

CHAPTER-8----------------------------------------------------------------

41-41

RESULT

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ACKNOWLEDGEMENT

Our heartfelt thanks to our principal Prof. Dr. ANIL KUMAR for having

provided us the necessary infrastructure required for the successful completion of our

project.

We acknowledge our gratitude to Prof. C. ASHOK KUMAR, Head of the

Department, Electronics and Communication Engineering, for the constant guidance

and encouragement.

We thank our internal guide Prof.MADHANNA, for his help and

invigorating suggestions extended with immense care throughout our work.

Our sincere thanks to all of the teaching and non – teaching staff for extending

their support and cooperation for the completion of our project.

RAMAKRISHNA RAJU.M (08D15A040

8 | P a g e

ABSTRACT:

A serial peripheral interface (SPI) is an interface that enables the serial (one bit at a time) exchange of data between two devices, one called a master and the other called a slave. An SPI operates in full duplex mode. This means that data can be transferred in both directions at the same time. The SPI is most often employed in systems for communication between the central processing unit (CPU) and peripheral devices. It is also possible to connect two microprocessors by means of SPI. The Block diagram has been depicted below

The term was originally coined by Motorola. National Semiconductor has an equivalent interface called Micro-wire. Serial interfaces have certain advantages over parallel interfaces. The most significant advantage is simpler wiring. In addition, serial interface cables can be longer than parallel interface cables, because there is much less interaction (crosstalk) among the conductors in the cable.

Many types of devices can be controlled by an SPI, including shift registers, memory chips, port expanders, display drivers, data converters, printers, data storage devices, sensors, and microprocessors. Data is transferred serially over a cable, input to a shift register, and transferred within each subsystem by means of parallel processing.

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CHAPTER-1

Introduction to Embedded Systems An embedded system is a special-purpose computer system designed to perform a dedicated function. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements, and often includes task-specific hardware and mechanical parts not usually found in a general-purpose computer. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale. Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. In terms of complexity embedded systems run from simple, with a single microcontroller chip, to very complex with multiple units, peripherals and networks mounted inside a large chassis or enclosure. Mobile phones or handheld computers share some elements with embedded systems, such as the operating systems and microprocessors which power them, but are not truly embedded systems themselves because they tend to be more general purpose, allowing different applications to be loaded and peripherals to be connected.

1.1Examples of Embedded Systems An embedded system typically has a specialized function with programs stored on ROM. Examples of embedded systems are chips that monitor automobile functions, including engine controls, antilock brakes, air bags, active suspension systems, environmental systems, security systems, and entertainment systems. Everything needed for those functions is custom designed into specific chips. No external operating system is required.

Another example is a chip for a microwave oven. It is specifically designed to run the front-panel controls and all the timing and electronics of the oven.

Network managers will need to manage more and more embedded systems devices, ranging from printers to scanners, to handheld computing devices, to cell phones. All of these have a need to connect with other devices, either directly or through a wireless or direct-connect network. Most will have custom operating systems or variations of existing operating systems (e.g., Microsoft Windows CE).

It's easy to picture nearly every electronic device as having an embedded system. For example, refrigerators, washing machines, and even coffee brewers will benefit in some way from embedded systems. A critical feature of an embedded system is its ability to communicate, so embedded systems support Ethernet, Bluetooth (wireless), infrared, or other technologies.

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A weather station on top of a building may employ an embedded system that gathers information from external sensors. This information can be pushed or pulled. In the push scenario, the data is automatically sent to devices that have requested it. In the pull scenario, users or network devices access the weather station to read the latest information.

If the weather station is connected to the Internet, it may have its own IP address and, ideally, will provide information to anyone that accesses the IP address. In this sense, the weather station is acting as a mini-Web server. In fact, many embedded systems are basically Web servers on a chip. The chips contain HTTP and HTML functions, and custom applications appropriate for the environment in which the chip will be used.

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CHAPTER-2

2.1 MICROCONTROLLER VERSUS MICROPROCESSOR

What is the difference between a Microprocessor and Microcontroller? By

microprocessor is meant the general purpose Microprocessors such as Intel's X86

family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family

(68000, 68010, 68020, 68030, 68040, etc). These microprocessors contain no RAM,

no ROM, and no I/O ports on the chip itself. For this reason, they are commonly

referred to as general-purpose Microprocessors.

A system designer using a general-purpose microprocessor such as the

Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make

them functional. Although the addition of external RAM, ROM, and I/O ports makes

these systems bulkier and much more expensive, they have the advantage of

versatility such that the designer can decide on the amount of RAM, ROM and I/O

ports needed to fit the task at hand. This is not the case with Microcontrollers.

A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount

of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the

processor, the RAM, ROM, I/O ports and the timer are all embedded together on one

chip. In many applications, for example a TV remote control, there is no need for the

computing power of a 486 or even an 8086 microprocessor. These applications most

often require some I/O operations to read signals and turn on and off certain bits.

2.2 MICROCONTROLLERS FOR EMBEDDED SYSTEMS

In the Literature discussing microprocessors, we often see the term Embedded

System. Microprocessors and Microcontrollers are widely used in embedded system

products. An embedded system product uses a microprocessor (or Microcontroller) to

do one task only. A printer is an example of embedded system since the processor

inside it performs one task only; namely getting the data and printing it. Contrast this

with a Pentium based PC. A PC can be used for any number of applications such as

word processor, print-server, bank teller terminal, Video game, network server, or

Internet terminal. Software for a variety of applications can be loaded and run. Of

course the reason a pc can perform myriad tasks is that it has RAM memory and an

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operating system that loads the application software into RAM memory and lets the

CPU run it.

In an Embedded system, there is only one application software that is typically

burned into ROM. An x86 PC contains or is connected to various embedded products

such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives,

mouse, and so on. Each one of these peripherals has a Microcontroller inside it that

performs only one task. For example, inside every mouse there is a Microcontroller to

perform the task of finding the mouse position and sending it to the PC. Table 1-1

lists some embedded products.

2.3 Typical Microcontroller Architecture and Features

The basic internal designs of microcontrollers are pretty similar. Figure1

shows the block diagram of a typical microcontroller. All components are connected

via an internal bus and are all integrated on one chip. The modules are connected to

the outside world via I/O pins.

Fig 1.1: Basic Layout of Microcontroller

The following list contains the modules typically found in a microcontroller.

You can find a more detailed description of these components in later sections.

Processor Core: The CPU of the controller. It contains the arithmetic logic unit, the

control unit, and the registers (stack pointer, program counter, accumulator register,

register file . . .).

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Memory: The memory is sometimes split into program memory and data memory. In

larger controllers, a DMA controller handles data transfers between peripheral

components and the memory.

Interrupt Controller: Interrupts are useful for interrupting the normal program flow

in case of (important) external or internal events. In conjunction with sleep modes,

they help to conserve power.

Timer/Counter: Most controllers have at least one and more likely 2-3

Timer/Counters, which can be used to timestamp events, measure intervals, or count

events. Many controllers also contain PWM (pulse width modulation) outputs, which

can be used to drive motors or for safe breaking (antilock brake system, ABS).

Furthermore the PWM output can, in conjunction with an external filter, be used to

realize a cheap digital/analog converter.

Digital I/O: Parallel digital I/O ports are one of the main features of microcontrollers.

The number of I/O pins varies from 3-4 to over 90, depending on the controller family

and the controller type.

Analog I/O: Apart from a few small controllers, most microcontrollers have

integrated analog/digital converters, which differ in the number of channels (2-16)

and their resolution (8-12 bits). The analog module also generally features an analog

comparator. In some cases, the microcontroller includes digital/analog converters.

2.4 The UART: What it is and how it works

The Universal Asynchronous Receiver/Transmitter (UART) controller is the

key component of the serial communications subsystem of a computer. The UART

takes bytes of data and transmits the individual bits in a sequential fashion. At the

destination, a second UART re-assembles the bits into complete bytes.

Serial transmission is commonly used with modems and for non-networked

communication between computers, terminals and other devices. There are two

primary forms of serial transmission: Synchronous and Asynchronous. Depending on

the modes that are supported by the hardware, the name of the communication sub-

system will usually include a A if it supports Asynchronous communications, and a S

if it supports Synchronous communications. Both forms are described below.

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2.5 Synchronous Serial Transmission

Synchronous serial transmission requires that the sender and receiver share a

clock with one another, or that the sender provide a strobe or other timing signal so

that the receiver knows when to “read” the next bit of the data. In most forms of serial

Synchronous communication, if there is no data available at a given instant to

transmit, a fill character must be sent instead so that data is always being transmitted.

Synchronous communication is usually more efficient because only data bits are

transmitted between sender and receiver, and synchronous communication can be

more costly if extra wiring and circuits are required to share a clock signal between

the sender and receiver.

A form of Synchronous transmission is used with printers and fixed disk

devices in that the data is sent on one set of wires while a clock or strobe is sent on a

different wire. Printers and fixed disk devices are not normally serial devices because

most fixed disk interface standards send an entire word of data for each clock or

strobe signal by using a separate wire for each bit of the word. In the PC industry,

these are known as Parallel devices. The standard serial communications hardware in

the PC does not support Synchronous operations. This mode is described here for

comparison purposes only

2.6Asynchronous Serial Transmission

Asynchronous transmission allows data to be transmitted without the sender

having to send a clock signal to the receiver. Instead, the sender and receiver must

agree on timing parameters in advance and special bits are added to each word which

are used to synchronize the sending and receiving units.

When a word is given to the UART for Asynchronous transmissions, a bit

called the "Start Bit" is added to the beginning of each word that is to be transmitted.

The Start Bit is used to alert the receiver that a word of data is about to be sent, and to

force the clock in the receiver into synchronization with the clock in the transmitter.

These two clocks must be accurate enough to not have the frequency drift by more

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than 10% during the transmission of the remaining bits in the word. (This requirement

was set in the days of mechanical teleprinters and is easily met by modern electronic

equipment.)

After the Start Bit, the individual bits of the word of data are sent, with the

Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted

for exactly the same amount of time as all of the other bits, and the receiver “looks” at

the wire at approximately halfway through the period assigned to each bit to

determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit,

the receiver will examine the signal to determine if it is a 1 or a 0 after one second has

passed, then it will wait two seconds and then examine the value of the next bit, and

so on.

The sender does not know when the receiver has “looked” at the value of the

bit. The sender only knows when the clock says to begin transmitting the next bit of

the word.When the entire data word has been sent, the transmitter may add a Parity

Bit that the transmitter generates. The Parity Bit may be used by the receiver to

perform simple error checking. Then at least one Stop Bit is sent by the transmitter.

When the receiver has received all of the bits in the data word, it may check

for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to

be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear

when it is supposed to, the UART considers the entire word to be garbled and will

report a Framing Error to the host processor when the data word is read. The usual

cause of a Framing Error is that the sender and receiver clocks were not running at the

same speed, or that the signal was interrupted.Regardless of whether the data was

received correctly or not, the UART automatically discards the Start, Parity and Stop

bits. If the sender and receiver are configured identically, these bits are not passed to

the host.If another word is ready for transmission, the Start Bit for the new word can

be sent as soon as the Stop Bit for the previous word has been sent.

Because asynchronous data is “self synchronizing”, if there is no data to

transmit, the transmission line can be idle.

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CHAPTER-3

MICROCONTROLLER PIN CONFIGURATION

ATmega8

The ATmega8 is a low-power CMOS 8-bit microcontroller, based

on the AVR enhanced RISC architecture. By executing powerful instructions in a

single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz

allowing the system designer to optimize power consumption versus processing

speed.

Fig. 3.1.1 Pin Out of ATmega8

AVR core combines a rich instruction set with 32 general-purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed

in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

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3.1 The ATmega8 provides the following prominent features

• High-performance, Low-power AVR® 8-bit Microcontroller

• Advanced RISC Architecture

130 Powerful Instructions – Most Single-clock Cycle Execution

32 x 8 General Purpose Working Registers

Fully Static Operation

Up to 16 MIPS Throughput at 16 MHz

On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

8K Bytes of In-System Self-programmable Flash program memory

512 Bytes EEPROM

1K Byte Internal SRAM

Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

Data retention: 20 years at 85°C/100 years at 25°C

Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Programming Lock for Software Security

• Peripheral Features

Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode

One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and

Capture

Mode

Real Time Counter with Separate Oscillator

Three PWM Channels

8-channel ADC in TQFP and QFN/MLF package

Eight Channels 10-bit Accuracy

6-channel ADC in PDIP package

Six Channels 10-bit Accuracy

Byte-oriented Two-wire Serial Interface

Programmable Serial USART

Master/Slave SPI Serial Interface

Programmable Watchdog Timer with Separate On-chip Oscillator

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On-chip Analog Comparator

• Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection

Internal Calibrated RC Oscillator

External and Internal Interrupt Sources

Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

23 Programmable I/O Lines

28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

• Operating Voltages

2.7 - 5.5V (ATmega8L)

4.5 - 5.5V (ATmega8)

• Speed Grades

0 - 8 MHz (ATmega8L)

0 - 16 MHz (ATmega8)

• Power Consumption at 4 Mhz, 3V, 25°C

Active: 3.6 mA

Idle Mode: 1.0 mA

Power-down Mode: 0.5 μA

The Idle mode stops the CPU while allowing the USART, Two-wire interface,

A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue

functioning. The Power-down mode saves the register contents but freezes the

Oscillator, disabling all other chip functions until the next External Interrupt or

Hardware Reset.

In Power-save mode, the Asynchronous Timer continues to run, allowing the

user to maintain a timer base while the rest of the device is sleeping. The ADC Noise

Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and

ADC, to minimize switching noise during ADC conversions.

By combining an 8-bit RISC CPU with In-System Self-Programmable Flash

on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides

a highly flexible and cost-effective solution to many embedded control applications.

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3.2 Pin Descriptions:

VCC- Digital supply voltage.

GND- Ground.

Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors

(selected for each bit). The Port B output buffers have symmetrical drive

characteristics with both high sink and source capability. As inputs, Port B pins that

are externally pulled low will source current if the pull-up resistors are activated. The

Port B pins are tri-stated when a reset condition becomes active, even if the clock is

not running. Depending on the clock selection fuse settings, PB6 can be used as input

to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the

inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip

clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2

if the AS2 bit in ASSR is set.

Port C (PC5..PC0)

Port C is an 7-bit bi-directional I/O port with internal pull-up resistors

(selected for each bit). The Port C output buffers have symmetrical drive

characteristics with both high sink and source capability. As inputs, Port C pins that

are externally pulled low will source current if the pull-up resistors are activated. The

Port C pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that

the electrical characteristics of PC6 differ from those of the other pins of Port C. If the

RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this

pin for longer than the minimum pulse length will generate a Reset, even if the clock

is not running

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors

(selected for each bit). The Port D output buffers have symmetrical drive

characteristics with both high sink and source capability. As inputs, Port D pins that

are externally pulled low will source current if the pull-up resistors are activated. The

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Port D pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

3.3RESET

Reset input. A low level on this pin for longer than the minimum pulse length

will generate a reset, even if the clock is not running. Shorter pulses are not

guaranteed to generate a reset.

AVCC

AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and

ADC (7..6). It should be externally connected to VCC, even if the ADC is not used.

If the ADC is used, it should be connected to VCC through a low-pass filter. Note that

Port C (5..4) use digital supply voltage, VCC.

AREF

AREF is the analog reference pin for the A/D Converter.

ADC7..6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the

A/D converter. These pins are powered from the analog supply and serve as 10-bit

ADC channels.

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Fig 3.3.1 BLOCK DIAGRAM OF AT mega 8

The ATmega8 AVR is supported with a full suite of program and system

development tools including: C compilers, macro assemblers, program

debugger/simulators, in-circuit emulators, and evaluation kits.

A flexible interrupt module has its control registers in the I/O space with an

additional global interrupt enable bit in the Status Register. All interrupts have a

separate interrupt vector in the interrupt vector table. The interrupts have priority in

accordance with their interrupt vector position. The lower the interrupt vector address,

the higher the priority. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 20h - 5Fh

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3.4 I/O PORTS

All AVR ports have true Read-Modify-Write functionality when used as general

digital I/O ports. This means that the direction of one port pin can be changed without

unintentionally changing the direction of any other pin with the SBI and CBI

instructions. The same applies when changing drive value (if configured as output) or

enabling/disabling of pull-up resistors (if configured as input). Each output buffer has

symmetrical drive characteristics with both high sink and source capability. The pin

driver is strong enough to drive LED displays directly. All port pins have individually

selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins

have protection diodes to both VCC and Ground.

All registers and bit references in this section are written in general form.

Three I/O memory address locations are allocated for each port, one each for the Data

Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx.

The Port Input Pins I/O location is read only, while the Data Register and the Data

Direction Register are read/write. In addition, the Pull-up Disable – PUD bit in

SFIOR disables the pull-up function for all pins in all ports when set.

Most port pins are multiplexed with alternate functions for the peripheral

features on the device. Enabling the alternate function of some of the port pins does

not affect the use of the other pins in the port as general digital I/O.

3.5 Ports as general purpose I/O:

The ports are bi-directional I/O ports with optional internal pull-ups. Each port pin

consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are

accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and

the PINxn bits at the PINxI/O address. The DDxn bit in the DDRx Register selects the

direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin.

If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written

logic one when the pin is configured as an input pin, the pull-up resistor is activated.

To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has

to be configured as an output pin. The port pins are tri-stated when a reset condition

becomes active, even if no clocks are running. If PORTxn is written logic one when

the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is

written logic zero when the pin is configured as an output pin, the port pin is driven

low (zero). Normally, the pull-up enabled state is fully acceptable, as a high-

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impedance environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to

disable all pull-ups in all ports.

Table 2.1.2.1 Selection Table

Fig 3.5.1 General I/O Block diagram

Independent of the setting of Data Direction bit DDxn, the port pin can be read

through the PINxn Register bit. The PINxn Register bit and the preceding latch

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constitute a synchronizer. This is needed to avoid meta stability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. The

maximum and minimum propagation delays are denoted tpd, max and tpd, min

respectively.

Fig 3.5.2 Timing Diagram while Reading an 1

Consider the clock period starting shortly after the first falling edge of the

system clock. The latch is closed when the clock is low, and goes transparent when

the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal.

The signal value is latched when the system clock goes low. It is clocked into the

PINxn Register at the succeeding positive clock edge. As indicated by the two arrows

tpd, max and tpd, min, a single signal transition on the pin will be delayed between ½ and

1½ system clock period depending upon the time of assertion.When reading back a

software assigned pin value, a nop instruction must be inserted. The out instruction

sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the

delay tpd through the synchronizer is one system clock period.

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Fig 3.5.3 Timing diagram when Reading an

3.6 8-bit Timer/Counter Register DescriptionTimer/Counter Control Register – TCCR2

fig 3.6.1 TCCR 1

Bit 7 – FOC2: Force Output Compare

The FOC2 bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero

when TCCR2 is written when operating in PWM mode. When writing a logical one to

the FOC2 bit, an immediate Compare Match is forced on the waveform generation

unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the

FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0

bits that determines the effect of the forced compare. A FOC2 strobe will not generate

any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2

bit is always read as zero.

• Bit 6,3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the

maximum (TOP) counter value, and what type of waveform generation to be used.

Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear

Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation

(PWM) modes

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table 3.6.2 TCCR modes

• Bit 5:4 – COM21:0: Compare Match Output Mode

These bits control the Output Compare Pin (OC2) behavior. If one or both of the

COM21:0 bits

are set, the OC2 output overrides the normal port functionality of the I/O pin it is

connected to.

However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin

must be set

in order to enable the output driver. When OC2 is connected to the pin, the function of

the COM21:0 bits depends on the WGM21:0 bit setting.

Timer/Counter Register – TCNT2

Fig 3.6.3 TCNT

The Timer/Counter Register gives direct access, both for read and write operations, to

the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)

the Compare

Match on the following timer clock. Modifying the counter (TCNT2) while the

counter is running, introduces a risk of missing a Compare Match between TCNT2

and the OCR2 Register.

Output Compare Register – OCR2

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Fig 3.6.4 OCR2

The Output Compare Register contains an 8-bit value that is continuously

compared with the counter value (TCNT2). A match can be used to generate an

Output Compare interrupt, or togenerate a waveform output on the OC2 pin.

3.7 8-bit Timer/Counter

Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module.

The main features are:

• Single Channel Counter

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Fig 3.8.1 . For

the actual placement of I/O pinsCPU accessible I/O Registers, including I/O bits and

I/O pins, are shown in bold. The device-specific I/O Register and bit locations are

listed in the “8-bit Timer/Counter Register Description”.

Fig 3.7.1 8-bit Timer/Counter

Registers

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The Timer/Counter (TCNT0) is an 8-bit register. Interrupt request (abbreviated to Int.

Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register

(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are

shared by other timer units. The Timer/Counter can be clocked internally or via the

prescaler, or by an external clock source on the T0 pin. The Clock Select logic block

controls which clock source and edge the Timer/Counter uses to increment its value.

The Timer/Counter is inactive when no clock source is selected. The output from the

clock select logic is referred to as the timer clock (clkT0).

Definitions

Many register and bit references in this document are written in general form. A

lower case “n”

replaces the Timer/Counter number, in this case 0. However, when using the register

or bit

defines in a program, the precise form must be used i.e. TCNT0 for accessing

Timer/Counter0

counter value and so on.

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The

clock source

is selected by the clock select logic which is controlled by the clock select (CS02:0)

bits located

in the Timer/Counter Control Register (TCCR0).

Counter Unit

.

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Fig 3.7.2 Counter Unit Block Diagram

Operation

The counting direction is always up (incrementing), and no counter clear is

performed. The counter simply overruns when it passes its maximum 8-bit value

(MAX = 0xFF) and then restarts from the bottom (0x00). In normal operation the

Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the

TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except

that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by

software. A new counter value can be written anytime.

Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore

shown as a

clock enable signal in the following figures. The figures include information on when

Interrupt

Flags are set. Figure contains timing data for basic Timer/Counter operation. The

figure

shows the count sequence close to the MAX value.

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Fig 3.7.3 timing diagrams 1

Fig 3.7.4 timing diagrams 2

CHAPTER – 4

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4.1 POWER SUPPLY DIAGRAM:

A variable regulated power supply, also called a variable bench power

supply, is one where you can continuously adjust the output voltage to your

requirements. Varying the output of the power supply is the recommended way

to test a project after having double checked parts placement against circuit

drawings and the parts placement guide.

This type of regulation is ideal for having a simple variable bench power

supply. Actually this is quite important because one of the first projects a

hobbyist should undertake is the construction of a variable regulated power

supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much

handier to have a variable supply on hand, especially for testing.

Most digital logic circuits and processors need a 5 volt power supply. To

use these parts we need to build a regulated 5 volt source. Usually you start

with an unregulated power To make a 5 volt power supply, we use a LM7805

voltage regulator IC (Integrated Circuit). The IC is shown below.

Fig 4.1.1 LM7805 voltage regulator

The LM7805 is simple to use. You simply connect the positive lead of

your unregulated DC power supply (anything from 9VDC to 24VDC) to the

Input pin, connect the negative lead to the

4.2 CIRCUIT FEATURES

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Brief description of operation: Gives out well regulated +5V output,

output current capability of 100 mA

Circuit protection: Built-in overheating protection shuts down output

when regulator IC gets too hot

Circuit complexity: Very simple and easy to build

Circuit performance: Very stable +5V output voltage, reliable operation

Availability of components: Easy to get, uses only very common basic

components

Design testing: Based on datasheet example circuit, I have used this

circuit successfully as part of many electronics projects

Applications: Part of electronics devices, small laboratory power supply

Power supply voltage: Unregulated DC 8-18V power supply

Power supply current: Needed output current + 5 mA

Component costs: Few dollars for the electronics components + the input

transformer cost

4.3 BLOCK DIAGRAM

Fig 4.3.1 BLOCK DIAGRAM of Power supply

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4.4 EXAMPLE CIRCUIT DIAGRAM

Fig 4.4.1 Circuit DDIAGRAMIAGRAM of Power supply

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Chapter-5

5.1 Circuit Description and operation

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SPI bus: single master and single slave

The Serial Peripheral Interface Bus or SPI ("s-pea-eye" or "spy") bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four-wire" serial bus, contrasting with three-, two-, and one-wire serial buses. Here we are transferring the data single bit at a time from master to slave or slave to masterby enabling these pins as high.

5.2 Interface

The SPI bus specifies four logic signals:

SCLK: Serial Clock (output from master);

MOSI; SIMO: Master Output, Slave Input (output from master);

MISO; SOMI: Master Input, Slave Output (output from slave);

SS: Slave Select (active low, output from master).

Alternative naming conventions are also widely used:

SCK; CLK: Serial Clock (output from master)

SDI; DI, SI: Serial Data In; Data In, Serial In

SDO; DO, SO: Serial Data Out; Data Out, Serial Out

nCS, CS, CSB, CSN, nSS, STE: Chip Select, Slave Transmit Enable (active

low, output from master)

The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be

connected to SDI on the slave, and vice-versa. Chip select polarity is rarely active

high, although some notations (such as SS or CS instead of nSS or nCS) suggest

otherwise.

.

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5.3 Data transmission

A typical hardware setup using two shift registers to form an inter-chipcircular

buffer

To begin a communication, the master first configures the clock, using a frequency

less than or equal to the maximum frequency the slave device supports. Such

frequencies are commonly in the range of 1–70 MHz.

The master then pulls the slave select low for the desired chip. If a waiting period is

required (such as for analog-to-digital conversion) then the master must wait for at

least that period of time before starting to issue clock cycles.

During each SPI clock cycle, a full duplex data transmission occurs:

the master sends a bit on the MOSI line; the slave reads it from that same line

the slave sends a bit on the MISO line; the master reads it from that same line

Not all transmissions require all four of these operations to be meaningful but they do

happen.

Transmissions normally involve two shift registers of some given word size, such as

eight bits, one in the master and one in the slave; they are connected in a ring. Data

are usually shifted out with the most significant bit first, while shifting a new least

significant bit into the same register. After that register has been shifted out, the

master and slave have exchanged register values. Then each device takes that value

and does something with it, such as writing it to memory. If there is more data to

exchange, the shift registers are loaded with new data and the process repeats.

Transmissions may involve any number of clock cycles. When there are no more data

to be transmitted, the master stops toggling its clock. Normally, it then deselects the

slave.

Transmissions often consist of 8-bit words, and a master can initiate multiple such

transmissions if it wishes/needs. However, other word sizes are also common, such as

16-bit words for touchscreen controllers or audio codecs, like the TSC2101

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from Texas Instruments; or 12-bit words for many digital-to-analog or analog-to-

digital converters.

Every slave on the bus that hasn't been activated using its slave select line must

disregard the input clock and MOSI signals, and must not drive MISO. The master

must select only one slave at a time.

5.4 Schematic Diagram:

5.5 Hardware Specification:

Regulated power supply 3.3v

AVR series Micro controller

5.6 Software tools:

WINAVR to compile the source file and generate the hex code.

AVR STUDIO to compile the source file and generate the hex code.

AVRISP2 to program the microcontroller.

5.7 Advantages

Full duplex communication

Higher throughput than I²C or SMBus

Complete protocol flexibility for the bits transferred

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Not limited to 8-bit words

Arbitrary choice of message size, content, and purpose

Extremely simple hardware interfacing

Typically lower power requirements than I²C or SMBus due to less circuitry

(including pullups)

No arbitration or associated failure modes

Slaves use the master's clock, and don't need precision oscillators

Slaves don't need a unique address -- unlike I²C or GPIB or SCSI

Transceivers are not needed

Uses only four pins on IC packages, and wires in board layouts or connectors,

much less than parallel interfaces

At most one "unique" bus signal per device (chip select); all others are shared

Signals are unidirectional allowing for easy Galvanic isolation

5.8 Disadvantages

Requires more pins on IC packages than I²C, even in the "3-Wire" variant

No in-band addressing; out-of-band chip select signals are required on shared

buses

No hardware flow control by the slave (but the master can delay the next clock

edge to slow the transfer rate)

No hardware slave acknowledgment (the master could be "talking" to nothing

and not know it)

Supports only one master device

No error-checking protocol is defined

Generally prone to noise spikes causing faulty communication

Without a formal standard, validating conformance is not possible

Only handles short distances compared to RS-232, RS-485, or CAN-bus

5.9 Applications:

SPI is used to talk to a variety of peripherals, such as

Used for Industrial applications as well as for home appliances also..

Sensors: temperature, pressure, ADC, touch screens, video game

controllers

Control devices: audio codecs , digital potentiometers, DAC

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Camera lenses: Canon EF lens mount

Communications: Ethernet, USB, USART, CAN, IEEE

802.15.4, IEEE 802.11, handheld video games

Memory: flash and EEPROM

Real-time clocks

LCD displays, sometimes even for managing image data

Any MMC or SD card (including SDIO varia

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Chapter-6Test procedure for EMXcore SBC V.1

Objective: to test two SBC01 V1 boards simultaneously for operation of all ports, and USART.

1. Equipment required

PC with serial port and RS232 cableMultimeter2 Nos wall socket adapters for 5V DCLED strips for testing boardsSerial port cable..male to male 9 pin D connectors

2. Visual Inspection of bare boards:

Check for unwanted shorts between tracks and between padsand cuts on tracks.

3. Assembly/ soldering components

Ensure components are selected as per BOM.Use sockets for all ICs ensuring proper orientationBend component leads (axial leads) leaving at least 2mm from each end.Place electrolytic capacitors and diodes as per polarity marking on PCB.Check for unwanted solder bridges .

4. Procedure for testing populated boards

We need two populated PCBs for the test. Call one as Master and the other as

slave.

Set up Programmer in the following way

Programmer set up

a. Click on the “eMx-programmer” icon present in the test folder.

b. Now a window pops up , click on “port” on the menu bar and select the

com port to which the programmers cable is being connected.

c. Now click on the “file” menu and click on “open”..

d. Now a window opens asking for a hex file to be selected. Select the slave

file present in the test folder named as “slave”.

e. Now connect the programmers 6Pin connecter to the slave board and insert

the connector in such a way that the boss faces the other side of the board..

Now check eMxSBC01 V.1 boards in the following way.

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Slave board

f. Connect 5V DC power supply (adapter) at P1 (Molex connector) and

check voltage at test point 5V with respect to Gd test point. Note voltage

in table 1. It should be between 4.6V and 5.4V

g. Switch of power supply.

h. If the power supply is OK, insert test micro controller, U1(MAX232) ,

connect LED strips to IO ports..P2,P3,P5 and P6

i. Switch ON power to board.

j. Check the temperatures of U1 and U2. If they get hot, switch off power

supply. Otherwise, proceed as follows.

k. Now click the “write” option present on the programming software..

l. Now after the program has been dumped. Switch “OFF” the board.

m. Connect the test jigs to the four ports and also connect one end of the test

USART cable to the slaves com port.

Master board

n. For master programming start the procedure from point 4 and instead of

selecting “slave” file select “master” file from the test folder.

o. Now after the program has been dumped. Switch “OFF” the board.

p. Connect the test jigs to the four ports and also connect the other end of the

test USART cable to the masters com port.

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OBSERVATIONS

a. Now switch “ON” the two boards. Push the reset button of the slave and

then push the reset button of the master.

b. Now in the master the LED’s should glow in a sequential manner. From

port B to port D.

c. If all the LED’s in the master had glowed. Now check the slave to see if

the LED’s are glowing in a similar manner.

d. After all the LED’s in the slave had been glowed then check the master

again to see the LED’s glowing again.

e. If point ‘b’ is not seen then master board has some trouble.

f. If point ‘c’ does not occur then the slave board has some trouble

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Chapter-7

CODING

#define F_CPU 8000000UL //freq 8 MHz#include <avr/io.h>#include <avr/pgmspace.h>#include <avr/interrupt.h>#include <util/delay.h>

#include "UART_routines.h"#include "SPI_routines.h"

void port_init(void){

PORTC = 0x00;DDRC = 0x00;PORTD = 0x00;DDRD = 0xFE;}

//call this routine to initialize all peripheralsvoid init_devices(void){ cli(); port_init(); uart0_init(); spi_init(); SPI_master_init(); SPI_slave_init( );sei();}//*************************** MAIN *******************************//

int main(void){ unsigned char data;

init_devices();

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transmitString("Please Enter 1 For MAster 2 For Slave Mode \n\r");

data=receiveByte();transmitByte(data);

// SPI_transmit(rx_data);// transmitByte(SPI_receive());

switch(data){case'1':transmitString("SPI MASTER:\n\r");

while(1){//transmitString("Please Enter Data \n\r");data=receiveByte(); transmitByte(data);SPI_transmit(data);//transmitByte(ack);

}break;case'2':transmitString("SPI SLAVE MODE:\n\r");while(1){data=receiveByte();transmitByte(data); SPI_transmit(SPI_receive());}break;}}//**************************************************************//******** FUNCTIONS FOR SERIAL COMMUNICATION USING UART *******//**************************************************************//Controller: ATmega32 (8 Mhz internal)//Compiler: AVR-GCC

//Date: 18 April 2009//**************************************************************

//**************************************************// ***** SOURCE FILE : UART_routines.c ******//**************************************************

#include "UART_routines.h"#include <avr/io.h>#include <avr/pgmspace.h>

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//UART0 initialize// desired baud rate: 9600// actual: baud rate:9600 (0.2%)// char size: 8 bit// parity: Disabledvoid uart0_init(void){ UCSRB = 0x00; //disable while setting baud rate UCSRA = 0x00; UCSRC = (1 << URSEL) | 0x06; UBRRL = 0x33; //set baud rate lo UBRRH = 0x00; //set baud rate hi UCSRB = 0x18;}//**************************************************//Function to receive a single byte//*************************************************unsigned char receiveByte( void ){

unsigned char data, status;

while(!(UCSRA & (1<<RXC))); // Wait for incomming data

status = UCSRA;data = UDR;

return(data);}

//***************************************************//Function to transmit a single byte//***************************************************void transmitByte( unsigned char data ){

while ( !(UCSRA & (1<<UDRE)) ); /* Wait for empty transmit

buffer */UDR = data; /* Start transmition */

}

//***************************************************//Function to transmit hex format data//first argument indicates type: CHAR, INT or LONG//Second argument is the data to be displayed//***************************************************/*void transmitHex( unsigned char dataType, unsigned long data ){unsigned char count, i, temp;

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unsigned char dataString[] = "0x ";

if (dataType == CHAR) count = 2;if (dataType == INT) count = 4;if (dataType == LONG) count = 8;

for(i=count; i>0; i--){ temp = data % 16; if((temp>=0) && (temp<10)) dataString [i+1] = temp + 0x30; else dataString [i+1] = (temp - 10) + 0x41;

data = data/16;}

transmitString (dataString);}*///***************************************************//Function to transmit a string in Flash//***************************************************void transmitString_F(char* string){ while (pgm_read_byte(&(*string))) transmitByte(pgm_read_byte(&(*string++)));}

//***************************************************//Function to transmit a string in RAM//***************************************************void transmitString( char* string){ while (*string) transmitByte(*string++);}

//**************************************************************//******** FUNCTIONS FOR SERIAL COMMUNICATION USING UART *******//**************************************************************//Controller: ATmega32 (8 Mhz internal)//Compiler: AVR-G//**************************************************************

//**************************************************// ***** HEADER FILE : UART_routines.h ******//**************************************************

#ifndef _UART_ROUTINES_H_

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#define _UART_ROUTINES_H_

#define CHAR 0#define INT 1#define LONG 2void uart0_init(void);#define TX_NEWLINE {transmitByte(0x0d); transmitByte(0x0a);}

unsigned char receiveByte(void);void transmitByte(unsigned char);void transmitString_F(char*);void transmitString( char*);void transmitHex( unsigned char dataType, unsigned long data );

#endif//**************************************************************// ****** FUNCTIONS FOR SPI COMMUNICATION *******//**************************************************************//**************************************************************

//Controller: ATmega32 (8 Mhz internal)//Compiler : AVR-GCC//Version : 2.2//Author : CC kiran reddy , Hyd (India)// www.emxcore technologies .com//Date : 2 Dec 2009//**************************************************************//**************************************************// ***** HEADER FILE : SPI_routines.h ******//**************************************************#ifndef _SPI_ROUTINES_H_#define _SPI_ROUTINES_H_

#define SPI_SD SPCR = 0x52#define SPI_HIGH_SPEED SPCR = 0x50; SPSR |= (1<<SPI2X)void SPI_master_init(void );

void SPI_slave_init(void );

void spi_init(void);unsigned char SPI_transmit(unsigned char);unsigned char SPI_receive(void);

#endif//**************************************************************// ****** FUNCTIONS FOR SPI COMMUNICATION *******//**************************************************************

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//**************************************************************

//**************************************************// ***** SOURCE FILE : SPI_routines.c ******//**************************************************#include <avr/io.h>#include "SPI_routines.h"

//SPI initialize//clock rate: 125Khzvoid spi_init(void){SPCR = 0x52; //setup SPI: Master mode, MSB first, SCK phase low, SCK idle lowSPSR = 0x00;}void SPI_master_init(void ){PORTB=0x00;DDRB=0x2C;}void SPI_slave_init(void ){PORTB=0x00;DDRB=0x10;

}unsigned char SPI_transmit(unsigned char data){// Start transmissionSPDR = data;

// Wait for transmission completewhile(!(SPSR & (1<<SPIF)));data = SPDR;

return(data);}

unsigned char SPI_receive(void){unsigned char data;// Wait for reception complete

SPDR = 0xff;while(!(SPSR & (1<<SPIF)));data = SPDR;

// Return data register

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return data;}

CHAPTER-8

RESULT:We finally achieved the aim of the project, which is SPI communication

between two microcontrollers

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