PowerPoint PresentationPatricia Gonzalez
Divya Akella
Sub-threshold FPGAs
A sub-VT ring oscillator at 80mV [2].
A 65nm chip : 256kb memory in sub-threshold region to below 400mV [3]
New wireless applications : Wearable body sensor node (19uW) running on harvested energy – small devices, long lifetimes!
Ultimate aim ? Reduce Power consumption!
Variation In sub-threshold
Issue : Meet Throughput
100 operations every 5 seconds -> Frequency requirement
Extract ECG : Some chips will met the requirement some chips wont
3
a critical obstacle : sensitivity of sub-threshold circuits to variations in process, voltage, and temperature (PVT)
Affects delay : limits product yield !
A system that adjusts the chip operation to account for PVT ?
Motivation : Razor
System should be able to run at multiple frequencies and voltages.
Design to ensure correct operation at all PVT variations.
Variations ? Environmental, local, global, voltage droops, even data dependent!
Razor approach : DVS based on dynamic detection of errors
Motivation : PDVS
Different energies for different modes of operation/workload!
The Problem
First “high” input is caught by the flop : seen at output Q
Second “high” input is missed ?
Test circuit
To experiment with this problem : chose a 3 bit adder
Output is shown to be flopped
Solution
Worst case (FF) corner power at 0.4 V = 1.4 nW
Further optimization is definitely possible!
Use of razor circuit only for critical paths
Design
Extra margin for worst case scenario!
What if variability is rare , what if it never occurs ?
In lower processes and sub – threshold , variability might be so much – voltage margins go up!
Optimization during circuit design can now be done for a typical case
We attempt to show use of razor in sub-threshold voltages.
Savings example (T = 20C)
0.4 31.81%
0.425 21.99%
0.45 14.21%
Variable voltage and frequency to adjust to variation
It will improve the efficiency, thereby increasing yield and lowering costs.
Achievable performance for a given energy budget
Improve yield at a given frequency by allowing slower chips to speed up by going to higher VDD
Yield against process variation !!
40 MHz
200 kHz
100 kHz
T=27ºC
0.4 V 0.43 V 0.45 V 0.48 V 0.3500000000000002 0.25 0.4 0.1
T = 100ºC
0.7 V 0.8 V 0.9 V 1 V 0.214285714285714 1.1904761904761911E-2 0.32142857142857251 0.45238095238095244 0.7 V 0.8 V 0.9 V 1 V 0 0 0 0
T = 27ºC
0.7 V 0.8 V 0.9 V 1 V 0.3333333333333332 9.6774193548387205E-2 0.1827956989247311 0.38709677419354838
T =20 ºC
0.7 V 0.8 V 0.9 V 1 V 0.36274509803921601 0.11764705882352902 0.1764705882352941 0.34313725490196079
T=100ºC
0.5 V 0.55 V 0.6 V 0.65 V 0.67567567567567732 0.43243243243243201 0 0
T=27ºC
0.5 V 0.55 V 0.6 V 0.65 V 0.48648648648648724 0.108108108108108 0.2972972972972972 0.108108108108108
T=20ºC
0.5 V 0.55 V 0.6 V 0.65 V 0.62162162162162271 0.108108108108108 0.2972972972972972 0.21621621621621612
T=100ºC
0.4 V 0.43 V 0.45 V 0.48 V 0.5750000000000004 0.3500000000000002 0.05 2.5000000000000012E-2
T=20ºC
0.4 V 0.43 V 0.45 V 0.48 V 0.30000000000000021 0.30000000000000021 0.25 0.15000000000000011
[1] Wang, A.; Chandrakasan, A.; , "A 180mV FFT processor using subthreshold circuit techniques," Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International , vol., no., pp. 292- 529 Vol.1, 15-19 Feb. 2004
2] B. H. Calhoun and A. Chandrakasan, “Characterizing andModeling Minimum Energy Operation for Subthreshold Circuits,” in ISLPED, 2004, pp. 90–95.
[3] B. Zhai, et al., “Theoretical and Practical Limits of Dynamic
Voltage Scaling,” in DAC, 2004, pp. 868–873.
[4] Dan Ernst, Tao Phan. Razor : A low power pipeline based on Circuit Level timming speculation.
[5] Mathias Eireiner,. In situ Delay Characterization and Local Supply voltage adjustment for compensation of local parameter variations.
References
Did not integrate into the system
Originally, used as a timer in the sub – Hz range
Gate leakage based system – variation with temperature is reduced
Found that with varying capacitance charging time, leakage transistors and Schmitt trigger design – higher frequency ranges can be obtained.
Voltage Time period Frequency
0.4 3.71E-07 2.70E+06
0.5 5.65E-08 1.77E+07
0.6 1.40E-08 7.16E+07
0.7 5.16E-09 1.94E+08
0.8 2.54E-09 3.94E+08
0.9 1.54E-09 6.48E+08