Part one Lecture 1 2020- 2021 computer organization

Part one Lecture 12020- 2021

computer organization

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Inside computer

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Example 1.1

1 kilobyte=210

1 megabyte=220

1 gigabyte= 230

1 terabyte= 240

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Example 1.2

How many byte in 16 megabyte

Sol

16m=16 * 220=24 * 220=224

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Littlie endian and big endian

Store data inside computer is either

little endian or big endian

In Littlie endian the low bytes goes to the low memory location and high bytes goes to high

memory location

In big endian low byte goes to high memory location and high byte goes to low memory

location

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Example 1.3

Convert the following from littlie endian to big endian

(9F 09 20 3A)16

Solution

Big endian= (3A 20 09 9F)16

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Basic component of computer system

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Basic component of microprocessor

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CISC vs RISC

CISC (complex instruction set computer) refers to CPU with lot of instruction which made

design very complex. time consuming and expensive.

But the programmer notes that not all instruction was used

so thatafter 1980 new CPU design RISC (reduced

instruction set computer) was developed. In this way we use many transistors to enhancement the

CPU performance

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Pipeline in microprocessor

8085 built by use one unit only

While 8086 consist two units

so that 8086 can implemented pipeline processing and 8085 cannot implement pipeline

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MOV instruction

Simply stated, the MOV instruction copies data from one location to another.

it has the following format

MOV destination, source ;copy source operand to destination

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MOV instruction

To study addressing mode we use MOV instruction

MOV register to register

MOV AL , .AH

MOV BH , DL

MOV AX , BX

MOV DS , AX

MOV AL . 55H

MOV AX ,4F36 H

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Some important notes

1: values cannot be load directly to segment register

2: if value 8 bits like 3A h move into 16 bits register the rest bits of register is zero

3: move value more to register case error

4: move data between register must same size

5: When we want to read /write data we must but [ ] in the instruction

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نكمل المنهاج بمحاضرات اخرى

مع السلامه

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computer memory structure

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REAL MODE MEMORY ADDRESSING

The 80286 and above operate in either the real or protected mode.

Only the 8086 and 8088 operate exclusively in the real mode..

Real mode operation

allows the microprocessor to address only the first 1M byte of memory space. Note that the first 1M byte of memory is called the real memory, conventional memory, or DOS memory system.

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segment and offset

A combination of a segment address and an offset address accesses a memory location in the real mode.

The segment address, located within one of the segment registers, defines the beginning address of any 64K-byte

memory segment.

The offset address selects any location within the 64K byte memory segment.

The 8086–80286 microprocessors have four memory segments

the 80386–Core2 microprocessors have six memory segments.

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Memory Addressing schemam

There are 3 types of address schema:- Physical Address:

- is the 20 bit address that is actually put on the address pins of the 8086 M.P. and decoded by the memory interfacing circuits. In 8086

M.P. this address can have a range of 00000 H to FFFFF H.Offset Address :

is a location within a 64KB Segment range. Or it is telling how far the location is from the beginning of the segment.

Logical Address: consists of a segment value and an offset address.To calculate physical addressing in real mode use

Physical address (20bits)= offset(16bits) + (16* segment register(16bits))

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Example 1.4

if CS=2500h, and IP=95F3h find:(a) The logical address. (b) The offset. (C) The physical address.Solution:(a) logical address of this code segment is:CS:IP2500h:95F3h(b) the offset of this code segment is IP or it is equal to 95F3h.(C) physical address = offset +(16* segment register)(16* segment register) means shift the value of segment register four bits to the left, that means add 4 zero's for binary number or "0" for hexadecimal number.Physical address = 95F3+25000h = 2E5F3h

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Example 1.5: Assume that DS is 5000h and the offset is 1950h, calculate (a) Logical address. (b) Physical address.

(c) Lower address of the segment.(d) Upper address of the segment

SolutionA: DS: offset this is the logical address5000h:1950hB: So that physical address will be50000+l950=51950hC: Lower address of the segment is DS and the offset is zero so the physical address will be:Lower address= 50000h+0000 = 50000hD: Upper address or the segment is DS with maximum offset 64KB or (FFFF) therefore.The upper address = 50000h +FFFFh = 5FFFFh

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Example 1.6: Assume that the physical address of the instruction is A0123h , and the code segment (CS) contains

(A000h) , what is the offset of this segment?

CS:IP

CS *16 +IP =physical address

A0000h + IP =A0123h

So IP =A0123h – A0000h= 00123h = 123h

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What is a stack and why is it needed

The stack is a section of read/write memory (RAM) used by the CPU to store information temporarily.

The CPU needs this storage area since there are only limited numbers of register.

The main disadvantage of stack is its access time, since the stack is in RAM,

it takes much longer time to access.

but it is to useful for temporary store in subroutine and interrupt

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How stack access

Two register used to access stack

(stack pointer SP , base pointer BP )

and one segment register(stack segment ,SS)

And there are two instruction used with stack one to write to memory stack PUSH

instruction for read from stack memory POP

all stack operation in 16 bits

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Flag register

Flag register has six conditional flags and three control

The six are CF,PF,AF,ZF, and OF,

the three remaining flags are call control flag use to control the operation of instruction before

they are executed

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مع السلامه

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addressing mode

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8086 addressing modes:

1. Immediate addressing mode.

2. Register addressing mode.

3. Direct addressing mode.

4. Register indirect addressing mode.

5. Based relative addressing mode.

6. Indexed relative addressing mode.

7. Based indexed addressing mode.

8: Scaled index addressing

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immediate addressing mode:

In this mode the operand is a constant data and when the instruction is assembled the operand comes immediately after the code.

MOV AX,2550h , move 2550h into AXMOV CX,625h , load the decimal value 625 in CXMOV BL,40h , load 40h into BL

Note:Immediate addressing mode can be used to load data into ay registers except the segment registers and flag.

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Register addressing mode:

With this mode the operand to be accessed is specified as residing in an internal register, or in this mode, the 8086 fetches an operand from (or load it into) a register.MOV AX,BXThis means copy the 16 bit contents to register BX (which is the source operand) to register AX (which is the destination operand).MOV BX,DXMOV ES,AXADD AL,BHNote: It should be noted that the source and destination registers must match in size i.e: MOV CL, AX , will give an error.

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Effective address:

The offset that the execution unit calculates for a memory operand is called "effective address" or EA.

EA is the distance in bytes from the beginning of the segment to the operands location.

So the logical address (LA) is: LA=DS:EA

EA can be made up from as many as three elements:

The base, index and displacement.

PA= segment base: base + index + Displacement.

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Direct addressing mode:

This mode is similar to immediate addressing mode but here the instruction OP code is followed by an effective address (EA) instead of data, so that the EA is used directly as the offset to calculate PA.

PA=(CS OR SS OR DS OR ES) : [DIRECT ADDRESS]

SEGMENT PART EFFECTIVE PART

Mov cx,[1234h]

Note: The default segment register is DS.

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Direct addressing mode:DS=200

MOV CX,[1234]h

PA=DS*(10H)+EA= 200H *10H +1234H

PA=2000H+1234H=3234H

CL=[3234H]=ED H CH=[3235H]=BEH

CX=BEED

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Register indirect addressing mode:

This mode is similar to the direct addressing mode, but here the EA resides in either a base register BX or index register SI or DI.

PA=(CS or SS or DS or ES) : (BX or SI or DI)

SEGMENT PART EFFECTIVE PART

MOV AX, [SI]

Which means move the contents of the memory location that is offset is loaded in register SI into AX

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Register indirect addressing mode:DS=200 BX,SI,DI

Mov AX,[SI]

PA=DS*(10H)+EA= 200H *10H +1234H

PA=2000H+1234H=3234H

AL=[3234H]=ED H AH=[3235H]=BEH

AX=BEED

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Based relative addressing mode:

In this mode the EA of the operand is obtained by adding a direct or indirect displacement to the content either BX or BP.

Note:

The default segment register is DS, except if BP is used instead of BX, then the segment register will be (SS).

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Based relative addressing mode:BASE REGISTER BX OR BP

Assume BX=2000H BP=1000HDS=3000H SS=4000HPA=DS*(10H)+BX+DISP -> DSPA=SS*(10H)+BP+DISP -> SSEX 1 MOV AL,BX+1234HPA= DS*(10H)+2000H+1234H=33234HDS *10H = 30000BX 2000DISP 1234AL=[33234H]EX2= MOV AL,BP+1234HPA=SS*(10H)+1000H+1234H=42234HSS*10 40000BP 1000DISP 1234AL=[42234]

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Example 1.13

MOV AX,[BX]+1234h assume DS=200h memory location 4234h=BEh and memory location 4235h=EDh also BX=1000h

Solution

PA=2000 +1000h+1234=4234h

From memory location 4234=AL

Memory location 4235=AH

So that AX=BEED

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indexed relative addressing mode:

This mode works in a manner similar to that of the based addressing mode,

but here uses the value of displacement as a pointer to the starting point of an array of data in memory and the content of specific elements

in the array that is to be accessed.

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indexed relative addressing mode:Index register DI OR SI

MOV AL[SI]+1234H

PA= DS*(10H)+1234H =2000H+2000H+1234H

AL=[52234]

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Based indexed relative addressing mode:

Combining the based and the indexed addressing modes results in a new, more powerful mode known as "based-indexed addressing mode" this mode can be used to access complex data structures such as 2-dimensional arrays.

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Based indexed relative addressing modeAssume SI=2000H BX=1000H BP=3000H

SS=300H DS=200H

EX1=MOV AH,[BX][SI]+1234h

PA=DS*(10H)+BX+SI+DISP

DS*(10H) 2000H

BX 1000H

SI 2000H

DISP 1234H

AH=[6234H]

EX1=MOV AH,[BP][SI]+1234h

PA=SS*(10H)+BP+SI+DISP

SS*(10H) 3000H

BP 3000H

SI 2000H

DISP 1234H

AH=[9234H]

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Scaled Index Addressing Mode

Scaled-index addressing is available only in the 80386 through the Pentium 4 microprocessor.

The second register of a pair of registers is modified by the scale factor of(2x,4x,8x) to

generate the operand memory address

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مع السلامه

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Part one Lecture 1-42020- 2021

example-addressing mode

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Review questionpart one

computer architecture and addressing mode

2020-2021

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Q1: Choose the correct answer in each of the following

If the CS =FF59, the range of physical address is:

FF590….0F58F

FF590…..FF5FF

FF950…..FF9FF

0F590….0F59F

F F 5 9 0

+ F F F F

1 0 F 5 8 F

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CS=FF59

LOWER ADDRESS = CS*10H+0000H

FF590

UPPER ADDRESS=CS*10H+FFFFh=0F58F

(24)d=(18)H (21)d=(15)h (31)d=(1F)h

F F 5 9 0

F F F F

1 0 F 5 8 F

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Q2:Choose the correct answer in each of the following

The 80286 is a ------ microprocessor whereas the 80386 is a --- microprocessor.

12bits-20bits

16bits-32bits

16bits-48bits

8bits-16bits

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Q3: Choose the correct answer in each of the following

The two units in the 8086up are

CU& PU

EU&CU

BIU&EU

BIU&PU

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Register of 8086 is either –—or ــــــــــــ in length.

8 OR 16

6 OR 30

12 OR 48

20 OR 42

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The external data bus of 8088Mp is

8 bit

16 bit

32 bit

48 bit

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Q6: If DS = 3499H and the offset = 3FB9H, find:The physical address

The logical address of the data being fetchedThe lower and upper range addresses of the data segment

Solution:Physical address = segment value (shifted left) + offset, therefore;Physical address = 34990 + 3FB9 = 38949The logical address = 3499 : 3FB9Lower range = segment value (shifted left) + 0000, therefore;The lower range = 34990 + 0000 = 34990Upper range = segment value (shifted left) + FFFF, therefore;The upper range = 34990 + FFFF = 4498F

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Q7:Assume that SP = FF2EH, AX = 3291H, BX = F43CH, and CX = 09. Find the content of the stack and stack pointer after the

execution of each of the following instructions.PUSH AXPUSH BXPUSH CX

Solution:

Important Note:

Register CX has a value of 09 but the real size of CX is 16-bit so that we must add 00 in the higher byte of CX, so CX will become 0009 before pushing its value into the stack.

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Q8: Suppose that DS = 1200H, SS = 2000H,

EAX = 00001000H, EBX = 00002000H, ECX = 00003000H, BP = 0100H, and SI = 0250H. Give the type of addressing mode and determine the physical address for each of the following instructions, assuming real mode operation:

A: MOV DL, [100H]

B: MOV [SI+100H], EDX

C: MOV CL, [EAX+2*EBX]

D: MOV [BP+SI], AL

E: MOV EAX, [EBX+ECX+8]

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solutionA: Direct addressing (MOV DL, [100H])Physical address = 12000 + 100 = 12100H

B: Register relative addressing (MOV [SI+100H], EDX)Physical address = 12000 + (0250 + 100) = 12350H

C: Scaled index addressing (MOV CL, [EAX+2*EBX])Physical add= 12000 + (00001000 + 00002000 * 2) = 17000H

D: Base plus index addressing (MOV [BP+SI], AL)Physical address = 20000 + (0100+0250) = 20350H

E: Base relative plus index addressing (MOV EAX, [EBX+ECX+8])Physical address = 12000 + (00002000 + 00003000 + 8) = 17008H

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Q9: Explain the functions of EU and BIU in the 8086 CPU.

EU: is the execution unit responsible for executing instruction.

BIU: is the bus interface unit responsible for fetching the instructions from the memory unit.

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Q 10:what is the major difference between 8088 and 8086 CPU?

• The major difference is that the external data for the 8086 is 16-bit while the 8088 has 8-bit external data bus.

• Queue 6 bye in 8086 and queue 4 byte in 8088

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Q11:make list of addressing modes available on the 80386.

Register

Immediate

Direct

Register indirect

Based relative

Indexed relative

Base index relative

Scaled-index.

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Q12:name the five memory operand addressing modes and give an example for each case.

• Register indirect ex: MOV AX,[SI]

• Based relative ex: MOV AL,[BP]+5

• Index relative ex: MOV AL,[SI]+5

• Base index relative ex: MOV AH,[BX][SI]+1234H

• Scaled index ex: MOV AL,[BX][SI*8]+55H

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Q13:Give the addressing mode for each of the following.

• MOV AX,DS register• MOV BX,5678H immediate• MOV CX,[3000] direct• MOV AL,CH resister• MOV [DI],BX register indirect• MOV AL,[BX] register indirect• MOV DX,[BP+DI+4] base index relative• MOV CX, DS register• MOV [BP+6], AL base relative• MOV AH, [BX+SI+50] base index relative• MOV BL,[SI]+10 index relative• MOV [BP][SI]+12,AX base index relative

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Part twolecture 5

2020- 2021Descriptor-format

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Segment and offset addressing scheme allows relocation

Relocatable a program meant you can be placed it’s into any area of memory and executed without change.

Segment and offset addressing scheme allows both program and data to Relocated without changing anything in program or data.

This is the idea used in general-purpose computer system where not all machine contains the same memory area.

The personal computer memory structure is different from machine to machine requiring re locatable program and data

Because memory is addressing within a segment and offset address, the memory segment can be moved to any place in memory system without changing any of the offset addresses this is accomplished by moving the entire program as block to new area and then changing

only the contents of segment register

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Q: what is Relocatable?

A Relocatable a program meant you can be placed it’s into any area of memory and executed without

change by use segment and offset schema.

The memory segment can be moved to any place in memory system without changing any of the offset addresses this is accomplished by moving the entire

program as block to new area and then changing only the contents of segment register

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Protected Mode Memory Addressing

Protected mode allows access to data and programs located within and above the first 1MB of memory. Microsoft Windows operates in protected mode.

The segment registers are used differently in protected mode.– They no longer store the segment address.– Instead, they contain a selector that selects a descriptor from a descriptor

table.

A descriptor table can contain up to 8192 descriptors.Each descriptor has 8 byte.There are two types of descriptor tables:

– Global descriptors: contain segment definitions that apply to all programs.– Local descriptors: unique to an application.

A descriptor contains information about:– Memory segment’s location– Length of the segment

Access rights

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Selectors and Descriptors

The selector, located in the segment register, selects one of 8192 descriptors from one of two tables of descriptors.

The descriptor describes the location, length, and access rights of the segment of memory indirectly; the segment register still selects a memory

segment, but not directly as in the real mode. in protected mode there are two descriptor tables used with the segment

register: one contains global descriptors and the other contains local descriptors.

Each descriptor has 8 bytes (base; limit and access right).The global descriptors contain segment definition that applies to all

programs, while the local descriptors are usually unique to an application. Each descriptor table contains 8192 descriptors so a total of 16384

descriptors are available to an application at any time. The descriptor describes a memory segment (of up to 64 KB) this allows up to

16384 memory segments to be described for each application. Figure 3.1 shows how the segment register functions in the protected mode

system.

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Example CS=0000 0000 0010 0111

Index 13 bits from segment

0000 0000 0010 0

Select descriptor 4

2^13= 2^3 2^10 =8k =8192

TI 0-> g descriptor TI=1 local

Select local descriptor

11=Lower RPL

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Descriptor format for 80286 and 80386 and above

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Descriptor 0f 80286 and 80386

For 80286 the base address 24bits and limit is 16bits .

For 80386 and above the base is 32 bits and limit is 20 bits

The 80286 access memory segment between 1 to 64k bytes while the 80386 and above access

memory segment between 1 to M (or 4k and 4G byte in length)

The segment limit contains the last offset address found in segment.

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Example

if a segment begin at memory location(F0 00 00 H) and end at location

(F0 00 FF H).base address

(start address of segment memory) = F0 00 00 H limit =(end address –start address)=FF H.

For 80286 the base address 24bits = F0 00 00 H and limit is 16bits =00 FF H.

For 80386 and above base is 32 bits =00 F0 00 00 H and limit is 20 bits= 00 0F F H.

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Control bits in 80386

G bits G=0 limit (11 m)G=1 limit (4k 4G)

segment =1 toلكي يكون حجم ال bits 20يكون limitال فان 0كانت قيمته اذا •1M مان قيمة ال 1اما اذا كانت قيمتهsegment =4k to 4G وتتم ذلك بضوب ال

limit by 212

•AV bitsIn 80386 and above this bits used by some operating system to indicate that segment is available(AV=1) or not available (AV=0).

D bitIndicates how 80386 and above instruction access register or memory .if D=0 than it is 16 bits means use offset as 16 bits. if D=1 than it is 32

bits means use offset 32 bits

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Access rights byte

This byte describes how segment function in the system .The access right byte allows complete control over the

segment .

if segment is a data segment growth beyond its limits the microprocessor’s program is interrupt indicating

a general protected fault.

You can even specify if data can be written or it is write-protected.

The code segment is also controlled in similar fashion and can have reading inhibited to protect software

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Q: What are the purpose of access right bye in descriptor?

This byte describes how segment function in the system .

The access right byte allows complete control over the segment in protected mode

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Example The access rights byte of segment descriptor content (FE)16

.what type segment descriptor does it describe ,and what are its characteristics ?

Solution(FE)16=( 1111 1110 )2

Since bit3 is S=1 the access right byte is for code/data segment descriptor. Bite 4 E=1 segment is code segment This segment has the characteristics that followP=1 segment is mapped into physical memoryDPL=11 privilege level 11 lowerS=1 code or data segmentE=1 executable code segmentC=1 conforming code segmentR=1 readable code segmentA=0 segment has not been accessed

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FE1 1 1 1 1 1 1 0P=1DPL=11S=1 code or dataE=1 codeC=1 R=1A=0

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we have the following byte code and dataP DPL 1 1 -- -- A (access byte for code segment)P DPL 1 0 -- -- A (access byte for data segment)

Discuss the following access byteA(10011011) B(10010111) C(11110001)

solutionA(10011011)

P=1 present ,privilege level 00 highest , S=1 code or data E=1 code segment C=0 not conform R=1 read a=1 access

B(10010111)This is an access byte data segment, present ,access .privilege

level 00 highest .and both read and write accessibleC(11110001)

This is an access byte code segment ,present ,access .privilege level 11 lowest .and write protected

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Part twolecture 6

2020- 2021invisible-register

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Programming –invisible register

The global and local descriptor table is found in memory system.in order to access and specify the address of these tables.

The 80286 and above contain programming invisible registers. This registers are not directly address by software but it address by

system software. This register control the microprocessor when operated in protected

mode only Each segment register contains a program-invisible used in protected mode .The program-invisible register is a cache 0f 64 bits it is loaded

with base limit and access right each time the value of segment register is change.,

When a new segment value is placed in segment register the microprocessor access a descriptor table and loads the descriptors into

program-invisible register cache.

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Cs= 003B0000 0000 0011 1011

Index=7 TI=0 GDT

I take descriptor 7 [which have 8 byte] from GDT

Put it in cache in front to CS

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Cs= 003f0000 0000 0011 1111

Index=7 TI=1 RPL=11

I take descriptor 7 [which have 8 byte] from LDT

Put it in cache in frint to CS

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Protected Mode Register Model

1: Global Descriptor Table Register (GDTR).

2: Interrupt Descriptor Table Register (IDTR).

3: Local Descriptor Table Register (LDTR).

4: program invisible register (6 *64 bits cache for segments)

5: Task Register (TR).

6: control registers (CR0, CR1, CR2, and CR3) and Pentium add CR4.

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Notes

Size of limit in 80286 16 bits and base has 24 bits

While 80386 limit 20 bits and base 32 bits

80286 did not content FS and GS

Size of access right 8 bits in 80286 and 12 bits in 80386

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Global Descriptor Table Register (GDTR).

The content of GDTR defines a table in physical memory called Global Descriptor Table (GDT).

This GDT is one important element of the microprocessor memory management system in protected mode.

GDTR is located inside the processor. Each descriptor 8 byte provides information about the

limit(size), base (starting address), and access rights of a global memory segment.

The GDT provides a mechanism for defining the characteristics of the global memory address space.

Global memory is a general system resource that is shared by all software tasks.

GDT contains system segment descriptors. The limit which is 16 bits in 80286 and 20 bits in 80386 and above.it also content base which 24 bits for 80286

and 32 bits for 80386 and above .access right which is 8 bits for 80286 and 12 bits for 80386 and above

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Interrupt Descriptor Table Register (IDTR)

The IDTR defines a table in physical memory, this table contains interrupt descriptors not segment

descriptors. This register and table of descriptors provide the mechanism by which the microprocessor passes

program control to interrupt and exception service routines.

The IDTR is also 48-bits in length. The lower 2 bytes is LIMIT and higher 4-bytes in BASE.

The 80386 only supports up to 256 interrupts and exceptions.

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23hbase=2000

Limit =2323

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Local Descriptor Table Register (LDTR)

LDTR is part of the protected memory management support mechanism.

Each task can have access to its own private descriptor table in addition to global descriptor

table.

This private table is called the LDT and defines a local memory address space for use by the task.

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Task Register (TR)

The (TR) is a 16-bit register holds a selector that accesses a descriptor that defines a task.

The task is most often a procedure or application program. The descriptor for the procedure or application program is

stored in the GDT. The task register allows a context or task switch in about 17

µsec. The task switch allows multitasking systems to switch from

one task to another in a simple and orderly fashion. The content of TR is changed automatically whenever the

microprocessor executes an instruction that performs a task switch.

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Part two lecture 7

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example

Assume that base address of the LDT is ( 00 12 00 00)16 and the GDT base address is ( 00 10 00 00)16, if the value of the selector loaded into the CS register is 1007H. What is the requested privilege level? Is the segment descriptor in the GDT or LDT? What is the start address of the descriptor from descriptor table?

Solution:CS=(1007)16= (0001 0000 0000 0111)2

RPL = (11)2 = 3 Lowest Privilege LevelTI =1 the segment descriptor is in the LDT Index = (0001 0000 0000 0)2

Offset = index × 8 = (0001 0000 0000 0)2 × 8= (0001 0000 0000 0000)2 = 1000H

DESCRIPTOR address =LDT base+offsetDESCRIPTOR address = 00120000H + 1000H

= 00121000H

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BSAE 00 12 00 00CS=0000 0000 0001 0111

INDEX=0000 0000 0001 0 DES-NO=2

INDEX*8= 0000 0000 0001 0*8= 0000 0000 0001 0000=0010h

ADDRESSS=BASE+INDEX*8= 00 12 00 00 +0010

DESCRIPTIOR0 DES -1 DES=2

00 12 00 00 =B0 00 12 00 08= 00 12 0 10

00 12 00 01 =B1

00 12 00 02 =B2

00 12 00 03 =B3

00 12 00 04 =B4

00 12 00 05 =B5

00 12 00 06 =B6

00 12 00 07 =B7 00 12 00 0F

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Example:

Assume that limit 16 bits(80286)GDTR = (00 21 00 00 01 FF)16.LDTR cache = (00 31 00 00 03 CF)16.

1: What is the starting and ending address of the GDT? 2: How large is the table (GDT) in bytes?3: How many descriptors can be stored in this table? 4: What is the address range of the second descriptor in the GDT?5: If a value of 4004H is loaded into ES register, what is the requested privilege level? What is the address of the segment descriptor?6: If the selector loaded into LDTR is 0040H, what is the starting address of the LDT descriptor that is to be loaded into the cache?

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Solution:

1: start address of GDT GDT start = Base of GDTR= (00210000)16

End address of GDT GDT end = Base of GDTR + Limit of GDTR

= (00210000)16 + (01FF)16 = (002101FF)16

2: GDT size= Limit of GDTR + 1= 01FFH+1= 0200H = 512 bytes

3: No. of descriptors = table size / (descriptor size) = 512 bytes / 8 bytes = 64 descriptors.

4: START ADDRESS=BASE+NO-DES*8 =00210000+1*8second descriptor starts at 00210008H Second descriptor ends at 0021000FH.

136

Solution

5: ES = 4004H = (0100 0000 0000 0100)2

RPL= (00) 2 = 0 (Highest).TI = 1 LDT

Index=(0100 0000 0000 0) 2

Address of the segment descriptor = base of LDTR cache +Index × 8

= 00310000H + 4000H = 00314000H.

6: Starting address of LDT descriptor = base of GDT + LDTR = 00210000H + 0040 H = 0210040 H

137

Example:

in 80386 and above if base is (10 00 00 00) 16 and limit (1FF)16 what is the end address if G=0 and G=1Solution for G=0 for End address=base + limit =10 00 00 00 +0 01 FFhFor G=1 Limit is appended with (FFF) 16 to determine the end addressEnd address= 10 00 00 00 + 0 01 FF FF F =101FFFFF

138

Example:

what is the maximum value that should be assigned to LIMIT in the IDTR?

Solution:

The maximum table size in bytes is:

IDT size = 8 x 256 = 2048.

LIMIT = 0000011111111111 = 07FFH.

139

Example:

What is the address range of the last descriptor in the interrupt descriptor table defined by base address (00011000)16 and limit (01FF)16.

Solution:

IDTstart = (00011000)16.

IDTend = base + limit= (000111FF)16 .

The last descriptor in this table takes up the 8-bytes of memory from address (000111F8)16 through (000111FF)16.

140

examplewhat are the descriptor address and actual address in protected mode if logical address DS: 10H DS=13H and GDTR=(00 00 20 00 00 FF)16

Use instruction MOV Ax.[10H]Assume descriptor isOr Memory 00 00 20 10 =FF H 00 00 20 11= 0F H00 00 20 12 =00 00 00 20 13= 01 H00 00 20 14 =00 00 00 20 14= 00 H00 00 20 16 =00 00 00 20 17=00 H

141

Solution

DS=(13 )16= 0000 0000 0001 0011

RPL=11

Table index=0 global descriptor table

Selector=2

GDT base =00 00 20 00

GDT limit =00 FF

Descriptor address=GDT base +selector *8=(00 00 20 10)16

Actual memory address= segment base + effective address

=00 00 01 00+10=00 00 01 10

142

Example:

What are the descriptor address and actual address in protected mode if logical address DS: 10H DS=27H and GDTR= (00 00 20 00 00 FF)16 LDTR=(00 38)16

Use instruction MOV Ax.[10H]Assume descriptor is

Memory 00 00 20 38= 1F H 00 00 20 39= 0000 00 20 3A= 00 H 00 00 20 3B=0000 00 20 3C= 10 H 00 00 20 3D=0000 00 20 3E= 00 H 00 00 20 3F=00

143

Solution

DS=(27)16 =(0000 0000 0010 0111)2

RPL=11 lowestTI=1 local descriptor table Descriptor address =GDT base +LDTR=00 00 20 00 +00 38 =00 00 20 38From memory data descriptor Segment base= (00 10 00 00)16 limit=(1F 00)16

Actual address= segment base +effective address(00 10 00 00)16 + (10)16= (00 10 00 10)16

144

7المحاضرة رقم انتهاء


مع السلامه

.

145

Lecture-8Summary questions about

descriptor

Mohammad Mubarak

حساب

base limit access right

base ,limit and access right

GDTR=(10 20 30 40 50 60)باعطاء : 1

LDTR cache=(10 20 30 40 50 60)

Limit=(50 60)

Base=(10 20 30 40)

baseهي ل bytesاربعة اول

two byteهو اخر limitوال


الطريقه الثانيه •

start address and end addressاعطاء ••base=start address •Limit=end address – start address

Start address=(60 00 00)h end address(60 00 FF)hBase =(60 00 00)h limit=(60 00 FF)h- (60 00 00)h=FFHFor 80286 base=(60 00 00)h limit=(00 FF)hFor 80386 base=(00 60 00 00)h limit=(0 00 FF)h


اعطاء ال •

•limit (lest 4 bits of byt6 , byte1 , byte 0)

•base=(byte7 , byte 4 , byte3 , byte2)

•descriptor as 8 byte

حل مسائل

قوانين يلحل المسائل المتعلقه بهذا الفصل يجب ان تكون ملم

segmentعمل ال معرفة لحل المسائل اضاقه الى المتبعه register في الprotected mode وكذلك يجب معرفة

protected modeال في كيفبة النفاذ الى الجدولين المهمين والذي global descriptor table GDTوهما الجدول العام

localهو متاح لكل التطبيقات وكذلك الجدول الخاص descriptor table LDT 8192وكل جدول يحتوي على

descriptor وكلdescriptor 8مكون من byte تمثل

اهم القوانين هي

Start address to each descriptor (GDT or LDT) =base

End address to each descriptor (GDT or LDT)=base + limit

Size of each descriptor (GDT or LDT)= limit +1

Number of descriptor in each descriptor (GDT or LDT)=size/8

Range of any descriptor

Start of range =(number of descriptor)*8 + base

End of range =start address+8

Address of descriptor in byte to each descriptor= base + index *8

Where index is 13 bits (bits3 to bits 15) from segment register as we will see later

Address of descriptor which use to fill LDTR cache = base GDT +LDTR

Actual address=base + effective address

شرح

معرفة قبل البدء في حل المسائل يجب •

حيث تستقم ال Segment in protected modeاجزاء ال :1•

•2 bits request privilege level

•1 bits for table index to select if TI 0=GDT or 1=LDT

•13 index which is used to refer the number of descriptor

المعطات قي السؤال الى segmentلذلك يجب تحويل قيمة ال •binary لمعرفة اي جدول سنستخدم وكذلك رقم الdescriptor

RPLاضافة الى قيمة

كما قي الرسم التالي•

شرح

descriptorكثير من اسئلة الفصل تتم باعطاء قيمة ال : • start addressويطلب منك قيمة byteبثمانية ارقام descriptorوكذلك حالة ال end addressوكذلك قيمة بعض الاسئله في ومن الممكن access rightاو ما يعرف

end addressزكذلك start addressيعطي قيمة الحالتين يجب descriptorويرغب قي معرفة قيمة ال

descriptor format for 80286عليك ان تحقظ ال and 80386 الموضحه قي الرسم قي الاسفل

شرح

لذلك يجب access right byteكثير من الاسئلة متعلقه ب : •ويجب ان descriptorمن جدول ال byte 5تعلم بانه ال ان

وكما يلي في حالة كون byteلهذا ال ل bitsتعرف توزيع ال S=1 and E=1

systemفانها تعني 0=تميز اذا كان قيمتها Sحيث •descriptor اما اذا كانت قيمتS=1 فتعنيcode or data

segment descriptor

bitsنلاحظ قيمة ال code or data segmentولتميز هل هي E اذا كانE=0 فأنها تعنيdata segment اما اذا كانتE=1

وكما موصح في الرسم code segmentفانها

protectedالعامله في ال registersيجب معرفة كافة ال : mode كما قي الشكل

• ز

شرح

Protectedلها مايقابلها في ال segment register (CS,DS,SS,ES,GS,FS)كل •mode عبارة عنcache 64بحجم bits يتم يوضع فيها قيمة الdescriptor

base ,limit ,access rightبه وتمثل مثال لتنفيذ الايعاز •

•MOV AX,[10h] protected modeلمعرفة العنوان في ••Actual address=base +EA where base is the value of base for each

segmentبشكل GDTوالتي تستخدم لاملاء ال GDTR=48 bitsنلاحظ من الرسم ايضا وجود •

والتي ITDR interrupt descriptor table registerمباشر وكذلك وجود interrupt descriptor tableتستخدم لاملاء

لا interruptمع اختلاف واحد هو ان عدد ال GDTوهو من حيث العمل مشابه ل •عن limitوبذالك لا يمكن ان يزيد طول ال interrupt 256يتجاوز

256*8=(2048)

شرح

فتتم بصورة غير LDT (local descriptor table)اما املاء ال •مباشرة

cacheهنالك LDTRومقابل هذة ال LDTR =16 bitsباستخدام •64bit تدعىLDTR cache 64بطول bits تملاء بي محتويات

descriptor يتم اخذه منLDT والتي يطول LDTRمع محتويات base GDTيتم جمع LDTلملاء •

16 bits وسيكون الناتج هو عنوان الىGDT 8لغرض نقل bytes LDTلل base ,limit ,access rightوالتي سيمثل LDTR cacheالى

كما موضح قي الرسم

يمكن TSSDT(task descriptor table )هنالك جدول اخر يدعى •والتي بطول TRعن طريق استخدام LDTالوصول له بنفس طريقة

16 bits وبنفس الاسلوب للLDT

Question 1

assume the value of descriptor as show below find the start address and end address and status of descriptor

Solution

Base (start address)=(30 00 00 20)16

Limit =(8 10 8F)16

End address =base + limit

End address= (30 00 00 20)16 +(8 10 8F)16 = (30 08 10 AF)16

ز

P=1 segment is mapped into physical memory

DPL=00 privilege level 00

S=1 code or data segment descriptor

E=1 executable code segment

C=1 conforming code segment

R=1 readable code segment

A=1 segment has been accessed

Question 2

Assume GDTR = (00 21 00 00 01 FF)16. LDTR cache = (00 31 00 00 03 CF)16. 1: What is the starting and ending address of the GDT? 2: How large is the table (GDT) in bytes?3: How many descriptors can be stored in this table? 4: What is the address range of the second descriptor in the GDT?5: If a value of 4004H is loaded into ES register, what is the requested privilege level? What is the address of the segment descriptor?6: If the selector loaded into LDTR is 0040H, what is the starting address of the LDT descriptor that is to be loaded into the cache? 7: memory data as(00 21 00 40)16 = (FF 01 00 30)16

(00 21 00 44)16= (00 9F 50 40)16 what are the base and limit of LDT and how many descriptor it has?

(00 21 00 40)16 = (FF 01 00 30)16

(00 21 00 44)16= (00 9F 50 40)16

00 21 00 40=FF BASE=40 00 30 00

00 21 00 41=01 LIMIT =0 01 FF

00 21 00 42=00

00 21 00 43=30

00 21 00 44= 00

00 21 00 45= 9F

00 21 00 46=50

00 21 00 47=40

Solution:

1: GDT start = Base of GDTR= (00210000)16 GDT end = Base of GDTR + Limit of GDTR = (00210000)16 + (01FF)16 = (002101FF)16

2: GDT size= Limit of GDTR + 1= 01FFH+1= 0200H = 512 bytes3: No. of descriptors = table size / (descriptor size) = 512 bytes / 8 bytes = 64 descriptors.4: second descriptor starts=bsaeGDT+n0-des*8= 00 21 00 00+1*8=00210008End des= start+8=00210008+7=0021000FHStart at 00210008H And ends at 0021000FH.5: ES = 4004H = (0100 0000 0000 0100)2

RPL= (00) 2 = 0 (Highest). TI = 1 LDTAddress of the segment descriptor = base of LDTR cache +Index × 8

= 00310000H + 4000H = 00314000H.6: Starting address of LDT descriptor = base of GDT + LDTR = 00210000H + 0040 H = 0210040 H.

7: Base= (40 00 30 00)16 Limit =(0 01 FF)16

Size=limit +1 =(0 01 FF)16 =512 No of descriptor=512/8=64

Question 3Code a descriptor that describes a memory segment that begin at location (62 10 00)16and ends at location (62 10 FF)16 .this memory segment is code segment , present ,accessed and that can be read and it is not conform and high RPL the descriptor is an 80286 microprocessor Solution

Base=start=62 10 00 hLimit= end-start=62 10 ff -62 10 00=(00 ff)hAccess right=10011011=9BhS=1 E=1 A=1 E=1 C=0 R=1 DPL=00 P=1 access right=1 0 0 1 1 0 1 1=9BThe descriptor

Question 4

If the limit and base in global descriptor table are (0F FF)16 and (00 10 00 00)16.what is begin address of descriptor, size of the table in byte ,how many descriptor can store?

Solution

Begin address=base= (00 10 00 00)16

Size= limit +1 =(0F FF)16+1= (10 00)16 =8192 byte

Number of descriptor= 8192/8=1024 descriptor

Question 5

Assume that base address of the LDT is ( 00 12 00 00)16 and the GDT base address is ( 00 10 00 00)16, if the value of the selector loaded into the CS register is 1007H. What is the requested privilege level? Is the segment descriptor in the GDT or LDT? What is the start address of the descriptor from descriptor table?Solution:CS=(1007)16= (0001 0000 0000 0111)2

RPL=(11)2 =3 =lowest privilege levelTI =1 the segment descriptor is in the LDT Index = (0001 0000 0000 0)2

Offset = index × 8 = (0001 0000 0000 0)2 × 8= (0001 0000 0000 0000)2 = 1000H

DESCRIPTOR address = 00120000H + 1000H= 00121000H

Question 6

what are the descriptor address and actual address in protected mode if logical address DS: 10H DS=13H and GDTR=(00 00 20 00 00 FF)16


Or Memory 00 00 20 10 =FF H 00 00 20 11= 0F H00 00 20 12 =00 00 00 20 13= 01 H00 00 20 14 =00 00 00 20 14= 00 H00 00 20 16 =00 00 00 20 17=00 H

Solution

DS=(13 )16= 0000 0000 0001 0011RPL=11Table index=0 global descriptor table Index =(0000 0000 0001 0)binary=2GDT base =(00 00 20 00)16

GDT limit =00 FFDescriptor address=GDT base +index *8= (00 00 20 10)16

From memory data descriptor 2 has Segment base= (00 00 01 00)16 limit=(0F FF)16

Actual memory address= segment base + effective address= (00 00 01 00)16+(10)16= (00 00 01 10)16

Question 7

what are the descriptor address and actual address in protected mode if logical address DS: 10H DS=27H and GDTR= (00 00 20 00 00 FF)16

LDTR=(00 38)16


Memory 00 00 20 38= 1F H 00 00 20 39= 0000 00 20 3A= 00 H 00 00 20 3B=0000 00 20 3C= 10 H 00 00 20 3D=0000 00 20 3E= 00 H 00 00 20 3F=00

Solution

DS=(27)16 =(0000 0000 0010 0111)2

RPL=11 lowestTI=1 local descriptor table Descriptor address =GDT base +LDTR

=(00 00 20 00)16 +(00 38)16 = (00 00 20 38)16

From memory data descriptor Segment base= (00 10 00 00)16 limit=(1F 00)16

Actual address= segment base +effective address(00 10 00 00)16 + (10)16= (00 10 00 10)16

Question 8

The selector (02 24 )16 is loaded into the data segment .this value point to segment descriptor start address (00 10 02 20)16 in local descriptor table .if the word of descriptor are(00 10 02 20)16 = (01 10)16

(00 10 02 22)16 = (00 00)16

(00 10 02 24)16 = (1A 20)16

(00 10 02 26)16 = (00 00 )16

a)What are limit and base?b)If the segment of memory already loaded into physical memory? code segment or data segment?c)If EIP=(00 00 02 26)16 what is the physical of the next instruction to fetch from code segment ?

Solution

a)From Descriptor Base= (00 20 00 00)16 limit=(01 10)16

b) Access right = (1A)16 =(0001 1010)2

Since S=1 it is code or data segment

Since E=1 code segment

Code segment .not present ,not access , RPL=00 , readable ,not conform

c) Actual address= segment base +effective address

(00 20 00 00)16 + (00 00 02 26)16 = (00 20 02 26)16

Q9: What is relocated program or data?

A re locatable a program meant you can be placed it’s into any area of memory and executed without

change by use segment and offset schema.

The memory segment can be moved to any place in memory system without changing any of the offset addresses this is accomplished by moving the entire

program as block to new area and then changing only the contents of segment register

Q10 :what are the operation of segment register in protected mode?

Protected mode allows access to data and programs located within and above the first 1MB of memory. Microsoft Windows operates in protected mode.The segment registers are used differently in protected mode.They no longer store the segment address. Instead, they contain a selector that selects a descriptor from a descriptor table.A descriptor table can contain up to 8192 descriptors.Each descriptor has 8 byte.There are two types of descriptor tables:

– Global descriptors: contain segment definitions that apply to all programs.

– Local descriptors: unique to an application.A descriptor contains information about:

– Memory segment’s location– Length of the segment

Access rights

Q11: What are the purpose of access right bye in descriptor?

This byte describes function of segment in memory system in protected mode .

The access right byte allows complete control over the segment in protected mode

Q12: draw the Descriptor format for 80286 and 80386 and above

• .

Q13: what are the size of limit and base and access right in 80286 and 80386?

Size of limit in 80286 16 bits and base has 24 bits

While 80386 limit 20 bits and base 32 bits

80286 did not content FS and GS

Size of access right 8 bits in 80286 and 12 bits in 80386

Q14: draw all the register of 80386 in protected mode

• .

Q15 Select correct answer

•. The unit provides a four level protection mechanism for system's code and data against application program is:

• Segmentation unit

• Central Processing Unit

• Bus interface unit

• None of mentioned

Q15-2:Select correct answer

if the contents of the GDTR=00220000FFFF, there are

• 1024 descriptor tables

• 8192 descriptor tables

• (0022000003 *FF) descriptor tables

• (0022000003 *0F) descriptor tables


The GDTR is a

• 32 bits

• 16 bits

• 48 bits

• 42 bits


•The size limit of 80286 is

• 16 bits

• 10 bits

• 14 bits

• 12 bits


•The segment that will be accessed in the protected mode of 80386Mp are

• 4Kbyte to4Gbyte

• 10 to 20 Mbytes

• 20 to 30 Mbytes

• 30 to 40 Mbytes


•. A descriptor contains information about.

• Location

• Length

• Access right

• All above

•



مع السلامه

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190

Part threelecture-9

Advance computer technologyMohammed Mubark Salih

2020- 2021

Paging

Memory paging

The memory paging mechanism located within 80386 and above allows physical memory location to be assigned to any

liner address. The liner address is defined as address generated by program .The physical address is actual memory location accessed by a

program. With memory page unit the liner address is invisibly

translated to any physical address.Which allows an application written to function at a specific

address to reload through the paging mechanism .it also allows program to be placed into areas of physical

memory

Figure Page table and page entry

• .

Virtual memory

A CPU with virtual memory is fooled into thinking that it has access to an limited amount of physical memory (DRAM or main memory).

In virtual memory every time the CPU looks for certain information the operating system will first search in main memory and if it is not there it will

bring it into main memory from secondary memory(hard disk).

What happens if there is no room (space) in main memory? It is the job of operating system to swap data out of main memory and make room for new

data.

Operating system use LRU (last recently used )algorithm to swap data in and out main memory.

in LRU method the operating system keeps account of which data has been used the least number time in certain period and when swap need it swap

the least recently used data

Virtual memory implemented

To implemented virtual memory, two methods are used: 1: segmentation 2:paging.

In segmentation the size of data swapped in and out can size from 1 byte to few megabytes

(in 80386 ,80486 and Pentium the upper limit can be as high as 4 gigabytes).

In paging the size is a multiple of one page of 4096(4k) bytes. Paging is used widely since it prevents memory fragmentation.

If available memory becomes fragmented into small section of varied sizes the operating system must continuously move files around to make room for the new files

which could be any size which make the operation difficult.

Paging makes the job of operation system much easier since all the files will be multiple of 4k bytes .

if the size of files is not a multiple of 4k bytes. The operating system will leave the unused portion of 4kb page empty and the next file will placed on 4k boundary.

Assume the size of program store in H.D is 400 kbyteand size of page 4 kbyte physical memory 16 kbyte show the table of fill main

memory if you request the following page use LRU algorithm 1,2,3,4,6,1,3,7

.

Assume the size of program store in H.D is 400 kbyteand size of page 4 kbyte physical memory 16 kbyte show the

table of fill main memory if you request the following page use LRU algorithmm 1,5,3,2,1,6,3,7,6,3,5

Presence bit and dirty bits in paging

A presence bit (valid bit) in each location indicates whether the page has been transformed from auxiliary memory into main memory.

A =0 in the presence bit indicates that this page is not available in main memory.

If the presence bit (valid bit) in the word read from the page table is 0, it signifies that the content of the word referenced by the virtual

address does not reside in main memory.

A call to the operating system is then generated to fetch the required page from auxiliary memory and place it into main memory before

resuming computation.

Dirty bitsThere is a dirty bit which use if page altered while residing in main

memory this bit=1( change to page in main memory) otherwise this bit =0 when the page has not change in main memory?

How you address 64Ter byte of virtual memory

13 bits selector supplied by each segment register 8192 descriptors can be defended per

descriptor table two table(global and local)descriptor =16364 descriptor

Each descriptor 8k two descriptor 16k

Each segment 4Gigbytes memory segment

The maximum amount of virtual memory

16k * 4 G= 214 * 2 32=2 46= 26 * 240 =64Tbytes

Drawback 0f 80386 segmentation

1: variable segment size, which leads to memory fragmentation.

2: absence of what is call a dirty bit in the access byte of the descriptor table.

Q: Why should the operating system care if memory is altered(written into change)?

if the data is altered ,it is the job of operating system to save it on the disk to make sure that the hard disk always has latest data.

If the dirty bit is zero (D=0).it means that the data has not been altered and the operating system can ignore it when it needs room for new data (or code?) Since the original copy is on hard disk.

This will save time for the operating system.

If the dirty bit is one (D=1) ,the operating system must save the data before it lost and drop.

both problems of variable segment size and lack of dirty bit in segmentation are fixed in the paging method of virtual memory

Figure paged translation liner address to a

physical address

• .

Format of liner address

• .

Converting linear address to physical address

In paging, the linear address 32 bits is divided into three parts.

Offset (A11-A0) 12 bits

Page entry (A21_A12) 10 bits

Page directory (A31-A22) 10 bits

And there are two table

page directory

page table .

each entry to page directory 4 byte (32 bits)

Step1:How access page directory table

The upper 10 bit (A31_A22) of liner address are used for an entry into what called a page directory

There is a32 bit register CR3 ,inside the 386 that holds the physical base address of the page directory .

Work with 10 bit of linear address (A31-A22) points to entry of the page table directory

Step2: How access to page table

The out but of page directory table (20 bits) are adding with page value form linear address (A21-A12) to make entry to page table.

Each entry 4 byte(20 bits)

Step3: How access physical address

The output of page table 20bits work with offset of liner address (A11-A0) to access physical memory

Figure paging mechanism

• .

Example

Explain using diagram the translation of the linear address (03 01 00 8A)16 to physical address ,if the value of PDBA of CR3 is (00010)16

Assume page directory entry=(05001)16

and page table entry=(00030)16

solution(03 01 00 8A)16 =(0000 0011 00 00 0001 0000 0000 1000 1010)2dir=(00C)H page=(010)H offset= (08A)HDir =(0000 0011 00) 2= (0C)HPage =(00 0001 0000)2=(10)HOffset = (08A)16

Step1PDBA= (00010)16

Expanded PDBA to 32 bit = (00 01 00 00)16

Dir *2^2=2^2 * (0000 0011 00) =(0000 0011 0000) 2= (030)16

Enter to page directory table= (00 01 00 00)16 +(0 30)16 = (00 01 00 30)16

This location content =(05001)`16

step2expanded output of page directory to 32 bits=(05 00 10 00)`16

Page *2^2=2^2* (00 0001 0000)2= (00 00 01 00 00 00)2 =(40)16

Entry to page table ==(05 00 10 00)`1 +(40)16 =(05 00 10 40)16

This location content=(00030)16

Step3

Banding output of page table to 32 bits= =(00 03 00 00)16

The entry to physical memory =(00 03 00 00)16 +offset=(00 03 00 8A)

TLB (translation look –aside buffer)

Because the calculate the physical address from liner address in paging requires access to the page directory and page table, which are both

located in memory it consuming timeIntel use special type of cache called the TLB (translation look –aside

buffer). In the 80486 microprocessor, the cache holds the 32 most recent page

translation addresses .this means that the last 32 page table translations are stored in TLB, so

if the same area of memory is accessed ,the address is already presented in the TLB and access to the page directory and page table

is not required . this speeds program execution .

if translation is not in TLB , the translation from liner address to physical address calculation done by inter to page directory and page

table which consuming time and the new calculation store in TLB cache

Figure translation look aside buffer

• .

Why use TLB inside 386

The linear address must go through two level of translation table to get the actual physical address. this seems like a very long time and inefficient process and it is the reason for use of TLB cache .the TLB cache inside 386 holds the list of the most recently used physical address of the page frames when the CPU wants to access a piece of information (data or code) by providing the linear address , it first compare the 20 bit upper ) dir plus page ) address with the TLB to see if the table entry for the desired page is already inside the CPU . This result in two possibilities:

1:If match , it picks the 20 bit form TLB and adding its to 12 bits offset the result is the physical address 2:If it does not match , the CPU must enter to directory page table and page table to calculate the translation and record the result in TLB also find the physical address by adding its with 12bits offset the result is physical address



مع السلامه

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220

PART 3review question

paging

221

Q3-1Q3-1 Explain using diagram the translation of the linear address (03 01 00 8A)16 to physical address , if the value of PDBA of CR3 is (00010)16

Assume page directory entry =(05001)16 and page table entry=(00030)16

222

Solution

(03 01 00 8A)H = (0000 0011 00 00 0001 0000 0000 1000 1010)BDir =(0000 0011 00)B -> 2^2 *(0000 0011 00)B =(0000 0011 0000)B=(030)HPage =(00 0001 0000)B -> 2^2*(00 0001 0000)B= (0000 0100 0000)B=(040)HOffset = (08A)HExpanding 20 bits of (PDBA) (00010)H to 32bits by adding three digit zero = (00 01 00 00)HEnter to page directory table from address = expanded 32 bits PDBA+dir*2^2=

(00 01 00 00)H +(030)= (00 01 00 30)H output of this address from dir table=(0 50 01)H

Entry to page table from address=output from directory table (expanded to 32bit)+page*2^2(05 00 10 00)H +(040)H=(05 00 14 00) HThe out put of address (05 00 14 00) H from page table is (00030)HThe physical memory address = output of page table expanded to 32bits+offset(00 03 00 00)H +(08A)H=(00 03 00 8A)H

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Q3-2Q3-2: A processor is working in protected mode with PG = 1, and the value of PDBA = (28 6A0)H, Linear address = (A2 66 44 10)H , page table entry is (FF 66 42 60)H, page directory entry is

(36 28 A0 20)H , What is the physical address

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Solution:

Linear address = A2 66 44 10

=1010 0010 0110 0110 0100 0100 0001 0000

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Solution

(A2 66 44 10)H = (1010 0010 0110 0110 0100 0100 0001 0000)BDir =(289)H PAGE=(264)H offset=(410)HDir =(1010 0010 01)B -> 2^2 *(1010 0010 01)B =(1010 0010 0100)B=(A24)HPage =(10 0110 0100 )B-> 2^2*(10 0110 0100 )B= (10 01 1001 00 00)B=(990)HOffset = (410)HExpanding 20 bits of (PDBA) to 32bits by adding three digit zero = (28 6A 00 00)HEnter to page directory table from address = expanded 32 bits PDBA+dir*2^2=

(28 6A 00 00)H+ (A24)H= (28 6A 0A 24)Houtput of this address (28 6A 0A 24)H from dir table=( 36 28 A0 20 )H reset the least three digit to zeo= ( 36 28 A0 00 )H

Entry to page table from address=output from directory table +page*2^2

( 36 28 A0 00 )H+(990)H=( 36 28 A9 90 )HThe out put of address =( 36 28 A9 90 )H from page table is ( FF 66 42 60 )H reset the tree digit (FF 66 40 00)HThe physical memory address = output of page table expanded to 32bits+offset(FF 66 40 00)H +(410)H (FF 66 44 10)H

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Q3-3 If liner address is (67 45 30 8A) H how you translate its by paging to physical address (21 21 20 8A)H

SolutionLiner address=0110 0111 0100 0101 0011 0000 1000 1010)Dir=(19D)H page= (053)H offset=(08A)HDir*2^2= (0110 0111 0100)B= =(674)HPage*2^2=(0001 0100 1100)B=(14C)HOffset =(08A)HAssume PDBA=12345 page directory table entry=12345 and page table enter=21 21 2

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Q3-4: draw the mechanism using in Virtual memory

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Q3-5 what are drawback 0f 80386 segmentation?

There are two point of the drawbacks of 80386 segmentation

1: variable segment size, which leads to memory fragmentation.

2: absence of what is call a dirty bit which is use to show if data on main memory was change

dirty =1 (data must write to hard disk) and if it is not change dirty=0 did not need to save data on

hard disk.

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3-6: how virtual memory reach 64 Tbyte

The are two descriptor each one 8kbyte total 16kbyte=214

Each segment 4Gbyte=232

The maximum amount of virtual memory

16k * 4 G = 214 * 2 32=2 46= 26 * 240 =64Tbytes

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Q3-7/Choose the correct answer in each of the followingThe unit that is disabled in real address mode is

• Paging Unit • Central Processing Unit• Memory Management Unit• Bus Control Unit.

• Paging Unit • Central Processing Unit• Memory Management Unit• Bus Control Unit.

The unit that organizes the physical memory in term of pages of 4KB size each is:

• Segmentation unit• Instruction unit• Paging unit• Exaction unit•

• Segmentation unit• Instruction unit• Paging unit• Exaction unit•

The paging unit works under the control of

• Memory Management Unit• Exaction unit• Instruction unit• Segmentation unit

• Memory Management Unit• Exaction unit• Instruction unit• Segmentation unit

The unit provides a four level protection mechanism for system's code and data against application program is:

• Segmentation unit• Central Processing Unit• Paging unit• None of mentioned•

• Segmentation unit• Central Processing Unit• Paging unit• None of mentioned•

The unit provides a two level protection mechanism for system's code and data against application program is:

• Paging unit• Central Processing Unit• Segment unit• None of mentioned

• Paging unit• Central Processing Unit• Segment unit• None of mentioned

In paging to get the address of code or data, the 80386 convert from

• Physical to Logical• Physical to linear• Virtual to physical• Linear to physical

• Physical to Logical• Physical to linear• Virtual to physical• Linear to physical

3-8 what is Virtual Memory?

A CPU with virtual memory is fooled into thinking that it has access to an limited amount of physical memory (DRAM or main memory).

In virtual memory every time the CPU looks for certain information the operating system will first search in main memory and if it is not there it will bring it into main memory from secondary memory (hard disk).by use LRU algorithm

3-9 list all the mechanism using in Virtual memory

• To implemented virtual memory, two methods are used:

• 1: segmentation : it is implemented by use two descriptor GDT and LDT size of segment vary 1 to M or 4K to 4G

• 2:paging. It is implemented by using page directory table and page table with CR3(page directory base address(PDBA) size of paging 4K

3-10what are the benefit of Presence bit in paging

A presence bit (valid bit) in each location indicates whether the page has been transformed from auxiliary memory into main memory.

A =0 in the presence bit indicates that this page is not available in main memory. A call to the operating system is then generated to fetch the required page from auxiliary memory and place it into main memory before resuming computation.

3-11what are the benefit of dirty bits in paging

The a dirty bit is use to indicated that the page in main memory has be change or not change If page altered (update) while residing in main memory this bit=1( change to page in main memory) otherwise this bit =0 when the page has not change in main memory?

3-12 what are Drawback 0f 80386 segmentation

• There are two point of the drawbacks of 80386 segmentation

• 1: variable segment size, which leads to memory fragmentation.

• 2: absence of what is call a dirty bit in the access byte of the descriptor table.

3-13 draw how paged translation liner address to a physical address

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3-14why we use TLB (translation look –aside buffer),support your answer by drawing

Because the act of paging a 4K-byte section of memory requires access to the page directory and page table, which are both located in memory, Intel has incorporated special type of cache called the TLB (translation look –aside buffer). This cache used to store the 32 most recent page translation addresses .in this way we speeds program execution because we did not want to translate the liner address. if translation is not in TLB , the page directory and page table must be accessed separate TLBs for each of their instruction and data caches.

3-15 what are the fields of a linear address

• In paging, the linear address 32 bits is divided into three parts.

• Page directory (A31-A22) 10 bits

• Page entry (A21_A12) 10 bits

• Offset (A10-A0) 12 bits

3-16 draw the Segment translation

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3-17 draw the page translation

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3-18draw the segment and paging addressing mechanism

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3-19what are the different between segmentation and paging in 80386?

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Q20: Assume the size of program store in H.D is 400 kbyteand size of page 4 kbyte physical memory 16 kbyte show the table of fill main memory

if you request the following page by use LRU algorithm 1,5,3,2,1,6,3,7,6,3,5

Number of page= physical memory/page size=16k/4k=4 page

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مع السلامه

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Part one Lecture 1 2020- 2021 computer organization