Parasitic Inductance Effect on Switching Losses for

a High Frequency Dc-Dc Converter

Thomas Meade†, Dara O’Sullivan∗, Raymond Foley∗, Cristian Achimescu†, Michael Egan∗ and Paul McCloskey†

∗Department of Electrical Engineering,

University College Cork,

Cork, Ireland†Tyndall National Institute,

Lee Maltings,

Cork, Ireland

Email: paul.mccloskey@tyndall.ie

Abstract— This work examines the impact of packaging para-

sitics on the efficiency of a synchronous DC-DC buck converter.An anaytical model of the losses in the converter is developedand this is compared to practical results at switching frequenciesin the range of 1-2 MHz. The effect that the packaging parasiticinductance has on efficiency is highlighted by predicting theexpected losses from a converter with optimised packagingparasitics.

I. INTRODUCTION

The steady decrease in IC system voltages along with the

sharp rise in power requirements result in significant current

being delivered from the power supply [1]. This trend coupled

with the increase in switching speeds of power semiconductor

devices, due to the technology transfer from bipolar to MOS

based devices and the reduction in Rds(on) means that the

effect of packaging parasitics on power converter performance

is increasingly significant. As switching speeds increase, the

limiting factor in power device performance is shifting from

the silicon characteristics to the path inductance. This paper

uses an analytical approach to model converter losses and

efficiency. The effect of packaging inductance is included in

the model by incorporating inductance values extracted from

the packaging geometry using Ansoft Q3D. The analytical

model of a discrete component converter, in the frequency

range of 1-2 MHz, is verified with practical efficiency results.

The model is then applied to predict the efficiency of a 3 MHz,

1V, 20A converter using three different packaging techniques.

One technique is to use discrete devices on PCB, the next

technique is to use an integrated power-train incorporating

wire-bonds and the final technique is to use an innovative

wire-bond-free power train.

II. PACKAGING INDUCTANCE

The self inductance of a wire with rectangular cross section

can be derived using electromagnetic field theory and ‘geom-

etry mean distance’ as in [2]. The equation for self inductance

is given in (1), where l is the length of the wires, w and tare the width and thickness of the rectangular cross section,

respectively. The equation for mutual inductance between two

parallel wires is given in (2) for l > d, where d is the

separation distance and l is the length.

Lself =µ0l

2π

(

ln2l

w + t+ 0.5 + 0.22

(

w + t

l

))

(1)

Lmutual =µ0l

2π

(

ln2l

d− 1 +

d

l

)

(2)

It follows from (1), that to minimise the parasitic inductance

value, the length through which the current passes must be

minimised and the cross sectional area through which current

flows maximised.

Simulations were carried out in order to determine whether

a strategy of placing wire-bonds in parallel was more effective

at reducing the parasitic inductance value as opposed to using

a block of copper occupying the same total cross sectional area

of the wire-bonds. It was found that while placing wire-bonds

in parallel reduces the overall self inductance, the effect of

mutual inductance between the wires results in a higher overall

inductance. The formula for calculating the overall inductance

for two wire-bonds in parallel with current flowing in the same

direction is

Ltotal =Lself + Lmutual

2. (3)

In summary, packaging inductance is minimised by min-

imising current path length, maximising current path cross-

sectional area, and, where possible using a solid path, as

opposed to parallel paths. Such considerations have led to

innovative packaging techniques in power MOSFET design,

such as the DirectFET from International Rectifier [3].

III. MOSFET SWITCHING EQUATIONS

The circuit diagram of a synchronous buck converter with

the main power loop parasitics included is shown in Fig.1. It is

important to note that the loop includes the input decoupling

capacitor and its associated parasitic inductance. The parasitic

inductances shown are those which contribute to the switching

losses of the converter. In recent integrated converter power

trains [4], the inductances LS1 and LS2 have been effectively

978-1-4244-1874-9/08/$25.00 ©2008 IEEE 3

+-

VD

IoL

d1

Cin Load

High SideDriver

Ls1Ld2

Low SideDriver

Ld3

Ls2

Cout

Ld4

Fig. 1. Buck converter circuit with included parasitic inductance

VGH

RG

LD

CGS

+

-VD

CGD

CDS

LS

Fig. 2. Equivalent circuit for the main transition period

eliminated from the gate drive loop by connecting the source

terminal of the MOSFET directly to the driver inside an

integrated driver-MOSFET package, thus reducing the switch-

ing losses. In the analytical model developed, this source

inductance is included in the analysis but can be given a zero

value in the drive loop equations as the application requires.

In order to examine the effect of the parasitic inductances on

the switching losses of the high side MOSFET, the parasitic

inductances are grouped into two lumped values, with

LD = Ld1 + Ld2 + Ld3 + Ld4 + Ls2 (4)

and

LS = LS1. (5)

Each switching sequence, either from the off to the on state

or vice versa is divided into a number of separate intervals,

for which different conditions and constraints apply [5] [6].

The non-linear characteristics of the internal MOSFET capac-

itances [7] are included in the analysis.

A. Upper MOSFET Turn On Waveforms

Fig. 3 shows current and voltage waveforms during the turn

on of the upper MOSFET. This has four distinct time intervals,

described below.

1) Time interval 1: In this time period the gate voltage

rises to its threshold value. No drain current flows as long as

the gate voltage is less than the threshold voltage Vth. The

t

VGH

VDS

IDS

VGS

Current

&

Voltage

Io

TimeInterval 1

TimeInterval 2

TimeInterval 3

TimeInterval 4

t1

t2

t3

t4

Fig. 3. Current and voltage waveforms during MOSFET turn-on

time interval ends when the gate to source voltage equals the

threshold voltage.

VGS(t) = VGH ×(

1 − e−t

RG(CGD+CGS)

)

(6)

2) Time interval 2: In this time interval VGS(t) is greater

than Vth. Drain current, IDS(t) now rises. The change in

switching loop current induces a voltage across the parasitic

inductance and causes the drain to source voltage, VDS(t)(which in idealised switching waveforms [8] remains constant)

to fall. Writing equations around the switching loop as in [5]

yields:

VGS(t) = Aδ2VGS(t)

dt2+ B

dVGS(t)

dt+ VGS(t) (7)

where

A = RGgfsCGD(LD + LS) (8)

B = RG(CGD + CGS) + LSgfs. (9)

Solving (7) and piecing it together with the equation for

VGS(t) in time interval 1 [Eqn. (6)], yields:

VGS(t) = VB1 − VB2e−(t−t1)

T1

×(

cosω1(t − t1) +sin ω1(t − t1)

ω1T1

)

if 4A − B2 ≥ 0

(10)

and

VGS(t) = VB1 −VB2

T2 − T3

×(

T2e−(t−t1)

T2 − T3e−(t−t1)

T3

)

if 4A − B2 < 0 (11)

where

ω21 =

4A − B2

4A2, (12)

T1 =2A

B, (13)

T2 =2A

B +√

B2 − 4A, (14)

4

and

T3 =2A

B −√

B2 − 4A. (15)

VGH is the applied gate voltage and gfs is the forward

transconductance of the MOSFET. During turn-on

VB1 = VGH (16)

and

VB2 = VGH − Vth, (17)

while during the turn-off transient

VB1 = 0 (18)

and

VB2 = −Io

gfs + Vth

(19)

where I0 is the full load current. IDS(t) and VDS(t) of the

MOSFET for this time period can be calculated using (20) and

(21) based on VGS(t). This time interval comes to an end at

time t2 when IDS(t) rises to I0 or VDS(t) falls to I0RDSon,

whichever occurs first.

IDS(t) = gfs(VGS(t) − Vth) (20)

VDS(t) = VD − (LD + LS)dIDS(t)

dt(21)

3) Time interval 3: In this time interval either VDS(t)completes its fall or IDS(t) completes its rise. Consider first

the drain voltage completing its fall, IDS(t) having risen to

I0. Since the drain current is constant, VGS(t) must also be

constant:

VGS(t) = Vth +I0

gfs

. (22)

The drain to source voltage in this time period is given by:

VDS(t) = VDS(t2) −

(

VGH − (Vth + I0gfs

)

RGCGD

)

(t − t2) (23)

where VDS(t2) is the drain to source voltage at the start of

this time period, and t2 is the time at which IDS rises to full

load current. The time period ends at time t3 when VDS(t)completes its fall to I0RDSon.

Consider now the situation where the current completes its rise

during the third time interval,VDS(t) having already completed

its fall. IDS(t) and VGS(t) are given by:

IDS(t) = IDS(t2) +

(

VD

LD + LS

)

(t − t2) (24)

where VD is the applied dc input voltage and IDS(t2) is the

drain to source current at the start of this time period, and t2in this case is the time at which the drain voltage drops to

I0RDSon.

Current

&

Voltage

VDS

IDS

VGS

Vpeak

t

TimeInterval 2

TimeInterval 1

TimeInterval 3

TimeInterval 4

t4

t3

t2

t1

Fig. 4. Current and voltage waveforms during MOSFET turn-off

VGS(t) =

(

VGH − VGS(t2) −Ls

LD + LS

VD

)

×(

1 − e−(t−t2)

RG(CGD+CGS)

)

+ VGS(t2)

(25)

4) Time interval 4: In this time interval the gate to source

voltage completes its charge to the level of applied drive

voltage VGH .

VGS(t) = (VGH − VGS(t3))

×(

1 − e−(t−t3)

RG(CGD+CGS)

)

+ VGS(t3) (26)

B. Upper MOSFET Turn Off Waveforms

A similar analysis may be performed during the turn-off

transition of the upper MOSFET, using the waveforms shown

in Fig. 4.

1) Time interval 1: In time interval 1, the gate source

voltage, VGS(t) falls at a rate determined by the time constant

RG(CGD + CGS). There is no change to the drain current

or drain to source voltage until the value of VGS(t) falls to

VGS(th) + I0/gfs. This is the gate voltage needed to sustain

drain current I0. The gate to source voltage during this period

is given by:

VGS(t) = VGHe−t

RG(CGS+CGD) . (27)

This interval ends at time t1 when VGS(t) falls to a value of

VGS(th) + I0gfs

.

2) Time Interval 2: In this time period the drain to source

voltage rises to VD, the applied dc input voltage. The drain

current remains constant at I0 and the gate to source voltage

stays constant at VGS(th) + I0gfs

. The drain to source voltage

during this time period rises according to the following equa-

tion:

VDS(t) =

(

gfsVGS(th) + I0

(1 + gfsRG)CGD + CDS

)

(t − t1). (28)

5

This time period comes to an end at time t2 when VDS(t)rises to VD .

3) Time Interval 3: As with the second time interval during

turn-on, both the drain current and drain voltage change. A

change in the drain current produces a change in the voltage

across the parasitic inductances LS and LD. A current flow

through the capacitance CGD is produced. This current flow

restrains the rate of decrease of the gate voltage, which in

turn restrains the original rate of change of drain current. The

gate to source voltage during this period is given by (29) or

(30). During this time interval IDS(t) falls from I0 to zero

according to (20) and VDS(t) changes in accordance with (21).

This time interval comes to an end at time t3 when VGS(t)falls to the threshold voltage VGS(th).

VGS(t) = VB1 − VB2e−(t−t2)

T1

×(

cosω1(t − t2) +sinω1(t − t2)

ω1T1

)

if 4A − B2 ≥ 0

(29)

VGS(t) = VB1 −VB2

T2 − T3

×(

T2e−(t−t2)

T2 − T3e−(t−t2)

T3

)

if 4A − B2 < 0 (30)

T1, T2, T3 and ω1 are as given previously for turn-on interval

2. Also

VB1 = 0 (31)

and

VB2 = −(I0/gfs + VGS(th)). (32)

4) Time interval 4: At the end of time interval 3, the drain

current has fallen to zero, but the drain voltage VDS(t3) is

greater than the circuit voltage VIN . The drain capacitance

CDS “rings” with the stray circuit inductance. The stray circuit

resistance Rl damps the oscillation. The drain voltage is given

by:

VDS(t) = VIN + (VDS(t3) − VIN )e−(t−t3)

T4 cos(ω4(t − t3))(33)

where

T4 =2LD

Rl

(34)

and

ω4 =

√

4LDCDS − C2DSR2

l

2LDCDS

. (35)

The gate voltage decays to zero with time constant RG(CGD+CGS). The gate to source voltage is given by:

VGS(t) = VGS(t3)e−(t−t3)

RG(CGD+CGS) . (36)

IV. SOURCES OF POWER LOSS

A. Crossover Switching Loss

The turn-on switching loss can be calculated using the turn-

on switching waveforms derived in Section III

Pon(loss) = FSW

∫ t3

t1

VDS(t) · IDS(t)dt (37)

where FSW is the switching frequency of the converter.

Similarly, the turn-off switching losses are calculated from

Poff(loss) = FSW

∫ t3

t1

VDS(t) · IDS(t)dt. (38)

B. Conduction Loss

The upper MOSFET conduction loss is given by:

Pcond−upper =

(

I20 +

∆I20

12

)

DRDS(on−upper) (39)

where ∆I0 is the ripple of the load current I0, D is the duty

cycle and RDS(on−upper) is the is the on-state resistance of

the top switch.

The lower MOSFET conduction loss is given by:

Pcond−lower =

(

I20 +

∆I20

12

)

(1 − D)RDS(on−lower). (40)

C. Gate Drive Loss

Most of the switch losses associated with charging and

discharging the MOSFET gate are dissipated in the driver IC

since the source and sink resistances of the driver IC are much

greater than the MOSFET’s internal gate resistance. The gate

drive loss of the upper MOSFET is given, as in [9], by:

PG−upper = QgVGHFsw. (41)

A similar equation holds for the gate drive of the lower

MOSFET.

D. Reverse Recovery and Ringing Turn On

The reverse recovery and ringing power loss is calculated

as in [7], via

PRRR(on) = FSW

(

VDQRR(lower) +1

2Qoss(lower)VD

)

(42)

where QRR(lower) is the reverse recovery charge for the lower

MOSFET, which is dependant on the loop inductance [7], and

Qoss(lower) is the charge stored in CGD + CDS of the lower

MOSFET.

6

IIN(cap)RMS =

√

√

√

√

[

(ISW (pk) − IIN(avg))2 +∆I2

SW (pp)

12

]

· D + I2IN(avg) · (1 − D) (46)

E. Reverse Recovery and Ringing Energy Turn Off

The reverse recovery ringing power loss during MOSFET

turn-off is given by

PRRR(off) = FSW

1

2

(

Qoss(V peak)Vpeak − Qoss(VD)VD

)

(43)

where Qoss(V peak) is the charge stored in CGS + CGD of

the upper MOSFET when the voltage reaches its peak value,

Vpeak . Qoss(VD) is the charge stored in CGS + CGD of the

upper MOSFET when the voltage reaches its steady state

value, VD.

F. Diode Conduction Loss

The average power loss in the synchronous diode is given

by:

Pdiode = VfrI0−vTd1FSW + VfrI0−pTd2FSW (44)

where Vfr is the forward voltage drop, Td1 and Td2 are the

dead-times when the diode is conducting, I0−v is the valley

value of the load current I0 and I0−p is the peak value of the

load current I0.

G. Other Losses

Losses in the input and output capacitors as well as the

power inductor must also be considered to accurately model

the overall converter loss. The input capacitor power loss can

be calculated from

PIN(cap) = I2IN(cap)RMSResr−IN(cap) (45)

where the rms capacitor current, IIN(cap)RMS , is calculated

from (46) above and

IIN(avg) =VoutIout

ηVIN

. (47)

ISW and η are the top-switch current and converter power-

train efficiency respectively. The ac component of the load

current generates a power loss in the output capacitors. This

is given by

POUT (cap) = ∆I20(RMS)Resr−OUT (cap) (48)

The power inductor losses comprise of hysteresis and eddy-

current losses in the core and winding resistive losses. Total

losses are calculated using a vendor-specified procedure [10]

for the inductor used in the design.

Fig. 5 shows the theoretical loss breakdown of the designed

converter operating at three different frequencies. The most

notable difference between the loss breakdowns as the fre-

quency is increased is the change in the switching loss of the

converter, and in particular, the upper MOSFET turn-off power

loss, Poff .

Upp

er M

OS C

ondu

ctio

n Los

s

Low

er M

OS C

ondu

ctio

n Los

s

Rev

erse

Rec

over

y an

d Rin

ging

Tur

n O

n

Rin

ging

Tur

n O

ff

Bod

y D

iode

Con

duct

ion

Los

s

Gat

e-D

rive

Upp

er

Gat

e-D

rive

Low

er

Inpu

t Cap

acito

r

Iutp

ut C

apac

itor

P on P off

Indu

ctor

Los

s

Wire Los

s

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Po

wer

Lo

ss (

W)

534 kHz

1.5 MHz

1.9 MHz

Fig. 5. Theoretical breakdown of power-converter losses at three differentfrequencies

V. PRACTICAL DC-DC CONVERTER

A practical DC-DC converter as shown in Fig. 8 was built in

order to verify the analytical power loss equations. The output

voltage is 1V, the input voltage is 12V and the inductor value

is 300 nH. The parasitic inductances were extracted from the

layout diagram, shown in Fig. 9, using the software package

Ansoft Q3D. The extracted inductances are LD=6.03 nH and

LS=1.65 nH. Oscilliscope plots of VGS and VDS during the

MOSFET turn-on and turn-off transitions with a 20 A output

current are shown in Figs. 6 and 7 respectively.

Graphs of the efficiency versus load current for three

different switching frequencies are shown in Fig. 10. These

results show good correlation between the analytical model

that has been developed (theoretical values) and the measured

practical values.

A. Effect of Parasitic Inductance on a 3 MHz converter

Having validated the analytical model in a discrete-

component converter, it is possible to utilise the model for

predicting the converter efficiency at higher switching frequen-

cies, and to examine the effect of using alternative packaging

technologies at these frequencies. A similar power converter

is modelled at a switching frequency of 3 MHz, with packag-

ing parasitic inductances corresponding to (a) discrete power

devices, (b) currently available wire-bonded power trains, and

(c) an innovative wire-bond-free packaging technique using

copper as the interconnect medium. A comparison between the

switching losses of the three converters is shown in Fig. 11. As

is evident from Fig. 11, a higher parasitic inductance slightly

reduces the turn-on switching losses (with LS = 0), but

7

Fig. 6. MOSFET turn on voltage waveforms

Fig. 7. MOSFET turn off voltage waveforms

significantly increases the turn-off loss. The overall effect of

the changes in parasitic inductance on converter efficiency can

be seen in Fig. 12. Clearly, currently available wire-bonded

co-packaged power trains offer a significant advantage—in

terms of efficiency at a 3MHz switching frequency—over

designs using discrete components; however, the residual

parasitic inductance of even this approach limits the overall

converter efficiency. The plot predicts that the most appropriate

packaging strategy for a power converter at this frequency is

one which uses a wire-bond-free approach.

VI. CONCLUSION

This paper has presented an analytical model for a buck

converter which has been verified experimentally. The effect of

Fig. 8. Buck converter as implemented

Fig. 9. Layout diagram for the power stage of the converter

parasitic inductance on the switching losses has been examined

in detail. A loss model for a high frequency converter is

proposed in order to outline the impact of parasitic inductance

on efficiency and to highlight the deficiencies of using discrete

devices and a layout which are not optimised for minimum

parasitic inductance. The guidelines needed to reduce the

critical parasitic inductance values are also presented.

8

0 2 4 6 8 10 12 14 16 18 20 22 240

40

45

50

55

60

65

70

75

80

85

Eff

icie

ncy (

%)

Io (A)

Theoretical

Practical

(a) FSW =534 kHz

0 2 4 6 8 10 12 14 16 18 20 22 240

40

45

50

55

60

65

70

75

80

85

Eff

icie

ncy (

%)

Io (A)

Theoretical

Practical

(b) FSW =1.5 MHz

0 2 4 6 8 10 12 14 16 18 20 22 240

40

45

50

55

60

65

70

75

80

85

Eff

icie

ncy (

%)

Io (A)

Theoretical

Practical

(c) FSW =1.9MHz

Fig. 10. Efficiency vs. load current

REFERENCES

[1] D. Staffiere and M. Mankikar, “Power technology roadmap for IT powersupplies,” in Proc. IEEE Appl. Power Electron. Conf., Mar. 2001, pp.49–53.

[2] X. Qi, G. Wang, Z. Yu, R. W. Dutton, T. Young, and N. Chang, “On-chip inductance modeling and RLC extraction of VLSI interconnects for

Discrete Power DevicesWire-bonded Power TrainWire-bond-free Packaging

0

2

4

6

8

10

Pon

Poff

Pow

er

Loss

(W

)

Fig. 11. The effect of parasitic inductance on switching losses at 3MHz withIo = 20 A

10 12 14 16 18 20 22 24 26 28 300

40

45

50

55

60

65

70

75

80

Eff

icie

ncy (

%)

Io (A)

Discrete Power Devices

Wire-bonded Power Train

Wire-bond-free Packaging

Fig. 12. Efficiency comparison at 3 MHz for three packaging techniques

circuit simulation,” in Proc. Custom Int. Circuits Conf., May 2000, pp.487–490.

[3] A. Sawle, M. Standing, T. Sammon, and A. Woodworth. Directfet -a proprietary new source mounted power package for board mountedpower. International Rectifier. Surrey, England. [Online]. Available:http://www.irf.com/technical-info/whitepaper/directfet.pdf

[4] Philips PIP212-12M datasheet. [Online]. Available: http://www.nxp.com/acrobat/datasheets/PIP212-12M 4.pdf

[5] Y. Xiao, H. Shah, T. Chow, and R. Gutmann, “Analytical modelingand experimental evaluation of interconnect parasitic inductance onMOSFET switching characteristics,” 2004, pp. 516–521.

[6] “Hexfet power MOSFET designer’s manual,” International Rectifier, ch.11.

[7] Y. Rena, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of powerMOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319,Mar. 2006.

[8] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics

Converters, Applications and Design. John Wiley and Sons, ch. 22.[9] L. Balogh, “A design and application guide for high speed power

MOSFET gate drive circuits,” 2001, Unitrode Power Supply DesignSeminar.

[10] “IHLP-5050 application note,” Vishay Dale, 2006, unpublished.

9