OPTICAL REVIEW Vol. 1, No. I (1994) 20-23

Parallel MOdified Signed-Digit Computlng fOr Large Scale TWO DimensiOnal Data Array Hongxin HUANG, Masahide ITOH and Toyohiko YATAGAI Institute of Applied Physics, University of Tsukuba, Tsukuba, Ibaraki 305, Japan

(Accepted August 15, 1994)

We propose a novel parallel algorithm of modified signed-digit (MSD) computing, in which MSD digits are encoded to three bit plane (BP) patterns. The addition of two MSD data arrays is performed with two steps: calculating nine intermediate patterns from encoded BP patterns and calculating three BP patterns with the nine intermediate patterns. A system module constucted with nine beam splitter cubes is developed for optical

demonstration. Preliminary experimental results are given.

Key words : modified signed digit number system, parallel optical computing

1. Introduction

Parallel computing of data arrays plays an important role in modern application sciences. Optics, because of its

inherent 2D parallelism and flexible global intercon-nectivity, has been used for realizing high-speed comput-ing. Parallel analog computing, such as image addition, image multiplication, 2D Fourier transformation and cor. relation, has been advanced by optical technology.1) For overcoming the constraints on accuracy and flexibility of

analog optical computing, numerous digital optical computing techniques have been proposed for parallel processing. One of such approaches is modified signed-digit (MSD) computing. The number system of MSD computing uses three digits 1, O and I in the conversional

binary system.2) The inherent redundancy of MSD system limits the carry propagation only two bit positions to left,

thus the addition can be performed in three steps3) in-dependent on the length of MSD string. Generally, MSD computing can be implemented by using optical symbolic substitution.4~6) Recently, MSD computing systems using optical fan-out elements and correlation7) and using optical

10gic arrays and a hybrid system8) have been demonstrated.

We have also proposed a one-step algorithm for MSD computing by using three bit pairs simultaneously and demonstrated it with an optical correlation system.9) The

729 terms of one-step addition truth-table have been minimized to 68 minterms based on redundant bit repre-sentation of MSD digits.

In this paper, we present a novel parallel implementa-tion of MSD computing. It is shown that MSD addition is performed by 12 intermediate patterns derived from 68 minterms of one-step MSD addition. A new scheme using three separated patterns to encode an MSD digit array is proposed. A system module is constructed by using nine bearn splitter cubes for optical demonstration. The present

scheme uses pattern duplication, combination and shifting as three basic operations, instead of optical logic and threshold operations. Therefore the method has high throughput and is suitable for processing large-scale data

arrays .

2. MSD Addition Algorithm

For operations on two MSD data arrays, MSD digit is encoded with three bit plane (BP) patterns as shown in Fig. 1(a): If the MSD digit is 1, the corresponding pixel of

pattern BP-1 is I (transparent), whereas the pixels of patterns BP-1 and BP-1 are O (opaque), Similarly, if the MSD digit is O, then the pixel of pattern BP-O is I and the

pixels of patterns BP-1 and BP-1 are O. If the MSD digit is

1, then the pixel of pattern BP-1 is I and the pixels of patterns BP-1 and BP-O are O. Since we use, simultaneous-ly, three-position bit pairs: the current-position, the next-

10wer-order-position and the second-10wer-order-position bit pairs for obtaining an output bit in our one-step algorithm,9) in order to obtain correctly the least significant bit of the result, we pad two zero bit pairs at the

right of the least significant bit of input operands. Similar-

ly, the addition result of two nbit MSD numbers will generally be (n+1)bit number, in order to find correctly the (n+1)th output bit, one zero bit pair must be padded at the left of the most signiflcant bit of the input operands.

For evading the cross talks between two adjacent data of an MSD data array two zeros are padded at the right of the least significant bit of each datum and one zero is padded at the left 0L the most significant bit of the first column

data as shown in Fig. 1(b). Therefore, an M >< N n-bit MSD array is recorded on three BP patterns of (M(n+2)+ 1) X N elements and one BP pattern is the complement of the sum pattern of other two BP patterns.

The addition of two MSD data arrays is perL0rmed in the following two steps. First, according to six encoding BP patterns Aj and ~j ~=1, O, 1) of two input arrays A and B, nine intermediate patterns fi (i=0,...,8) are calcu-

lated by

f0=A1*B1, (1)

f =A1*B0+AO*B1, (2)

f2=A1*B1+AO*B0+A1*~1, (3)

~=A1*B0+AO*Bl, (4)

fi=A1*Bl, (5)

20

OPTICAL REVIEW Vol. 1, No. I (1994)

l opaque Cll transparent

( a)

1111 oooo 1111 1111 1111 oooo 1100 ooll olll

//// tttt\\\\

}

lIII 111111111DDDlll IDDC]DI Ill 11111 Illll I IDlllIII IDII IDIDll IDDD[]llIII Ill 11111 l lIII 111 DIICllll 11 111 IDI Ill lII CIIlll IC!1 ll

DlllIDDDDDDDC]lllIDD DIII IIDI 111DDC]DDDCICl DII DDDDDDlIDDDII I CID

Padded zeros

BP-1

BP-1

BP-O

(b)

Fig. 1. Optical bit-plane (BP) encoding of MSD digits (a), and an example for encoding an MSD data array.

J~=(A1+A1)*B0+AO*(B1+B1), (6)

j;=(A1+A1)*(B1+B1)+AO*BO, (7)

f,=A1*Bl+A1*~0+AO*B1, (8)

f8=A1+AO*B1+AO*B0+A1*B1. (9)

In the second step, the BP patterns Cj of the result array

C are obtained by

C1--f**f*'+f6*f3'*f8"+f=*f*'*f8" (10) C1=f6*fo +f6*f *fi"+f5*f3 *f"+f=*f2 (11) CO~j~*(/: +fi )+f5*f *fi"+f5*f3 *~"

+f**f,'+f6*f'*f8"+f6*f3'*f," (12) where "+" and * denote pixel-wise addition and multipli-'' ''

cation, and f.' and f." are patterns shifted f. by one and two

pixels to left, respectively. Because of the encoding method of Fig. 1, only the three addition cases of 1+0, 9+

21

1 and 0+0, and four multiplication cases 1*O, O*1, O*O and 1*1 exist in above pixel.wise operations of pattern, where 1 and O are values of the pixels on the bit plane patterns.

Equation (12) is not necessary because output O can be regarded as neither I nor 1.

3. Optical Implementation

As no addition of 1+1 exists in the above Eqs. (1)-(12). all pixel values are either O or 1, therefore, the threshold

operation is not necessary. The implementation can be performed with an optical system constructed by mirrors, beam splitters, and bearn combiners. Figure 2 shows a proposed system module made up of nine beam splitter cubes for calculating previous equations. There are eight input planes Pij (i=1,...,4 and j=1, 2) and one desired output plane Po' A beam splitter superposes two light beams modulated by two orthogonal input planes, respec-tively, and results two equivalent outputs. The output obtained at the plane Po is generally given by

po = L ( pl I ~ pl2)*p21 Hr p22 1 *p42+ L ( pl I + pl2)*p32 + p3 1 1 *p4 1

(13)

where pij is the transmittance of the input mask at the plane Pij. A11 the nine intermediate patterns can be per-formed by using the system module with proper arrange-ment of BP patterns at the input planes. For example, when BP patterns BO, A1, AO and B1 are inputted at the planes P31, P41, P22 and P42' and planes P11' P12' P21' P32 are

blacked, respectively, the pattern f is obtained at the plane

Collimated beam

Po

Fig. 2. Optical system module for implementing the proposed MSD algorithm .

Table I . Relations between locations of input patterns with the output pattern of Fig. 2. 1) OFF means a fully black pattern and ON means a fully white pattern. 2) two patterns are superposed.

Po Pll P12 P21 P22 P3 l P32 P4 l P4 2

j~

f fi

f;

fi

f j:;

fi

f*

C1 C1

OFF+)

OFF OFF OFF OFF OFF A1 OFF OFF j~" fi "

OFF OFF A1 OFF OFF ON A1 ON ON OFF OFF

OFF OFF OFF OFF OFF A1 BI OFF AO j~'

f '

OFF AO A1 AO OFF Al OFF AO A1 fi'

j;'

B1 BO AO.BO')

BO B1 B1 AO.BO BO AO.BO OFF fi'

OFF OFF B1 OFF OFF B1 B1 B1 A1 f '

J~'

A1 A1 ON*) A1 A1 AO ON A1 ON J~

j;

OFF B1 B1 B1 OFF BO ON B1 B1 J~

J~

22

O 10 -5 -15 1 11 -6 O 2 12 -7 1 3 13- -8 2 4 14 -9 3 5 15 -10 4 6 -1 -11 5 7 -2 -12 6 8 -3 -13 7 9 -4 -14 8

array A

O I -9 -lO 2 3 -11 -12 4 5 -13 -14 6 7 -15 8 9 1

10 11 3 12 13 5 14 15 7 -5 -6 9 10 -7 -8 11 12

array B

(a)

(b)

O 11 -14 3 14 -17 6 17 -20 9 20 -23 12 23 -8 15 26 -7 18 12 -6 21 13 -5 3 -9 -4 2-12 -3

arTay C

-25 -12 -13

2 5 8 11

14 17 20

(c)

Fig. 3. An example for explaining parallel MSD algorithm proposed, (a) Two input data arrays A and B, and corresponding six encoded bit plane patterns, (b) nine intermediate patterns, (c) bit plane patterns of sum array C and the result in decimal form.

Po' By using nine individual system modules, all nine intermediate patterns can be performed simultaneously. The patterns C1 and Cl can also be performed with the system module of Fig. 2. Table I gives the details of arrangements of input BP patterns for each calculation. The pattern CO of result array can be found by using a similar system module.

4. Experiruents

For illustrating the proposed parallel algorithm of MSD addition, computer simulations and optical experiments have been carried out. Figure 3 shows an example of computer simulation. Two 4-bit 4 x 10 input data arrays A and B and the encoding BP patterns are shown in the left and right of Fig. 3(a), respectively. Figure 3(b) shows the

nine intermediate patterns calculated by Eqs. (1)-(9) respectively. The BP patterns of sum array C and the results in decimal form are given in the left and right columns of Fig. 3(c), respectively.

A system module is constructed with nine I : I beam splitter cubes. Figure 4 shows photographs of preliminary experimental results. The input data arrays A and B used for experiments are the same as the first two columns of the arrays A and B shown in Fig. 3(a), respectively.

(a)

H. HUANG et al.

(b)

Fig. 4. Experimental photographs. (a) and (b) intermediate patterns j~ and J~, (c) and (d) the result bit plane patterns C1 and Cl.

Figures 4(a) and 4(b) show two intermediate patterns j~ and f5' The patterns C1 and C1 are shown in Figs. 4(c) and

4(d). The input masks are made by an OHP film and the pixel size is 0.42 mm. Figure 4 shows that the results well

agree with the theoretical prediction.

5. Discussion

The achievable information throughput is an important parameter in evaluating a parallel computing system. For

the MSD computing system presented, the relation between input patterns and the output pattern are pixel to

pixel image, thus the throughput is determined by the diameter D of beam aperture and the resolvable pixel size. The available pixel size (~ must be satisfied bylo)

(~2>>~l , (14) where I is a distance between the input plane and the shadow imaging plane. Assuming the condition of Eq. (14), we adopt the pixel size

(~=1/I~~T . (15) Then the throughput T is given by

_ D )2_ D2 (

~ (~ ~10~1 ' In our experirnental system, the aperture diameter D=8 mm, the maximum distance l=33 mm and the wavelength ~ =0.633 pm, gives a throughput of T=5 x 102.

The information throughput can be greatly increased by

using a lens imaging, which is realized by a lens-bearnsplitter complex element, for example. The resolv-able pixel size (5:L is determined (assuming diffraction limi-

tation) by

~ -'L~~~L (17) L~ DL ' where DL denotes an effective diameter of lens and f is focal length. The throughput Tlens is

2= )2 = L) ( . ( D DL2 Tlens (5jL 1.22~f (18)

OPTICAL REVIEW Vol. 1, No. I (1994) 23

If DL=8 mm, f=10 mm and ~ =0.633 pm then Tle*s=6.9 X 107, which means two 32-bit 2XI06 data arrays can be added

concurrently.

6. Conclusion

A novel parallel algorithm of MSD computing and an optical irnplementing architecture are proposed and demonstrated. Since all the optical procedures can be performed concurrently, the computing time is indepen-dent with the size of data array and the length of the MSD

string. If the input planes are partitioned into several sub-areas and one sub-area corresponds to one calculation of the intermediate pattern, the module number can be reduced to one for each step. Although this algorithm has advantages such as highly parallel operation, size free processing, compact system, and no logic gate array, the performance of the proposed system module is restricted by manufacturing errors and alignment of optical ele-ments. Since multiple duplications of BP patterns and the

intermediate patterns multiple input devices

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