October 12th, 2017

P18262: Battery Management System

Team Introduction

Left to right: Ben Stewart, Murali Prasad, Greg Malanga, Steve Titus, Jake Allison, Will McCaffrey

Agenda➢ Team Introductions➢ Phase 1

○ Problem Definition Refresher○ Customer & Engineering Requirements, 2nd Iteration

➢ Phase 2○ Scheduling & Budget○ Functional Decomposition○ Market Analysis & Benchmarking○ Concept Generation & Morphological Chart○ Pugh Analyses○ Concept Selection○ Test Plans & Procedures○ Feasibility Analysis○ Risks Assessment

➢ Phase 3 ○ Scheduling○ Preliminary Test Plan Execution

Phase 1

Problem Definition ReviewDesign a BMS for the EVT’s new electric motorcycle, REV2.

Previous BMS (pictured) inadequate:● Distributed architecture with multiple microcontrollers● Too large● Not fully utilizing BMS chip (LTC6802)● Unreliable connectorization● Limited processing power● Max voltage limitation● Incompatible with updated EVT FW standards.

Customer Requirements (rev. 2)

Engineering Requirements (rev. 2)

Phase 2

Phase 2 Scheduling

Functional Decomposition

Market Analysis

Benchmarking Against BMS 3.3BMS 3.3 is capable of monitoring 24-32 cells in series.

BMS 4.0 will need to work with 100+ cells.

Balance current of BMS 3.3 is 1 A Less current is required for BMS 4.0 with smaller cells.

BMS 3.3 is capable of communicating over CAN.

BMS 4.0 will need to communicate over CAN and master/slave with SPI.

BMS 3.3 is powered externally. BMS 4.0 should be powered by an external 5V source.

BMS 3.3 has temperature sensing with limited success.

BMS 4.0 will need to get temperature measurements.

BMS 3.3 has not achieved full current sensing.

BMS 4.0 will need to sense current and SOC accurately.

Morphological Chart

Pugh Analysis● Pugh Analysis used to determine the best design concept

● Solutions from Morphological chart are compared against each other and previous BMS design (DATUM)

● --, -, 0, +, ++ scale

● Each member completes Pugh analysis independently, results combined together, to avoid bias in selection

● Final results used to make concept selection

Pugh Analysis - Balancing Method

● Charge or discharge cells to equalize voltage levels.● Active methods conserve energy but are expensive and can be very complicated.● Passive methods are less expensive, but a single bad cell will drag down the others.● There are working examples of both methods.

Balancing Method Active (Capacitive)

Active (Inductive)

Passive (Internal)

Passive (Resistor

Array)

Hybrid (Inductivew/ Internal Passive)

BMS 3.3Criteria

Balancing Quality 0 + -- 0 ++

DATUMPrice - -- + + --

Size Constraints - - ++ 0 -

Feasibility - 0 0 + 0

Sum of "+" 0 1 3 2 2

Sum of "-" 3 3 2 0 3

Sum of "0" 1 1 1 2 1

Total -3 -2 1 2 -1

Pugh Analysis - Thermal Management

● Adds copper to the PCB which gives it more surface area to dissipate heat

Pugh Analysis - Temperature Sensing

● Both RTD and Thermistor are viable choices, but legacy and cost edge out the RTD● Thermistor was used in BMS 3.3 but was not properly implemented, this will be taken into

account.

Pugh Analysis - SoC Calculation

● Uses current sensing to calculate how much energy is left

● There are a few implementations, chip or algorithm, TBD from testing

Pugh Analysis - Current Sensing

● Two main technologies: magnetic and ohmic.

● Translate current to voltage, necessary for SoC calculation

● Two viable solutions, TBD by REV1 bench tests.

Pugh Analysis - BMS Chip Selection

● Dedicated chip for measuring voltage and temperature of set number of parallel cells

● Accuracy and speed are critical for optimal balancing / monitoring

● Support and features help set choices apart

Pugh Analysis - Communications and Slave Architecture

Communication Architecture Series (Daisy Chain)Parallel

(Bus)/Shared Harness

Parallel (Bus)/Split Harness PIC18F25K80

Criteria

Speed of Communication - + +

DATUMSingle Point of Failure -- + +

Complexity of Wiring + 0 -

Ease of Bus Enumeration + - -

Sum of "+" 2 2 2

Sum of "-" 3 1 2

Sum of "0" 0 1 0

Total -1 1 0

Pugh Analysis - Microcontroller Selection

Processor SelectionSTM32F303K8T6 STM32F303RE STM32F302R8 STMF334R8 STM32F303ZE STM32F302C8 PIC18F25K80

Criteria

Memory - + - - + +

DATUMManufacturability + - 0 0 -- 0

Cost + 0 0 0 - 0

Communication Channels - + 0 - + +

Sum of "+" 2 2 0 0 2 2

Sum of "-" 2 1 1 2 3 0

Sum of "0" 0 1 4 3 0 2

Total 0 1 -1 -2 -1 2

Pugh Analysis - Emergency Pack Shutoff

● Two solutions: indirect contactor control & pack fusing

● Indirect: BMS tells Gateway/motor controller to cut power

● High current fuse on pack output (already implemented on REV1)

Pugh Analysis - E/P Safety

● PTC resettable fuses in balance circuit

● Conformal coating (internal HW)

● Insulated and keyed connectors

Concept Selection (Five Designs)

Final Concept Selection

Test PlansIn order to perform feasibility and design concept validation, we formulated the following test plans, to be performed early in Phase 3

Test Plans - Current Sensing

● Test shunt and hall-effect on REV1, compare performance metrics.

● Use Arduino for data collection. Use USB oscilloscope for baseline measurements.

● Explore concerns with hall-effect vs. shunt

Test Plans - State of Charge

● Connect to a setup using the 50V pack

● Use a current shunt for current input to chip

● Use Picoscope as a baseline for current measurements

● Have arduino for communication and data collection

Test Plans - BMS Chip Dev. Boards

● Verify communication between LTC6811/LTC6820 and Arduino (microcontroller)

● Prevent/expose potential firmware-related blocking issues early on.

● Verify cell voltage and temperature sensor reading by LTC6811 dev board. Read this data using the Arduino.

Feasibility Analysis - Balancing

● Performed mathematical and cost analysis for feasibility of active vs. passive balancing.

● Sufficient balance current of 100mA and estimated three times less cost makes passive balancing much more feasible.

Feasibility Analysis - Prototyping● Acquire development boards for selected

concept:○ (x2) LTC6811 - BMS IC○ LTC6820 - isoSPI Transceiver○ STM Nucleo - Microcontroller○ TI Battery Fuel Gauge - SoC estimation

● Verify basic functionality and device

compatibility and prevent potential issues.

● To be completed early on in Phase 3.

Phase 3

Phase 3 Scheduling: Gantt Chart

Phase 3 Scheduling: Gantt Chart

BudgetDev. Boards

Chip Worst Case Expected

STM 25 25

SOC 100 0

BMS 150 0

Sub-Total 275 25

Fabrication Costs

Worst Case Expected

PCBs Slave 175 100

Master 150 75

Parts Slave 150 100

Master 50 50

Assembly Cost 525 325

Worst Expected

Total 800 350

Phase 3 Risk Assessment

S15-16 Test Procedure - Current Sense

● Head-start on test procedure for current sense comparison.

● Dual-range Hall-effect stands out to be more effective method: LEM DHAB S/124

S15-16 Test Procedure - Current Sense

Questions? Comments?