P. Baron CEA IRFU/SEDI/LDEF ACTAR Meeting Santiago de Compostela March 11, 2008 1

A review of AFTER+ chipA review of AFTER+ chipIts expected requirementsIts expected requirements

At this time, AFTER+ must fit the specifications of:•ACTAR/GANIL•TPC/GLAD/R3B/FAIR•TPC&ACTIVE TARGET/MSU•TPC/CENBG

2ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+: AFTER+: ArchitectureArchitecture

Main features for AFTER+:Main features for AFTER+:

•72 Analog Channels; Slow Control & test.72 Analog Channels; Slow Control & test.

Main features for the channelMain features for the channel

•Input Current Polarity: positive Input Current Polarity: positive oror negative. negative.

•CSA + PZC + Filter (semi-Gaussian order 2). CSA + PZC + Filter (semi-Gaussian order 2).

[Possibility to bypass the CSA and to enter directly to the filter or SCA input].[Possibility to bypass the CSA and to enter directly to the filter or SCA input].

•511 analog memory cells. 511 analog memory cells.

•Auto Triggering: discriminator + threshold (DAC) + inhibition.Auto Triggering: discriminator + threshold (DAC) + inhibition.

Main features for the readoutMain features for the readout

•Analog OR of the 72 discriminator outputs [1 current output].Analog OR of the 72 discriminator outputs [1 current output].

•Address of the hit channel (through slow control link).Address of the hit channel (through slow control link).

•4 SCA readout modes.4 SCA readout modes.

Serial Interface Mode CKIn Test CSA;CR;SCAin (N°1)

Asic “Spy” Mode

Readout

Mode

AFTER+

511 cells

SCAFILTER

tpeak

CSA

1 channel

x72

in(7

6ou

t)

76 to 1

SCA MANAGERSLOW CONTROLW / R CK

ADC

TEST

Charge range

Power on

Reset

BUFFERΣ 72 discriminator outputs

ADC

DACDiscri

inhibit

external 12-bit ADC[AD9229]

BUFFER

3ACTAR Meeting Santiago de Compostela March 11, 2008

ADC

AFTER+

SCAFILTER

CSA

1 channel

x72

in(7

6ou

t)

76 to 1

SCA MANAGERSLOW CONTROL Write Read TEST

DAC Discriinhibit

BUFFER

AFTER+: AFTER+: Mode of operationMode of operation

Trigger_out

Discri_inDiscri_in

Discri_outDiscri_out

Hit_channelHit_channel

Trigger_outTrigger_out

Write_SCAWrite_SCARead_Address_hit channelRead_Address_hit channel

ResetReset

Read_SCARead_SCA

Data_SCA_outData_SCA_out

Asic management(local or global)

SCA read: READ & CKread

SCA write: Write & CKwrite

Slow control: Din, Dout, CK, CS

Test: DACDAC

ADC control

Trigger control: multiplicity & detection

Reset: hit_channel register Reset

SCA_inSCA_in

Channel iChannel i

Stop Sampling:Stop Sampling: on external or local Triggeron external or local Trigger

SCA writeSCA write address readaddress read SCA readSCA read SCA writeSCA write

4ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: Charge measurementCharge measurement

Charge Range

• 3 charge ranges 120fC [750keV], 1pC [6.25MeV] & 10pC [62.5MeV]

• Adjustable / channel

Charge Measurement

• Output dynamic range: 2V (differential); match the ADC specification [12-bit ADC AD9229]

• I.N.L: < 2%

Peaking Time

• 16 values: 50ns to 1µs• Adjustable / chip

Charge Resolution

• Configuration: Charge Range:120fC; Peaking Time: 200ns; Cin Asic < 30pFasked: < 600 e- rms; possibility: < 850 e- rms.

5ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: SCASCA

SCA memory cells

• 511

Sampling frequency

• 1 MHz to 100 MHz

Time Resolution

• Correlated to the sampling frequency• Jitter: < 2ns

Reading frequency

• 20 MHz to 25 MHz

6ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: triggertrigger

Discriminator solution

• L.E.D• Inhibition: / channel

Trigger output

• Current: Σ 72 discriminators

OR_hit channelOR_hit channel

Iin I=Iin

Hit channel 01

Iin I=Iin

Hit channel 02

Iin I=Iin

Hit channel i

Iin I=Iin

Hit channel 72

72 x72 x IIinin

Slow Control Register(2 bits)

Iin

Trigger time resolution

• The trigger time resolution will be dependent on the input charge, threshold & peaking time value => no spec.

7ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: triggertrigger

Input dynamic range

• 5% of asic input dynamic range• IN.L: < 5 %

Threshold value

• Common DAC: 3 bits + 1 bit of polarity

• Individual DAC: 4 bits

Comment: DACLSB = 0.04% of asic input dynamic range

Minimum threshold value

• Minimum value: ≥ noise

Comment: [Preliminary result] 120fC; 30pF; 200nsminimum # 3 keV ( 0.5fC; 0.4 % of asic input dynamic range)

8ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: ReadoutReadout

Readout frequency

• 20 MHz to 25 MHz

Readout mode: 1 channel means 511 SCA cells

• All channels [Treadout # 2ms]• Hit channels [Treadout # 26µs x nchannel]• Specific channels [Treadout # 26µs x nchannel]

internal Readout buffer

• 2 [controlled by slow control]Comment: for all the 4 readout modes ??

Readout mode: 1 channel means 511, 256 or 128 SCA cells

Comment: for all the 3 readout modes ??

9ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: TestTest

Calibration

• External capacitor; test on 1 channel / 72

“test”

• 3 internal capacitors (1 / charge range); test on 1 channel / 72

Functional

• 1 internal capacitor/channel; test on 1, few or all channels

10ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: Counting rate & PowerCounting rate & Power

Counting Rate

• 1 kHz max. [CENBG]

Power consumption

• < 10 mW / channel

11ACTAR Meeting Santiago de Compostela March 11, 2008

AFTER+ Requirements: AFTER+ Requirements: ConclusionConclusion

• The design of the chip could be started if all the requirements are defined, approved and fixed.

• Don’t forget that this chip is only one element of the global readout electronic.

• Generally, the specifications for the asic and the global electronic architecture are defined in the same time.