Oxidation Control of GaAs/AlGaAs/InGaAs pHEMT

for High Efficiency and Low Voltage Wireless Applications

Can Zheng, Robert Coffie, Dario Buttari, James Champlain, and Umesh Mishra

Electrical and Computer Engineering Department

University of California at Santa Barbara, USA

GaAs on Insulator (GOI)

Advantages of GaAs On Insulator (GOI):

• Elimination of substrate leakage current• Reduced output conductance• Excellent charge control• High efficiency

Source DrainGate

GaAs channel

Insulating buffer

Source DrainGate

GaAs buffer

GaAs channel

Insulating buffer can be obtained by the lateral wet oxidation of Al0.98GaAs layer

Conventional FET GOI FET

150 Å In0.20GaAs Channel

n+ Al 0.22 GaAsAlAs Defect Diffusion Barrier

graded Al xGaAs (x=0.98 -0.22)

Al0.98GaAs Oxidation Layer

(100) GaAs Substrate

LT GaAs

GaAs Smoothing Layer

GaAs Smoothing Layer

Al 0.22 GaAsn+ GaAs Contact Layer

n+ Al 0.22 GaAsAl 0.22 GaAs

Al 0.22 GaAs

Oxide Buffer

pHEMT

Advantages of GaAs On Insulator (GOI):

• Elimination of substrate leakage current• Reduced output conductance• Excellent charge control• High efficiency

Advantages of pHEMT:

• Higher mobility of InGaAs channel• Increased sheet carrier concentration due to the large conduction band discontinuity between InGaAs/AlGaAs

• Superior power and efficiency performance• low noise

GOI pHEMT

MBE Grown GOI pHEMT Structure

DC I-V Characteristics of Fully Oxidized GOI & Control pHEMTs

GOI and Control pHEMTs: 0.7 µm long, 150 µm wide

Vgs = 0.5 to – 2.5V, step = 0.5 VVgs = 0.5 to – 2.5V, step = 0.5 V

• IDSS (GOI) ~ 436 mA/mm, IDSS (Control) ~ 586 mA/mm.

• Decreased current level in fully oxidized GOI sample is due to back depletion from high defect density oxide-semiconductor interface and charge compensation.

0

100

200

300

400

500

600

700

800

0 1 2 3 4 5

I DS (m

A/m

m)

VDS

(V)

0

100

200

300

400

500

600

700

800

0 1 2 3 4 5

I DS (m

A/m

m)

VDS

(V)

Control GOI

The Effect of Traps: Back Depletion

• 1D Poisson simulation indicates more charge loss with increased oxide-semiconductor interface defect density, causing up to 20% charge loss for GOI MESFETs grown on LT AlGaAs or GaAs buffer.

• MESFETs grown on LT GaAs buffer shows charge loss up to 30 ~ 40% after the oxidation.

•Additional charge loss can be contributed to charge compensation during the oxidation process.

ntrap

ntrap increases

wdep,owdep,o +∆wdep

Oxide OxideLT GaAs LT GaAs

ntrap increases

wdep,owdep,o +∆wdep

Oxide OxideLT GaAs LT GaAs

ntrap increases

wdep,owdep,o +∆wdep

Oxide OxideLT GaAs LT GaAs

0.75

0.8

0.85

0.9

0.95

1

0 5 1012 1 1013 1.5 1013 2 1013

LT GaAs BufferLT AlGaAs Buffer

Nor

mal

ized

Cha

nnel

Cha

rge

(nsh

/ n 0)

Oxide Top Interface Trap Density (cm-2)

Minimize Charge Loss by Growing LT AlGaAs Buffer

Charge Loss of fully oxidized GOI MESFET

• GOI MESFET directly grown on GaAs substrate: 80%.

• GOI MESFET on LT Grown GaAs buffer ( Tg = 270 ºC): 35 ~ 40%.

• GOI MESFET on LT Al0.3Ga0.7As buffer (Tg = 270 ~ 400 ºC): 6 ~ 17 %

The growth and anneal temperature of the LT

Al0.3Ga0.7As buffer is critical to obtain the

minimized charge loss.

0

5

10

15

20

260 280 300 320 340 360 380 400 420

LT AlGaAs Growth Temperature (°C)

Cha

rge

Loss

( %

)

gm Characteristics ofFully Oxidized GOI & Control pHEMTs

• gm_(GOI) ~ 366 mS/mm, gm (Control) ~ 280 mS /mm

• GOI sample has sharper turn-on and higher gm near pinch-off

GOI and Control pHEMTs: gate 0.7 µm long, 150 µm wide, Vds = 2.5 V

0

100

200

300

400

500

600

700

800

0

50

100

150

200

250

300

350

400

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5

Vgs(volts)

I d(m

A/m

m)

gm(m

S/mm

)

Control

0

100

200

300

400

500

600

700

800

0

50

100

150

200

250

300

350

400

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5

Vgs(volts)

I d(m

A/m

m)

gm(m

S/mm

)

GOI

• gm peaking was observed for GOI pHEMT due to impact ionization

• Control sample showed constant gm curves s

m gv vg Cl d l

ε= = i

G

gm peaking in Fully Oxidized GOI pHEMT

AlGaAs

Al2O3SI GaAs Substrate

n+ GaAs n+ GaAs

• Traps are generated during the oxidation process at the oxide semiconductor interface and in the adjacent layers. • Impact ionization of the traps underneath the gate by hot electrons can take place at substantially lower drain bias compared to the electron-hole pair generation by band to band ionization.• Electrons removed from the deep levels shift the threshold voltage to the negative direction, therefore causing the increase in current.

Gain peaking is attributed to an increase in drain current induced by trap-related threshold voltage shift.

InGaAsAlGaAs

DS

-0.08

-0.07

-0.06

-0.05

-0.04

-0.03

-0.02

0

100

200

300

400

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5

I g (mA

/mm

) gm (m

S/mm

)

Vgs

(V)

Interface traps

Threshold Voltage Shift in GOI pHEMT

0

20

40

60

80

-1.5 -1 -0.5 0 0.5

ID (mA/mm)_1ID (mA/mm)_2

I D (m

A/m

m)

VGS

(V)

VDS

= 0.2 V

• The threshold voltage of a GOI pHEMT was measured in the dark at a low VDS of 0.2V.

• The 80mV threshold voltage shift toward the positive voltage direction was observed after up to 5V VDSapplied to the GOI pHEMT.

• The threshold voltage shift can be contributed to the negatively charged trap states underneath the gate.

Threshold Voltage of GOI pHEMTbefore and after high bias applied.

Transconductance Characteristics in SOI MOSFET’s

Front gate and back-gate characteristics in NMOS SOI transistors for both high-does SIMOX wafers or BSOI wafers

•The rapid kink phenomenon has been contributed to the presence of energetically –localized trap states at SOI/BOX interface.

Takeo Ushiki, Koji Kotani, et al. IEEE Transactions on Electron Devices, Vol. 47, 2000, P360

1. Controlled Wet Oxidation of AlGaAs

4. Gate recess etch and gate metallization

Partially Oxidized pHEMT Process Flow

3. Mesa Isolation and S/D Ohmic Contact

2. Anneal (600°C/3min)

pHEMT

oxidation depth

SiNx Cap

Oxide AlGaAs

G

pHEMT

oxidation depth

SiNx Cap

Oxide AlGaAs

S D

pHEMT

oxidation depth

Oxide AlGaAs

S D

pHEMT

oxidation depth

Oxide AlGaAs

Partially Oxidized pHEMTs

gate

source drain

S DGs dg

s dg

oxidation trench

Fully oxidized devices• Truly insulating buffer• charge loss• gm peaking

Partially oxidized devices• insulating buffer underneath the source• reduced charge loss• no gm peaking

Subthreshold Leakage Current

10-2

10-1

100

101

102

103

-3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5

I DS

(mA

/mm

)

VGS

(V)

Oxide

source draingate

channel

A

Oxide

source draingate

channel

B

A

B

Partially oxidized pHEMT can effectively block the subthreshold leakage current compared with the un-oxidized control sample, especially when the high field drain side of the gate edge is blocked by the oxide.

Control

Oxidation Distance from Source Edge

source draingate

channel

0.5

0.6

0.7

0.8

0.9

1

-3 -2 -1 0 1 2 3 4

S G D

Oxidation Distance from Source Edge (µm)

I DSS

_ox

/ ID

SS_u

n (%

)

IDSS_unoxidized = 667 mA/mm

Partially Oxidized & Control pHEMTs DC Characteristics

250

300

350

400

450

-3 -2 -1 0 1 2 3 4

Gm

_max

(mS/

mm

)

Oxidation Distance from Source Edge (µm)

S G D

Gm_max_unoxidized = 341 mS/mm

GOI and Control pHEMTs: gate 0.7 µm long, 150 µm wide

• Hall measurement shows charge density of 3.54 x 1012/cm2

and mobility of 6467cm2/(v.sec)

• Oxidation conditions : 400ºC, 30 minutes, oxidation depth 5 µm

• Charge loss up to 30% for fully oxidized sample was observed

• High gm peaking was observed for samples with the oxide extending beyond the drain edge of the gate

-20

0

20

40

60

80

100

-3 -2 -1 0 1 2 3 4

Dra

in C

urre

nt D

ispe

rsio

n (%

)

Oxidation Depth (µµµµm)

S G D

Unoxidized

Oxidized

Unoxidized

Oxidized

-20

0

20

40

60

80

100

-3 -2 -1 0 1 2 3 4

Dra

in C

urre

nt D

ispe

rsio

n (%

)

Oxidation Depth (µµµµm)

S G D

LT GaAs buffer (001235_2) LT AlGaAs buffer (010882_2)

Dispersion in Partially Oxidized pHEMTs

Serious dispersion was observed for the pHEMTs with oxide extending beyond the gate region. The pHEMTs with an LT AlGaAs buffer showed lower dispersion compared to the pHEMTs with an LT GaAs buffer when oxide is around the source region.

Submicron GOI & Control pHEMTs RF Characteristics

GOI and Control pHEMTs: gate 0.7 µm long, 150 µm wide

• ATN loadpull measurement: 8 GHz, Class AB bias, 3.5 V VDS

• Lower gain is observed for the partially oxidized sample due to the reduction in channel charge after the oxidation

• Highest power added efficiency was observed for samples with oxide front terminated around source edge due to decreased subthreshold leakage current

• RF measurement is limited by the available matching states of our Loadpull system

Gai

n (d

B)

Unoxidized

Partially-oxidized

14

15

16

17

18

-3 -2 -1 0 1 2 3 4

S G D

Oxidation Distance from Source Edge (µm)

PAE

( %

)

30

35

40

45

50

55

60

-3 -2 -1 0 1 2 3 4

Unoxidized

Partially-oxidized

Oxidation Distance from Source Edge (µm)

S G D

Conclusions

• Oxidized Al0.98Ga0.02As offers an insulating buffer for MESFETs and pHEMTs, increasing the efficiency of the device.

• Partially oxidized devices retain the benefits of the oxide buffer, while not suffering as greatly from the charge loss problem.

• Partially oxidized pHEMTs with oxidation stopped around the source region showed improved power added efficiency at low power supply.

• Transconductance peaking due to impact ionization of the traps underneath the gate was observed when oxide extended beyond the gate.

• Serious dispersion was observed for the pHEMTs with oxide extending beyond the gate region. The pHEMTs with an LT AlGaAs buffer showed lower dispersion compared to the pHEMTs with an LT GaAs buffer when oxide is around the source region.