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Chapter 9Memory Management

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Outline Background

Swapping

Contiguous Allocation

Paging

Segmentation

Segmentation with Paging

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Background

Program must be brought into memory and placed within a process for it to be run.

Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.

User programs go through several steps before being run.

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Binding of Instructions and Data to Memory

Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes.Load time: Must generate relocatable code if memory location is not known at compile time.Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers).

Address binding of instructions and data to memory addresses canhappen at three different stages.

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Multistep Processing of a User Program

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Logical vs. Physical Address Space

The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Logical address – generated by the CPU; also referred

to as virtual address. Physical address – address seen by the memory unit.

Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme.

compiler: symbol --> relocatable addressloader: relocatable address -> absolute address

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Memory-Management Unit (MMU)

Hardware device that maps virtual to physical address.

In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.

The user program deals with logical addresses; it never sees the real physical addresses.

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Dynamic relocation using a relocation register

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Dynamic Loading

Routine is not loaded until it is calledBetter memory-space utilization; unused routine is never loaded.Useful when large amounts of code are needed to handle infrequently occurring cases.No special support from the operating system is required implemented through program design.

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Dynamic LinkingLinking postponed until execution time.Small piece of code, stub, used to locate the appropriate memory-resident library routine.Stub replaces itself with the address of the routine, and executes the routine.

First time a stub is performed1. Locate or load the routine2. Replace itself with address of the routine

Operating system needed to check if routine is in processes’ memory address.Dynamic linking is particularly useful for libraries.

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Overlays

Keep in memory only those instructions and data that are needed at any given time.

Needed when process is larger than amount of memory allocated to it.

Implemented by user, no special support needed from operating system, programming design of overlay structure is complex

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Overlays for a Two-Pass Assembler

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SwappingA process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution.Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped.Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

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Schematic View of Swapping

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Contiguous Memory Allocationrelocation register + limit registerMMU:

Using relocation register allow OS to dynamically change its size (for transient OS codes, such as drivers seldom used).

memory

relocationregister

CPUlogical

address

physical

address <

limitregister

yes

no

trap; address error

OS relocation

register

limitregister

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Multiple-Partition Allocationmultiple contiguous fixed partition allocation The number of partitions determines the

degree of multiprogramming.

multiple contiguous variable partition allocation hole: one large block of available memory. dynamic storage-allocation problem: search

a hole big enough for a request first-fit best-fit worst-fit

By simulation, FF and BF are better than WF. FF is faster than BF.

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An Scheduling Example

OS

2160 K

0

400K

2560 K

process memory time

P1 600K 10

P2 1000K 5

P3 300K 20

P4 700K 8

P5 500K 15

job queue

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Memory Allocation and Long-term Scheduling (FCFS)

OS

P1

P2

P3

0400

1000

200023002560

OS

P1

P4

P3

0400

1000

200023002560

OS

P5

P4

P3

0400

1000

200023002560

1700

900

1700

P2 terminates

allocate P4

P1 terminates

allocate P5

external fragmentation

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Fragmentationinternal fragmentation: memory is internal to a partition, but is not being used.external fragmentation: free memory is enough but not contiguous.Compaction: shuffle the memory contents to make all free memory together a solution to external fragmentation problem possible only if relocation is dynamic and is done

at execution time. Selecting an optimal compaction is difficult. Swapping can also be combined with compaction

compact if necessary, and then roll in a process (into a different location)

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Compaction

OS

P4

P3

0400

900

1900

2560

OS

P5

P4

P3

0400

1000

200023002560

1600

900

1700Compact

P5

660K260K

300K

100K

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Comparison of some Different Ways to Compact Memory

OS

P1

P4

P3

0300

600

150019002100

1200

P2500

1000

300K

200K

400K

OS

P1

P4P3

0300

600

150019002100

1200

P2500

1000

900K

OS

P1

P4

P3

0300

600

150019002100

1200

P2500

1000

900K

OS

P1

P4

P3

0300

600

150019002100

1200

P2500

1000 900K

original allocation moved 600K moved 400K moved 200K

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PagingLogical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available.Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).Divide logical memory into blocks of same size called pages.Keep track of all free frames.To run a program of size n pages, need to find n free frames and load program.Set up a page table to translate logical to physical addresses. Internal fragmentation.

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Address Translation Scheme

Address generated by CPU is divided into: Page number (p) – used as an index into a page

table which contains base address of each page in physical memory.

Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

logical address:

page number (p) + page offset (d):

No external fragmentation shared pages

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Paging model of logical and physical memory

page 0

page 1

page 2

page 3

logical memory

1437

0123

page 0

page 2

page 3

page 1

01

23

4

5

6

7

page table frame number

Example: page size = 1 K(2, 13) ----------------> (3*1K + 13)

----------------> 0110000000000 + 0000001101

----------------> 0110000001101

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physical

memory

CPU

logical

addressphysicaladdress

f d p d

f

p

page table

Paging hardware for address translation

(dynamic relocation)

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Paging Example

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Paging Example

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Free Frames

Before allocation After allocation

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DisscussionsNo external fragmentationinternal fragmentation: 1/2 page in average

suggesting a smaller page size in the past

Page sizes have grown over time (2~4 Kbyte today)

memory, process, data sets have become larger better I/O performance page table is smaller

frame table: an entry for each physical frame free or allocated (if allocated) to which page of which process

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Implementation of Page Table

Page table is kept in main memory.Page-table base register (PTBR) points to the page table.Page-table length register (PRLR) indicates size of the page table.In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

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Hardware support dedicated registers (fast but small size) main memory + page-table base regist

er (PTBR)Problem: accessing a byte needs two mem

ory accesses (too slow)!Solution: associative registers (translation

look-aside buffers - LTBs) hit ratio, 16-512 registers have a hit ratio abou

t 80-98%

Structure of the Page Table

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Paging Hardware with TLB

physical

memory

CPU

logical

address

physical

address

f d

p d

f

p

page table

page frameno. no.

TLB

TLB miss

fp

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Effective Access TimeAssociative Lookup = time unitAssume memory cycle time is 1 microsecondHit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers.Hit ratio = Effective Access Time (EAT)

EAT = (1 + ) + (2 + )(1 – )= 2 + –

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Memory ProtectionMemory protection implemented by associating protection bit with each frame.

Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated

page is in the process’ logical address space, and is thus a legal page.

“invalid” indicates that the page is not in the process’ logical address space.

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An example

page 0page 1page 2

page 3

logical memory

page 3

page 5page 4

01234567

page table

page 4

page 5

page 0

page 2

page 1

89

n

2347

01234567

8900

vvvvvvii

frame No.

00000

1046812287 12290

valid but illegal

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Page Table Structure

Hierarchical Paging

Hashed Page Tables

Inverted Page Tables

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Hierarchical Page Tables

Break up the logical address space into multiple page tables.

A simple technique is a two-level page table.

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Multilevel PagingA very large table requires a very large contiguous memory.Two-level paging: the page table itself is also paged.

SPARC: 2-level, Motorola 68030: 3-level

page number page offset

p1 p2 d logical address

outer-page table

...

p1

p2 d

page of page table desired page

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.

Two-Level Paging

outer-page table

page table in memory

page 0

page 123

page 1516

123

..

1708...

929

900

...

page 516

...

...

page 708

page 900

...

...

page 929

...

...

process in memory

Example: (1K page size)

(1, 2, 121)

-> (708*1K +121)

0

1

2

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Address-Translation Scheme

Address-translation scheme for a two-level 32-bit paging architecture

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Hashed Page Tables

Common in address spaces > 32 bits.

The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.

Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

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Hashed Page Table

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Inverted Page TableEach process has a page table, which may consist of millions entries. This may consumes large amounts of physical memory.Solution: inverted page table one entry for each frame, storing the

virtual address of the page stored in it.(process-id, page number)

A virtual address: (process-id, page number, offset)

: only one table is used: table searching time is larger

Solution: hash + associative register (cache)

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Inverted Page Table

physical

memory

CPU

logical

address

physical

address

i d

pid p

i

inverted page table

pid p d

search

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Shared PagesAnother advantage of paging is the possibility of sharing common code, which must be reentrant . reentrant code (pure code): It never change during execution.Particularly important in a time-sharing environment

e.g., 40 users run an editor at the same time

Only one copy of the shared code needs to be kept in physical memory.Two (several) virtual addresses are mapped to one physical address.

system using inverted page table is difficult to implement shared pages (memory).

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Shared Pages

ed 1

ed 2

ed 3

data 1

3461

0123

page table

0 1

2 3

4

5

6

7 8

data 1

process P1for P1

ed 1

ed 2

ed 3

data 2

3462

0123

page table

process P2for P2

ed 1

ed 2

ed 3

data 3

3467

0123

page tableprocess P3for P3

data 3

ed 1

ed 2

ed 3data 2

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SegmentationMemory-management scheme that supports user view of memory. A program is a collection of segments. A segment is a logical unit such as:

main program,procedure, function,method,object,local variables, global variables,common block,stack,symbol table, arrays

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User’s View of a Program

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Logical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space

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Segmentation Architecture (1)

Logical address consists of a two tuple:<segment-number, offset>,

Segment table – maps two-dimensional physical addresses; each table entry has: base – contains the starting physical address

where the segments reside in memory. limit – specifies the length of the segment.

Segment-table base register (STBR) points to the segment table’s location in memory.Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR.

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Segmentation Architecture (2)

Relocation. dynamic by segment table

Sharing. shared segments same segment number

Allocation. first fit/best fit external fragmentation

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Segmentation Architecture (3)Protection. With each entry in segment table associate: validation bit = 0 illegal segment read/write/execute privileges

Protection bits associated with segments; code sharing occurs at segment level.Since segments vary in length, memory allocation is a dynamic storage-allocation problem.A segmentation example is shown in the following diagram

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Segmentation Hardware

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Example of Segmentation

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Protection and SharingEasy association of protection A segment represents a semantic portion and

thus all entries should be used in the same way. Instruction section: read-only or execute-only put array in a segment: MMU automatically

check each array index Many errors can be checked by hardware

Easy to share a segment Problem: code segment refer to itself Solution

all processes use the same segment number indirect reference (offset)

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Sharing of Segments

editor data 1

logical memory

segment 0segment 1

limit base0 25286 43062

1 4425 68348

segment table

P1

editor data 2

logical memory

segment 0segment 1

P2

limit base0 25286 43062

1 8850 90003

segment table

43062

editor

68348 72773

data 1

data 2 90003 98553

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FragmentationAllocation: best-fit or first-fit: external fragmentationHow serious a problem is external fragmentation? Would long-term scheduling with compaction help?The answer mainly depends on the average segment size. vary large: variable-seized partition. very small (a byte):

No external fragmentation. But, every byte needs a base register for relocation, doubling memory use!

Generally, small average segment size small external fragmentation.

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Segmentation with Paging

Both paging and segmentation have their advantages and disadvantages.It is possible to combine these two schemes to improve on each. MULTICS system:

page the segments + page the segment table OS/2 32-bit version:

page the segments + page the page tables (two-level paging)

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Multics

Page the segments: 1. No external fragmentation

2. allocation is trivial and fast: 1. internal fragmentation

2. slower

Page the segment table: page table do not need a large contiguous memory

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Paged segmentation on GE645 (MULTICS)

+

memory

logical address

physical

address

page table for segment s

segment table

yes

no

s d

segment page-tablelength base

+ p d’

d

f d’f

STBR

segment table base register

16 bits

18 bits

10 bits6 bits

1K

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Address Translation in Multics

s1 s2 d1 d2

logical address

page table

for segment

table (256)

...

s1

s2

d1 page of segment table

(1K) d2

page table

for segment

(64) page of segment

(1K)

segment

numberoffset

8 10 6 10

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Segmentation with Paging – Intel 386

As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

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Intel 30386 Address Translation