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© MOTOROLA, INC. 1995 REV 2
SEMICONDUCTORTECHNICAL DATA
MOTOROLA
Table 1. H4CPlus Series Arrays
Array Name Available GatesDie Size
(mils/side)Die Pads I/O Sites
PackagePins
H4CP011 11,036 179 120 120 80-100H4CP028 28,400 239 176 160 100-169H4CP048 48,100 287 216 208 100-225H4CP075 74,520 337 256 256 128-225H4CP109 109,368 391 304 312 160-313H4CP146 145,544 438 344 360 160-313H4CP178 178,000 476 376 400 160-313
Product Data SheetH4CPlus™ SERIES CMOS ARRAYS
The new H4CPlus Series arrays feature new 3.3V, 5V and mixed-voltagecapability, high-speed interfaces, and analog PLLs for chip-to-chip clock skewmanagement. The gate length has been reduced to 0.65 µm Leff to provideimproved 5V performance and competitive performance at 3.3V.
The low- and mixed-voltage capability lets designers customize the H4CPlusarrays to fit power and performance needs. All H4CPlus arrays have dual VDD railswith custom power/ground bus tying to power input and output buffers for full 3.3V,full 5V or a mix of system voltage levels. Additionally, the core of the arrays may bepowered by either 3.3V or 5V.
New, high-speed CMTL, GTL, and PECL macros offer enhanced chip-to-chipcommunication. CMTL (Current Mode Transceiver Logic™), a Motorola innovationwith optional active termination, offers a high speed communication interface at200+ MHz and can interface to differential and single-ended PECL (Pseudo EmitterCoupled Logic). Differential and single-ended GTL (industry standard GunningTransceiver Logic™) offers high performance data bus and point to pointcommunications up to 250 MHz. Differential and single-ended PECL inputs offerECL compatible clock rates up to 400 MHz worst case. Also, new PCI (PeripheralComponent Interface) compliant I/O buffers are available in 5V and 3.3V versions.
(cont’d. page 2)
H4CPlus Series Features• 0.65 µm Leff, channelless, triple-layer metal gate arrays• Typical gate delay of 280 ps at 5V and 420 ps at 3.3V (NAN2, FO=2)• Low power, 1µW/gate/MHz (3.3V), 3µW/gate/MHz (5V)• 3.3V, 5V or mixed system and core voltage levels• Custom power bus tying and ground bus isolation for special power needs• Configurable I/O cell supports 2 to 24 mA, up to 48mA using dual I/O cells• PCI compliant 5V and 3.3V I/O buffers with 5V I/O tolerant, 3V I/O input and
output macros, and 5V I/O fail-safe macros• Differential and single-ended GTL I/O and PECL input macros• Analog PLL with 70 to 250 MHz worst case VCO frequency• Pseudo-Random and comparator BIST macros• Single-, dual-, and quad-port metal SRAMs• Single- and dual-port diffused SRAMs• Powerful design environment using Mentor Graphics, Cadence Design
Systems, Synopsys, Quad Design Technology, and Motorola design tools• OMPAC ball-grid array, MicroCool, and PQFP packaging
Order this Data Sheet by H4CP/D
H4CPlusSERIES
HIGH PERFORMANCETRIPLE LAYER METAL
SUB-MICRONCMOS ARRAYS
(insert photo ofH4CPlus SERIES
Packages)
QFPMicroCoolOMPAC
TYPICAL H4CPlus SERIES PACKAGES
MOTOROLA H4CPlus_Series
2
(cont’d from page 1)Each array can have two APLL (Analog Phase Lock Loop)
macros, placed in the adjacent corners of the die, havingseparate APLL power pins for obtaining low noise and phasejitter. External components are not required since the VCOfilter is contained in the APLL. The APLL can be used inapplications such as clock synthesis with a worst case VCOfrequency of 70 to 250 MHz (30 to 415 MHz typical).
Other design features include Fail-Safe macros, metal anddiffused RAMs, ESSD/LSSD scan macros, JTAG boundaryscan, and Built-In Self Test macros.
HIGH-PERFORMANCE TECHNOLOGYThe H4CPlus Series uses a self-aligned twin tub process
in which n-type and p-type well implants are driven togetherto form deep, balanced wells to improve short n-channel tran-sistor performance, see Figure 1. A lightly doped drain (LDD)diffusion is used to reduce hot carrier injection effects causedby a high electric field in the short channel transistors. A high-ly-reliable multi-layer metal structure is achieved by a pla-narization technique using tapered contacts and vias.
The combination of a small feature size and a thin gate ox-ide coating provides both high gate density and low powerdissipation. The typical power dissipation for internal gates isonly 1µW/gate/MHz at 3.3V and 3µW/gate/MHz at 5.0V witha load of 0.05 pF (fanout = 1).
Figure 1. H4CPlus Series CMOS Device Cross-Section
M3
M2
M1
PTO
PTO
BPSG
p-Welln-Well
p-Fieldp-MOSFETn-MOSFET
p-Substrate
PolysiliconGate
Gate Oxide
PSGPassivation
(Plasma Teos Oxide)
(Plasma Teos Oxide)
Field Oxide
Plasma Nitride
The H4CPlus Primary CellThe primary cell consists of four pairs of n- and p-type
transistors. The transistors are the same size to optimizeboth gate density and routability. The primary cell is used toconfigure all H4CPlus Series macrocells. Figure 2 shows half
of a primary cell (two p-type and two n-type transistors) con-figured in a 2-input NAND gate (NAN2). The typical gatedelay for a 2-input NAND with a fanout of 2 is 280 ps at 5Vand 420 ps at 3.3V.
Figure 2. 2-Input NAND Gate Implemented Within Half of a Primary Cell
P-ChannelTransistors
N-ChannelTransistors
A
B
A
X
B
A
B
VDD VSS
PolysiliconGate
N-Well P-Well
X
A
B
VDD
VSS
PRODUCT DESCRIPTION
H4CPlus_Series MOTOROLA
3
Triple-Layer Metal RoutingA triple-layer metal (TLM) structure provides superior
routing access to configure and connect macrocells as wellas distribute power and ground, see Figure 3.
Figure 3. Triple-Layer Metallization (SEM Photo)
One important benefit of TLM routing is improvedroutability for higher gate utilization. TLM also providesimproved clock distribution by moving the clock signals to thetop metal layer where the capacitance per unit length is 30%less than the lower metal layers due to a thicker dielectriclayer. In addition, TLM reduces interconnect delays typicallyby 10% with shorter interconnect lengths and improvespower distribution.
• Gate Ensemble Place and RouteThe design of the routing layers is accomplished with
Cadence’s Gate Ensemble place and route system. Some ofGate Ensemble's capabilities include soft/firm grouping ofmacros, clock-tree synthesis, incremental layout changes,and highly accurate distributed RC calculations. In addition,the power-bus router automatically uses single-, double-, orquadruple-width power tracks to optimize performance whileminimizing spent routing channels where needed.
• PrediX FloorplanningPrediX is Motorola’s powerful floorplanning and routabil-
ity analysis tool that enables designers to predict andimprove routing congestion especially in complex circuits.PrediX is easy to use and interfaces with Gate Ensemble toassure the desired results in layout and timing.
PRODUCT DESCRIPTION (continued)
THE H4CPlus SERIES LIBRARYThe H4CPlus Series library is an optimized set of macros
containing a complete suite of I/O functions, combinatorialand sequential functions. Many basic logic functions come inseveral versions including standard/high-drive capacity andscan/non-scan to provide the widest choice of functions.
I/O Macrocell LibraryThe H4CPlus Series I/O cells, see Figure 4, are config-
urable into inputs, outputs, bidirectionals, oscillators, JTAG I/O, CMTL, GTL, and PECL interfaces. The standard CMOS,TTL, slew control, 3-state, open-drain and Schmitt-trigger I/Ofunctions are available as well. The I/O cell also providespull-up and pull-down resistors, active terminations forCMTL, voltage translation between 3.3V and 5V levels, andpower and ground connections.
• 3.3V, 5V, and Mixed-Voltage I/OThe I/O cell can support any combination of 3.3V and 5V
in system and core voltage requirements. This is accom-plished with a voltage translator to translate between logiclevels based on the system and core voltages, see Figure 4.
Low-voltage interfaces are important in systems requiringlow-power since most of the power dissipated in ICs occursin the outputs. However, performance is usually sacrificed forlower power. The H4CPlus Series I/O offers all combinationsof system and core voltage levels to meet power and perfor-mance goals. For example, the ONL8 is a 12mA output for a3.3V/3.3V (3.3V Input/Output with 3.3V core. Its power dissi-pation is about 56% less than the 5V/5V ON8 output, but it is41% slower at 100pF, see Figure 5. The ONLX8 (3.3V/5V)and the ONX8 (5V/3.3V) is moderately slower than the ON8.
Figure 4. H4CPlus Series I/O Cell
• Selectable Output DriveUp to 24 mA is available from a single I/O cell, two cells
may be paralleled for up to 48 mA drive from a single outputpin. (All JTAG outputs and bidirectionals are not parallelable,but have higher current capacity versions available.) Unusedoutput drivers may also be used to drive highly loaded inter-nal signals such as clock networks.
• Slew Rate ControlSlew rate control outputs are available to reduce system
SSO noise as well as over-shoot and undershoot of outputsignals caused by fast rise and fall times. All 4 and 8 mA out-put buffers have a moderate (10%) and slow (30%) slewcontrol version.
JTAGLogic
T InPad
Pad
I/O Cell
I/O Cell
Pull Resistors
Active TerminationsESD Diodes
Configurable Output
Configurable Input
Vol
t. T
rans
.Out
I/O Cell
Arr
ay C
ore
SPECIAL DESIGN FEATURES
MOTOROLA H4CPlus_Series
4
• PCI I/O BuffersPCI (Peripheral Component Interface) is emerging as a
high-performance local bus architecture. It is a highly flexi-ble, processor independent architecture that has applicationsin low- to high-end desktop, server and low-power, mobilesystems. Motorola offers PCI compliant 3.3V and 5V I/Obuffers to allow connection of H4CPlus arrays to any PCIlocal bus “speedway”.
• GTL InterfaceGTL is able to drive system backplanes while still occu-
pying only a single I/O site for 50Ω and two sites for 25Ω.This licensed implementation provides a high performancebus driver for system I/O data rates exceeding 200 Mbits/secdepending on the bus fanout loading. Differential GTL is alsoavailable for providing the clock signals to Fast StaticBiCMOS RAMs and for point to point applications providingworst case clock rates of greater than 200 MHz.
• PECL InterfaceStandard positive ECL voltage levels can be received
with differential and single-ended PECL receiver macros atworst case clock rates up to 400 MHz. The H4CPlus arrayscan also drive Standard PECL inputs by using CMTL or GTLoutput macros as described in application note AN1521.
Figure 6. Typical CMTL Applications
m-bits
n-Bit Shift Register
FIFO
ECLinPS™ Logic H4CPlus Series with CMTL I/O
High-SpeedData
400 MHzClock
400 Mb/secDataOut
H4CPlus Series with CMTL I/O PECL I/O RAMor RAMDAC
GraphicsEngine
or
CPU
or
SignalProcessor
Data Out
Address
Enable
n-bits
n-BITS
High-SpeedOutput
ASIC #1 ASIC #2
High-SpeedOutput
High-SpeedInput
High-SpeedInput
Self-TerminatingDifferential
Data In
Control
m-bits
FIFOControl
n-BITS
Data Out
Enable
Data In
Data Out
Enable
Data In
Self-TerminatingSingle-Ended
Vref
Vref
Figure 5. Performance Comparison of 12mA Output Buffers
• Fail-Safe I/O Macros5 Volt Fail-Safe I/O macros are provided for bus applica-
tions that will not load the active bus when power isremoved. These macros can be designed in applicationsrequiring "hot plug" operation where a card is inserted whilethe system is running.
• Extended Voltage Range I/O MacrosExtended Voltage Range I/O macros, or 5V tolerant 3.3V
I/Os provide a flexible design solution for designers imple-menting 3 volt systems in a 5 volt world. These macros des-ignated by an "E" in their name require only a 3 volt supply,but can tolerate the reception of a 5 volt signal on the pad.
• CMTL InterfaceMotorola’s new Current Mode Transceiver Logic (CMTL)
buffers provide a low-power alternative to high-speed inter-faces. On-chip active termination allows for the lowest possi-ble power dissipation while enhancing the performance.They may also be configured with external 50Ω terminationsin bidirectional or PECL applications.
The drivers have been engineered to operate withoutexternal reference or termination voltages and over a widerange of common-mode voltages. The flexibility of thisdesign allows simple, direct interfaces to ECLinPS or otherECL-level chips operating in a PECL environment with stan-dard terminations.
Applications for CMTL range from video to telecommuni-cations to tightly-coupled processor/cache interfaces. I/Opair delay is less than 2ns worst-case. Systems are nolonger limited by slow buffers for critical chip-to-chip paths.
ONL8 3.3V/3.3V Core
ONX8 5V/3.3V Core
ONLX8 3.3V/5V Core
ON8 5V/5V Core
System
t PLH
4
3
2
1
00 20 40
Load (pF)
60 80 100
SPECIAL DESIGN FEATURES (continued)
H4CPlus_Series MOTOROLA
5
• OscillatorsThree different oscillator I/O macros are available on the
H4CPlus Series arrays: non-inverting buffer, clock buffer,and Schmitt trigger versions. These macros can be config-ured for ceramic resonators from 32 KHz to above 60 MHzwith quartz crystals.
• JTAG Boundary Scan I/OThe H4CPlus Series I/O cell has JTAG logic built-in to
minimize the impact on performance and gate overhead.Also, the JTAG control and scan data signals between I/Osare connected automatically by design.
Internal Macrocell LibraryThe mature H4C Series library has been optimized to a set
of the most popular and efficient functions, including severalnew scan macros, for the H4CPlus library. All H4CPlus mac-rocells have been characterized at typical operating condi-tions for 3.3V and 5.0V operation for the highest modellingaccuracy. A summary of available macrocell types is shown inTable 2.
Table 2. Summary of Macrocells
Library Functions Macros
AND 7
NAND 11
OR 7
NOR 11
EXOR, EXNOR 5
A/N, A/O, O/N, O/A 22
Inverting Buffer 9
Non-Inverting Buffer 8
3-State Buffer 8
D Flip-Flop 23
Latch 11
Multiplexer 13
Decoder 4
Arithmetic 9
Misc. 6
Table 3. Summary of Special Functions
Special Function Macros
Metallized SRAMs 24
BIST 5
Analog PLL 10
Internal JTAG 6
Figure 7. Performance of NAN2 Macros
Several types of macrocells come in high-drive, balancedslew-rate, or complementary output versions. High-drive ver-sions provide improved performance on nets with highfanouts. Balanced slew rate versions of macrocells providemore symmetrical rise and fall slew rates with slightly betterperformance than standard macros. For example, Figure 7shows the NAN2H at 3.3V and 5V to have better performancethan the balanced and standard-drive NAN2.
Metallized SRAMsThe metal SRAMs are a family of asynchronous single, du-
al, and quad-port blocks up to 2304 bits. These RAMs aregate array based (not diffused), and are an excellent choicefor small memory block applications such as “scratch-pads”or FIFOs.
Table 4. Sizes of Metallized SRAMs
H4CPlus Series Metallized SRAM Sizes
Single-Port Dual-Port Quad-Port
8x8 8x9 16x18
8x18 8x18 16x36
16x8 8x36 32x18
16x18 8x72 32x36
16x36 16x9
32x8 16x18
32x18 16x36
32x36 16x72
64x18 32x9
64x36 32x18
32x36
32x72
8765432100.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NAN2 (3.3V)
NAN2H (3.3V)NAN2B (3.3V)
NAN2 (5V)
NAN2H (5V)NAN2B (5V)
Fanout
Ave
. Pro
p. D
elay
(n
s)
SPECIAL DESIGN FEATURES (continued)
MOTOROLA H4CPlus_Series
6
• Clock DistributionMotorola offers clock tree synthesis during layout to build
balanced clock distribution networks or clock trees. Clocktrees are load-balanced networks that synchronizes clocksignals for all on-chip sequential elements. Clock trees havea minimal effect on design routability, critical data paths, tim-ing driven layout and floorplanning.
• Analog Phase Locked LoopAPLL (Analog Phase Lock Loop) macros can be used in
applications such as clock synthesis with a worst case VCOfrequency of 70 to 250 MHz (30 to 415 MHz typical). TheAPLL is an embedded function and requires 6 (CMOS) or 7(PECL) pins for VCO control, reference frequency, test, andpower signals. No external filters are needed.
An APLL is diffused into two opposite corners of allH4CPlus arrays. No area within the core of the array is usedso the APLL does not contribute to the total gate count.
• Diffused SRAMSUser definable SRAM configurations are available using
Motorola’s Felix SRAM compiler. Felix generates several ver-sions of a given SRAM size, each with different performance,gate counts, and physical configurations.
Table 5. Analog PLL Features
Features Analog PLLOutput Frequency (Vco/2) 35MHz - 125MHzFrequency multiplication Yes
Phase Error +Jitter ±250psMax. Clock Tree Delay @ 50MHz 20ns
Max. Lock Time <10µsPins 6 (CMOS), 7 (PECL)Area 4-5 I/O sites
External Components None
Table 6. Diffused SRAM Features
Features Diffused SRAMsTechnology 3V and 5V
Strobe SynchronousPorts Single, Dual
WordsSingle: 16 - 4096 Dual: 8 - 1024
Bits/WordsSingle: 1 - 64
Dual: 1 - 128
Max. BitsSingle: 65536 (64K)Dual: 16384 (16K)
Routability M3 open
ARCHITECTURAL FEATURESThe H4CPlus Series offers solutions to many of today's de-
sign problems. Increasing application complexities placehigher demands on performance, clock skew management,testability, I/O capability and workstation based design envi-ronments. This section describes some of the special fea-tures of the H4CPlus Series that provide solutions to theseproblems.
Design for TestabilityThe time and cost to test an ASIC increases exponentially
as the complexity and size of the ASIC grows. Using a designfor test (DFT) methodology allows large, complex ASICs to beefficiently and economically tested.
Motorola supports several DFT methodologies, includingESSD/LSSD scan, JTAG boundary scan, and BIST for mem-ories. To take full advantage of these DFT methodologies,Motorola has supported the development of a low-cost, high-speed scan tester.
• ESSD/LSSD ScanMotorola offers Edge Sensitive Scan Design and Level
Sensitive Scan Design (ESSD/LSSD) versions of flip-flops,latches and other functions in the H4CPlus Series library. Au-tomatic Test Pattern Generation (ATPG) can be performedusing Mentor Graphics’ FastScan ATPG tool.
• JTAG Boundary ScanMotorola’s JTAG I/O and JTAG control macrocells are de-
signed to conform to the IEEE 1149.1 JTAG boundary scanspecification. The JTAG I/O macrocells are designed to opti-mize performance and minimize silicon overhead by embed-ding all sequential and multiplexing logic within the I/O sitesof the array.
• Built-In Self TestTwo versions of Built-in-Self-Test (BIST) are available for
memories: “Pseudo-Random” BIST is relatively easy to im-plement, requires few gates, and can achieve fault coverageup to 99%. “Comparator” BIST, on the other hand, is morecomplicated to design and requires more gate overhead, butcan achieve 100% fault coverage.
Clock Distribution and ManagementASICs are becoming an integral part of system design and
are regularly found interfacing with multiple chips includingother ASICs, microprocessors and memories. Optimizingperformance of such systems rests on maximizing communi-cation between chips using synchronous interfaces. Clockskew control and distribution, both on-chip and betweenchips, is of critical importance.The Motorola solution to clockmanagement is to use the clock tree to control skew on-chipand an analog PLL to control clock skew between ASICs.
SPECIAL DESIGN FEATURES (continued)
H4CPlus_Series MOTOROLA
7
THE OPEN ARCHITECTURE CAD SYSTEMThe Open Architecture CAD System (OACS) offers a
highly versatile and powerful design environment for thedesign of Motorola’s H4CPlus Series CMOS arrays. TheOACS integrates several of the industry's most powerfuldesign tools with selected Motorola high-productivity toolsinto standard verilog and EDIF netlist based CAD environ-ments. The information in this data sheet reflects two majorversions of OACS: OACS 4.0 and OACS 3.2M.
OACS 4.0 is Motorola’s point tool CAE solution based onCadence Design System’s Concept schematic editor, Syn-opsys’ synthesis tools, and Cadence’s Verilog XL logic sim-ulator.
OACS 3.2M is Motorola’s framework based CAE solutionusing Mentor Graphic’s Falcon Framework. This solutionprovides support of Mentor’s design entry tools and Quick-Sim II logic simulation.
OACS 4.0 and 3.2M Features Supported Third-Party Design Tools:
• Cadence- Concept, Verilog XL, Veritime, Verifault,
Gate Ensemble, and Dracula• Mentor Graphics
- FastScan, DFTAdvisor, ASICVectors Interface,Falcon Framework, Design Architect,QuickSim II, QuickPath, and AutoLogic
• Quad Design- MOTIVE
• Synopsys- Design Compiler, HDL Compiler, Test
Compiler, and DesignWareSupported Motorola Design Tools:
• Mustang and MTV automatic test pattern generationand verification
• TestPAS test vector validation and extraction• ERC and MARV comprehensive electrical and
manufacturing rules checking• PrediX floorplanning and routability prediction• PrediX IPS physical placement
Supported Systems Capabilities:• Verilog (OACS 4.0) and EDIF 2.0.0 (OACS 3.2M)
backplanes to provide open design environments• Testability support: ESSD/LSSD scan, JTAG boundary
scan, BIST, and scan synthesis• Sophisticated delay and timing limits calculations for
accurate simulation and timing analysis• Estimated and actual (back-annotated) wire
capacitances• Includes intrinsic, rise/fall time, output pin loading and
distributed RC delays• Continuous process, temperature, and voltage
variation• Clock skew management: clock-tree synthesis and
PLL
• Supports multiple technologies: HDC Series, H4CSeries, H4CPlus Series, and M5C Series
• Supported on HP9000/7XX and SUN 4 SPARC
workstations
The OACS Design FlowFrom the conception of your design to its fabrication, you
will see that the OACS design flow is accurate, efficient, andflexible. The design flow has three basic phases (see Figure8) design capture and verification, physical design, and post-layout design verification.
• Design Capture and VerificationPre-layout design is performed by the customer using
OACS tools to develop and simulate the ASIC product. Inaddition to schematic capture, designs can be synthesizedusing a hardware description language (HDL or VHDL),equations, or truth tables. The design may be floorplanned tooptimize for density or performance. PrediX, Motorola’s floor-planning tool, allows experimentation with various floorplansto achieve desired gate density and performance goals. Inaddition, PrediX provides to the designer routability informa-tion to guide the designer in the floorplanning phase. At thispoint in the design phase, delay and timing calculations,netlist verification, automatic test pattern generation, or statictiming analysis can be performed. Pre-layout simulations useestimated best/typical/worst-case delays based on gate,load, slew rate, and floorplan driven estimated RC delays.Prior to the release of the design to layout, the test vectorscreated by the customer must pass specific rules to take fulladvantage of Motorola’s production test equipment.
• Physical DesignPhysical design, place and route, is performed by Motor-
ola’s Option Development Engineers (ODE). An ODE is dedi-cated to each option and works directly with the customer tosatisfy their layout requirements. Options such as timingdriven layout and clock tree synthesis are available to opti-mize silicon performance. Optionally, the user may choose touse PrediX IPS (Integrated Placement Solution) to performmacro placement on the target die and leave only the routingto the ODE. PrediX IPS not only enables the customer tocontrol the actual placement of the critical paths within thecircuit, but also improve the accuracy of the estimated para-sitics and resulting estimated timing over that provided by astandard PrediX floorplan. Upon completion of the physicaldesign, back-annotation data of actual wire routing lengthsand RC parasitics is provided to the customer for post-layoutverification.
• Post-Layout Design VerificationThe post-layout design verification is performed by the
customer to assure that the physical layout of the design sat-isfies all performance and timing requirements. Post-layoutsimulations use the actual parasitics obtained from the physi-cal layout to provide simulations that represent the circuit’sbehavior in silicon. Following a successful post-layout designverification and customer sign-off, Motorola begins manufac-turing of the ASIC design.
AN INTEGRATED DESIGN SYSTEM SOLUTION
MOTOROLA H4CPlus_Series
8
AN INTEGRATED DESIGN SYSTEM SOLUTION
Figure 8. OACS Design Flow
PH
YS
ICA
LD
ES
IGN
DESIGN_INFO - Collect Design Data
CREATE_BLOCK - Create Directory Structure
Behavioral Description
Verilog / QuickSim II - Behavioral Simulation
Design Compiler - Logic Synthesis AutoLogic - Logic Synthesis
EDIFIN - Design Translation
ASIC_CONCEPT - Schematic Capture
Design Architect - Schematic Capture
ERC - Electrical Rules CheckingERC - Electrical Rules Checking Creates Netlist if Required
PrediX -Floorplanning, Placement& Routability Prediction
Verilog - Functional Simulation QuickSim II - Functional Simulation
DECAL - Estimated Timing
ASIC_Verilog - Estimated Timing Simulation
QuickSim II - Estimated Timing Simulation
ASIC_MOTIVE - Timing Analysis ASIC_FastScan / Mustang - ATPG and Fault Grading
TestPAS - Test Pattern Processing
ASIC_RELEASE - Release Files
Gate Ensemble, Dracula - Layout
Release to Motorola
DECAL - Back-Annotated Timing
ASIC_Verilog - Post-Layout Simulation
QuickPath - Timing Analysis
DE
SIG
N C
AP
TU
RE
AN
D V
ER
IFIC
AT
ION
PO
ST-
LAY
OU
T D
ES
IGN
VE
RIF
ICA
TIO
NP
HY
SIC
AL
DE
SIG
N
Mentor EDDM Database
Tool Control Files
Estimated Metal Lengths and Capacitances
Estimated Timing Data
Functional Test Patterns Functional Test PatternsScan Test Patterns
Verified Test Patterns
EDIF Netlist, Layout & Test Vector Data
Actual Metal Lengths and Capacitances
Actual Timing Data
ASIC_MOTIVE - Timing Analysis
Mentor EDDM Database
Test Compiler / DFTAdvisor - Test Synthesis
Verilog Netlists
ASIC_CONFIG - Design File Creation
Pinout - I/O Ring Definition
EDIF Netlists
Invokes Timebase
QuickSim II - Post Layout Timing SimulationInvokes Timebase
Invokes Timebase
QuickPath - Timing AnalysisInvokes Timebase
H4CPlus_Series MOTOROLA
9
Beyond standard QFPs, Motorola offers two styles ofhigh performance, surface mounted packages to comple-ment the H4CPlus Series arrays.
OMPAC (Over-Molded Pad Array Carrier)Motorola has developed a unique plastic pad array carrier
package (OMPAC) to support trends toward PC board spacesavings, improved manufacturing yields and better electricaland thermal performance. OMPAC’s low profile is ideal forportable products. Its ability to handle large die and pin countswithout coplanarity and skew problems makes it well suited toCMOS gate arrays.
The OMPAC package primarily consists of a thin, doublemetal printed circuit board that is overmolded with plastic. Theintegrated circuit is attached to a gold plated die flag on thesubstrate with a silver filled epoxy. Electrical connections tothe integrated circuit are made using conventional gold ballbonding techniques. Etched copper traces extend from thebond finger connections to plated thruhole vias near the edgeof the package, which connect to an array of solder ball termi-nals (lands) on the bottom of the substrate (see Figure 10).
PACKAGING
Figure 10. Simplified Cross-Sectional View of OMPAC
DIE
BT RESIN EPOXYCOPPER FOIL
SOLDER BALL
THERMAL VIA:COPPER PLATED THROUGH-HOLE
SOLDER MASKCOVERING THERMAL VIA
MOLDING COMPOUND
GOLD PLATED DIE ATTACH
SOLDER MASK
DIE ATTACH EPOXY
Figure 9. Over-Molded Pad Array Carrier (OMPAC)saves board space and improves manufacturing yields
MicroCool QUAD FLAT PACKThe MicroCool QFP is a new QFP compatible plastic
package with higher heat dissipation capacity. It has a heatslug attached to a printed circuit board which supports a cop-per lead frame. The package is supported within an MCR tomaintain pin coplanarity. The MicroCool is a high pin densitypackage that is capable of meeting the higher power dissipa-tion (up to 3 W, depending on temperature and ambient con-ditions) and higher performance requirements of the H4CPSeries.
DrypackQFPs, MicroCools and the OMPAC packages will be
shipped by Motorola baked and drypacked. The trend to-wards Surface Mount Technology (SMT) with high density,thinner packages (which are more sensitive to thermal stressfailure during board mounting) has led Motorola to conductnumerous studies. The resultant action is a slow bake ofmoisture from the SMT package and shipping in drypackbags to shield the unit from moisture absorption. Units arebaked at 125oC for 24* hours, cooled and placed in a vacuumsealed drypack with desiccant bags, humidity indicator card,and lot identification stickers.
*Note: Varies by package type, please consult factory.
MOTOROLA H4CPlus_Series
10
Table 7. Package SelectionARRAY NAME H4CP011 H4CP028 H4CP048 H4CP075 H4CP109 H4CP146 H4CP178
CDA Array (Die Size) mils/side 179 239 287 337 391 438 476# of I/O Cells 120 160 208 256 312 360 400
# of Programmable Signal or Power and Ground Pads*
100 156 184 212 252 280 304
# of Dedicated Power and Ground Pads*
20 20 32 44 52 64 72
PACKAGE TYPE 80 QFP (CU)100 QFP (CU)128 QFP (CU)160 QFP (CU)208 QFP (CU)240 QFP (CU)
QQQQQQ
AA
PA
A,FA
PA
A,FA,FA
A,FA,FA,F
A,FA,FA,F
160 MicroCool (CD)208 MicroCool (CD)
A,FA,F
A,FA,F
A,FA,F
169 OMPAC (CU) Q A A A225 OMPAC (CU) Q A A A A A256 OMPAC (CU) Q P A P P313 OMPAC (CU) A A A324 CBGA (CU) P P P
*Numbers indicate wirebond pads availabilityQFP: Plastic Quad Flat Pack (CU) denotes Cavity Up (CD) denotes Cavity DownMicroCool: QFP-type package with heat slugOMPAC: Over-Molded Pad Array Carrier, a PGA type package with solder balls instead of pins, Prototypes for the 169 and 225 OMPAC are supplied in a GTPAC packageCBGA: Ceramic Ball Grid Array, a small footprint hermetic package with superior electrical and excellent thermal performanceA = Available.F = Flexible power pin assignment.P = Planned.Q = Qualified. (Consult factory for qualification status)Note: The 225 OMPAC package has a number of (System/Core) power combinations, see individual pad to pin tables forspecific power features.
PACKAGING (Continued)
H4CPlus_Series MOTOROLA
11
The following tables detail the elements which make up theH4CPlus Series library. The elements are organized into thefollowing categories: Input/Output, Bidirectional Input andOutput Macros, System Interface Macros, Power/GroundMacrocells, Internal Macrocells, Memory Blocks (RAM Mac-rocells).
Gates = equivalent gate count (Internal Macrocells)System/Core I/O Voltage definition:5/5 V = 5 Volt System and 5 Volt Core5/3.3 V = 5 Volt System and 3.3 Volt Core3.3/5 V = 3.3 Volt System and 5 Volt Core3.3/3.3 V = 3.3 Volt System and 3.3 Volt Core
THE MACROCELL LIBRARY
H4CPlus Series Input Macros
InputMacro S
yste
mLo
gic
Cor
eLo
gic
Inve
rtin
g
Non
-Inv
ertin
g
Non
-Inv
ertin
gH
igh
Driv
e
Sch
mitt
Trig
ger
JTA
G
3.3V
5.0V
3.3V
5.0V
CMOS Input LogicICI • • •ICN • • • •ICNH • • • •ICXN • • • •ICXNH • • • •ILCI • • •ILCN • • • •ILCNH • • • •ILSN • • • • •ILSNH • • • • •ISN • • • • •ISNH • • • • •ISXN • • • • •ISXNH • • • • •TTL Input LogicILTXN • • • •ILTXNH • • • •ITN • • • •ITNH • • • •ITSN • • • • •ITSNH • • • • •ILTSXN • • • • •ILTSXNH • • • • •TTL, Fail-Safe Input LogicITNF • • •
H4CPlus Series Output Macros
OutputMacro S
yste
mLo
gic
Cor
eLo
gic
Driv
e(m
A)
1
3-S
tate
Ope
n-D
rain
JTA
G
3.3V
5.0V
3.3V
5.0V
CMOS/TTL Output LogicON2x • • 3 •* • •ON4x • • 6 •* • •ON8x • • 12 •* • •ON16x • • 24 •* • •ON32x • • 48 •* • •ONL2x • • 2 • •ONL4x • • 3 • • •ONL8x • • 6 •* • •ONL16x • • 12 •* • •ONL32x • • 24 • • •ONLX2x • • 2 • •ONLX4x • • 3 • • •ONLX8x • • 6 •* • •ONLX16x • • 12 •* • •ONLX32x • • 24 • •ONX2x • • 3 • •ONX4x • • 6 • • •ONX8x • • 12 • • •ONX16x • • 24 • • •ONX32x • • 48 • •TTL, Fail-Safe Output LogicON8TF • • 12 •
1. See electrical specifications for additional infor-x = Suffix such as S2, T, and OD.* = 3-State with Slew Rate Control
MOTOROLA H4CPlus_Series
12
THE MACROCELL LIBRARY (Continued)
Bidirectional Input and Output Macros JTAG TAP I /O Functions
InputMacro
SystemLogic
CoreLogic
Inve
rtin
g
Non
-Inv
ertin
g
Sch
mitt
Trig
ger
JTA
G JTAG I/OMacro
System Logic Core Logic
3.3V
5.0V
3.3V
5.0V 3.3V 5.0V 3.3V 5.0V
CMOS Input Logic CMOS Input LogicBICI • • • TCK • •BICN • • • • TCKH • •BICXN • • • • TDI • •BILCI • • • TDOUT • •BILCN • • • • TMS • •BILSN • • • • • TRSTB • •BISN • • • • TCKX • •BISXN • • • • • TCKHX • •TTL Input Logic TDIX • •BILTXN • • • • TDOUTX • •BITN • • • • TMSX • •BITSN • • • • • TRSTBX • •BILTSXN • • • • • TDOUTLX • •TTL, Fail-Safe Input Logic TCKL • •BITNF • • • TCKHL • •
OutputMacro
SystemLogic
CoreLogic
Driv
e(m
A1
Ope
n-D
rain
3-S
tate
JTA
G2
TDIL • •TDOUTL • •
3.3V
5.0V
3.3V
5.0V
TMSL • •TRSTBL • •
CMOS/TTL Output Logic TTL LogicBON2x • • 3 •* • TCKT • •BON4x • • 6 • •* • TCKHT • •BON8x • • 12 • •* • TDIT • •BON16x • • 24 • •* • TMST • •BON32x • • 48 • •* • TRSTBT • •BONL2x • • 2 • • TCKTX • •BONL4x • • 3 • • • TCKHTX • •BONL8x • • 6 • •* • TDITX • •BONL16x • • 12 • •* • TMSTX • •BONL32x • • 24 • • • TRSTBTX • •BONLX2x • • 2 • • TCKLTX • •BONLX4x • • 3 • • • TCKHLTX • •BONLX8x • • 6 • •* • TDILTX • •BONLX16x • • 12 • •* • TMSLTX • •BONLX32x • • 24 • • • TRSTBLTX • •BONX2x • • 3 • •
1. See electrical specifications for additional informa-tion. 2. For Bidirectional JTAG Macro the O is removed inthe name. i.e.: BON2T = BN2TJ x = Suffix such as S2, T, and OD. * = 3-State with Slew Rate Control
BONX4x • • 6 • • •BONX8x • • 12 • • •BONX16x • • 24 • • •BONX32x • • 48 • •TTL, Fail-Safe Output LogicBON8TF • • 12TTL, Extended Range Voltage Output LogicBONLE8T • • 6 • •BONLE16T • • 12 • •
H4CPlus_Series MOTOROLA
13
THE MACROCELL LIBRARY (Continued)
H4CPlus Series System Interface Macros
InputMacro
SystemLogic
CoreLogic
Inve
rtin
g
Non
-Inv
ertin
g
Diff
eren
tial
JTA
G OutputMacro
SystemLogic
CoreLogic
Diff
eren
tial
JTA
G
3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V
CMTL Input Logic CMTL Output LogicBICMD • • • BOD32TCMT • • •ICMD • • • • O32CM • •ILCMD • • • OD32CMT • • • •GTL Input Logic OD32TCMT • • • •BIGN • • • • ODX32CM • • •IGI • • • ODLX32CMT • • •IGN • • • • ODL32CMT • • • •BILGN • • • • GTL Output LogicILGI • • • BON40G • • •ILGN • • • • ON20G • • •IGD • • • ODL20G • • •ILGD • • • OD20G • • •PCI Input Logic BONL40G • • •IPCH • • • • ONL20G • • •IPCXN • • • • PCI Output LogicIPCXNH • • • • BONTPC • • •BILPC • • • • BONXTPC • • •BIPCXN • • • • BONLXTPC • • •ILPC • • • • ONPCS2 • • •ILPCH • • • • ONPC • • •PECL Input Logic ONTPC • • •IPD • • • • BONLTPC • • •IPN • • • BONTPCS2 • • •ILPD • • • ONLPC • • •ILPN • • • ONLTPC • • •IPXD • • • ONXPC • • •IPXN • • • ONXTPC • • •Oscillators ONLXPC • • •OSCPB • • • ONLXTPC • • •OSCPHB • • • ONTPCS2 • • •OSCPSB • • • Analog PLLOSCPBL • • • AP1 • •OSCPHBL • • • AP2 • •OSCPSBL • • • APD1 • • •Reference Voltage Macros/Resistors APD2 • • •PUL • • • • APT1 • •PDL • • • • APT2 • •ENID • • • • PLLDelay • • • •
APL1 • •APL2 • •APDL1 • • •APDL2 • • •
MOTOROLA H4CPlus_Series
14
# INTERNAL MACROS Gates
AND Gates1 AND2 2-Input AND Gate 22 AND2H 2-Input AND Gate, 2X Drive 23 AND3 3-Input AND Gate 24 AND3H 3-Input AND Gate, 2X Drive 35 AND4 4-Input AND Gate 36 AND4H 4-Input AND Gate, 2X Drive 37 AND8H 7-Input AND Gate, 2X Drive 6
NAND Gates1 NAN2 2-Input NAND Gate 12 NAN2H 2-Input NAND Gate, 2X Drive 23 NAN2B 2-Input NAND Gate, Balanced 24 NAN3 3-Input NAND Gate 25 NAN3H 3-Input NAND Gate, 2X Drive 36 NAN4 4-Input NAND Gate 27 NAN4H 4-Input NAND Gate, 2X Drive 48 NAN5 5-Input NAND Gate 49 NAN5H 5-Input NAND Gate, 2X Drive 5
10 NAN6CH6-Input NAND Gate, 2X Drive,1X Complementary Output
6
11 NAN8H 7-Input NAND Gate, 2X Drive 7OR Gates
1 OR2 2-Input OR Gate 22 OR2H 2-Input OR Gate, 2X Drive 23 OR3 3-Input OR Gate 24 OR3H 3-Input OR Gate, 2X Drive 35 OR4 4-Input OR Gate 36 OR4H 4-Input OR Gate, 2X Drive 37 OR8H 7-Input OR Gate, 2X Drive 8
NOR Gates1 NOR2 2-Input NOR Gate 12 NOR2H 2-Input NOR Gate, 2X Drive 23 NOR2B 2-Input NOR Gate, Balanced 24 NOR3 3-Input NOR Gate 25 NOR3H 3-Input NOR Gate, 2X Drive 46 NOR4 4-Input NOR Gate 47 NOR4H 4-Input NOR Gate, 2X Drive 48 NOR5 5-Input NOR Gate 49 NOR5H 5-Input NOR Gate, 2X Drive 5
10 NOR6CH6-Input NOR Gate, 2X Drive,1X Complementary Output
6
11 NOR8H 7-Input NOR Gate, 2X Drive 7EXCLUSIVE OR & EXCLUSIVE NOR Gates
1 EXNORA 2-Input EXNOR, Unbuffered Inputs 32 EXNOR3H 3-Input Exclusive NOR, 2X Drive 8
3 EXORA2-Input Exclusive OR, UnbufferedInputs
3
4 EXOR3H 3-Input Exclusive OR, 2X Drive 85 EXOR4H 4-Input Exclusive OR, 2X Drive 10
AND/NOR, AND/OR, OR/NAND, & OR/AND Gates
1 ANDOI222-Input AND + 2-Input NOR, into2-Input NOR
3
2 ANDOI22H2-Input AND+2-Input NOR,→2-Input NOR 2X Drive
4
3 AO21H2-Input AND, 1-Wide,→2-Input OR,2X Drive
3
4 AO22H2-Input AND, 2-Wide, into 2-Input OR,2X Drive
3
AND/NOR, AND/OR, OR/NAND, & OR/AND Gates (Cont’)5 AO321H 3,2,1-input AND-OR, 2X Drive 56 AO4321H 4,3,2,1-input AND-OR, 2X Drive 87 AOI21 2-Input AND, 1-Wide,→2-input NOR 2
8 AOI21H2-Input AND, 1-Wide, → 2-input NOR, 2X Drive
3
9 AOI211 2-Input AND, 1-Wide,→3-input NOR 2
10 AOI211H2-Input AND, 1-Wide, → 3-input NOR,2X Drive
4
11 AOI22 2-Input AND, 2-Wide,→2-input NOR 2
12 AOI22H2-Input AND, 2-Wide,→2-input NOR,2X Drive
4
13 OA21H2-Input OR, 1-Wide,→2-input AND,2X Drive
3
14 OA22H2-Input OR, 2-Wide,→2-input AND,2X Drive
3
15 OAI21 2-Input OR, 1-Wide,→2-input NAND 2
16 OAI21H2-Input OR, 1-Wide,→2-input NAND,2X Drive
3
17 OAI211 2-Input OR, 1-Wide,→3-input NAND 2
18 OAI211H2-Input OR,1-Wide,→3-input NAND, 2X Drive
4
19 OAI22 2-Input OR, 2-Wide,→2-input NAND 2
20 OAI22H2-Input OR, 2-Wide, → 2-input NAND,2X Drive
4
21 ONDAI222-Input OR + 2-Input NAND,→2-InputNAND
3
22 ONDAI22H2-Input OR + 2-Input NAND,→ 2-InputNAND, 2X Drive
4
Inverting Buffers1 INV Inverter 1
2 INVBInverter, Balanced(Symmetrical Rise & Fall)
1
3 INV2 2-Inverters in parallel 1
4 INV2B2-Inverters in parallel, Balanced(Symmetrical Rise & Fall)
2
5 INV4 4-Inverters in parallel 2
6 INV4B4-Inverters in parallel, Balance(Symmetrical Rise & Fall)
4
7 INV8 7-Inverters in parallel 4
8 INV8B7-Inverters in parallel, Balanced(Symmetrical Rise & Fall)
8
9 INVXInverted Buffer (used to drive internallogic from an I/O Site)
--
Non-Inverting Buffers1 BUF 1X drive Buffer 12 BUF2 2X drive Buffer 2
3 BUF2B2X drive Buffer, Balanced(Symmetrical Rise & Fall)
3
4 BUF4 4X drive Buffer 3
5 BUF4B4X drive Buffer, Balanced(Symmetrical Rise & Fall)
5
6 BUF8 8X drive Buffer 5
7 BUF8B8X drive Buffer, Balanced(Symmetrical Rise & Fall)
9
8 BUFXNon-Inverting Buffer (used to driveinternal logic from an I/O Site)
--
# INTERNAL MACROS Gates
THE MACROCELL LIBRARY (Continued)
H4CPlus_Series MOTOROLA
15
3-State Buffers1 TBUF 3-state Buffer, Active Low Enable 4
2 TBUFH3-state Buffer, Active Low Enable,2X Drive
5
3 TBUFP 3-state Buffer, Active High Enable 4
4 TBUFPH3-state Buffer, Active High Enable,2X Drive
5
5 INVTInverting 3-state Buffer, Active LowEnable
2
6 INVTHInverting 3-state Buffer, Active LowEnable, 2X Drive
3
7 INVTPInverting 3-state Buffer, Active HighEnable
3
8 INVTPHInverting 3-state Buffer,Active High Enable, 2x Drive
4
D Type Flip-Flops1 DFF1A Scan D Flip-Flop 152 DFF4A 4-Bit Scan D Flip-Flop 48
3 DFFGLPD Flip-Flop, Multiplexed (or Scan)Input with HOLD function
13
4 DFFP D Flip-Flop 85 DFFPH DFFP, 2X Drive 8
6 DFFLPAD Flip-Flop, Multiplexed (or Scan)W/Unbuffered Input/ Clock
8
7 DFFLPAH DFFLP, 2X Drive 98 DFFRP D Flip-Flop with Reset 89 DFFRPH DFFRP, 2X Drive 10
10 DFFRLPD Flip-Flop W/Reset, Multiplexed(or Scan) Input
11
11 DFFRLPH DFFRLP, 2X Drive 1112 DFFRSLPB D Flip-Flop w/Set and Reset 1413 DFFRSPHB D Flip-Flop w/Set and Reset, 2X Dr. 1014 DFFSCH DFFSC, 2X Drive 1815 DFFSCAH DFFSCA, 2X Drive 2016 DFFSP D Flip-Flop with Set 817 DFFSPH DFFSP, 2X Drive 10
18 DFFSLPD Flip-Flop w/Set, Multiplexed(or Scan) Input
12
19 DFFSLPH DFFSLP, 2X Drive 1220 DFFSRPA D Flip-Flop with Synchronous Reset 9
21 DFFSRLPAD Flip-Flop, Multiplexed (or Scan)Input with Synchronous Reset
12
22 DFFSSP D Flip-Flop with Synchronous Set 9
23 DFFSSLPD Flip-Flop, Multiplexed (or Scan)Input with Synchronous Set
12
Latches1 LATN D-Type Latch, Neg Gate Latched 52 LATNH LATN, 2X Drive 63 LATP D-Type Latch, Pos Gate Latched 54 LATPH LATP, 2X Drive 6
5 LATRND-Type Latch W/Reset, Neg GateLatched
6
6 LATRNH LATRN, 2X Drive 7
7 LATRPD-Type Latch W/Reset, Pos GateLatched
6
8 LATRPH LATRP, 2X Drive 79 LAT4TH LAT4TH, 2X Drive 23
10 LSSD1AH LSSD1A, 2X Drive 1411 SRLSSD1H SRLSSD1, 2X Drive 13
# INTERNAL MACROS Gates
Multiplexers1 MUX2A 2-1 Multiplexer, 1X Drive 32 MUX2H 2-Input Multiplexer, 2X Drive 33 MUX2IH MUX2I, 2X Drive 34 MUX4H 4-Input Multiplexer, 2X Drive 75 MUX41A Four 2-1 MUX with Common Select 126 MUX41AH MUX41A, 2X Drive 147 MUX8AH 7-Input Multiplexer, 2X Drive 18
8 MX414-Input Multiplexer W/individualSelects
5
9 MX41H MX41, 2X Drive 6
10 MX616-Input Multiplexer W/IndividualSelects
8
11 MX61H MX61, 2X Drive 9
12 MX818-Input Multiplexer W/IndividualSelects
10
13 MX81H MX81, 2X Drive 12Decoders
1 DEC4H DEC4, 2X Drive 9
2 DEC4AH1 of 4 Decoder, Active High Outputs,2X Drive
14
3 DEC1OF81 of 8 Decoder with Enable, Active LowOutputs
16
4 DEC8AH1 of 8 Decoder with Enable, ActiveHigh Outputs, 2X Drive
30
Arithmetic Circuits1 AD4FULA 4-Bit Full Adder, 2X Drive 40
2 AD4PG4-Bit Full Adder with Propagate &Generate, 2X Drive
94
3 ADFULH ADFUL, 2X Drive 104 ADFULHA Full Adder, 2X Drive 105 ADHALFH ADHALF, 2X Drive 66 ECOMP4 4-Bit Equality Comparator 167 LACG4 4-bit Look-Ahead-Carry Generator 328 MCOMP4 4-bit Magnitude Comparator 359 SBHALF Half Subtracter 6
Miscellaneous1 DCR4H 4-Bit Decrementer, 2X Drive 282 DLY8 7-Stage Inverter Delay 43 INC4H 4-Bit Incrementer, 2X Drive 284 MUL8X8 8X8 -Bit Unsigned Multiplier 11065 ROT8A 7-Bit Rotate, 1X Drive 546 SHIFT8 7-Bit Shift Register 45
BIST Soft Macros
1 ADDR_CELLAddress Counter Cell for SimplifiedBIST
20
2 DATA_CELL Pattern generator & Signature Analysis 273 COMPACELL Address Cell for Comparator BIST 344 COMPDCELL Data Cell for Comparator BIST 54
5COMPBISTCNTL
BIST Controller for Comparator BIST 780
JTAG Control Macro Functions1 BPREG 1-Bit Bypass Register 102 ENSCANI Enable Boundary scan Macro 20
3 IDREG32-Bit device Identification CodeRegister
256
4 MC_IREG 1-Bit Instruction Register (Soft Macro) 255 MC_IREG4 4-Bit Instruction Register (Soft Macro) 124
6 FMC_TAPCBTAP Controller (FIRM Macro) FixedPlacement which effects Routing
276
# INTERNAL MACROS Gates
THE MACROCELL LIBRARY (Continued)
MOTOROLA H4CPlus_Series
16
Miscellaneous JTAG Macro1 CKDRMID B-S Register Clock Driver 02 CKDRCC1 B-S Register Clock Driver 03 CKDRCC2 B-S Register Clock Driver 04 ENSCANJ B-S Register Enable Scan Macro 05 IMCDR B-S Reg. input Mode Control Driver 06 OMCDR B-S Reg. Output Mode Control Driver 07 ISOR Clock Net ISO and Test Data Resync 08 SHDR B-S Register Shift Driverr 09 TDBUF B-S Register Test Data Buffer 0
10 UDDR B-S Register Update Driver 0
MEMORY BLOCKS
# Name Ram SizeGate
Count
Single-Port RAM’s (Low Power)1 RSB8X8 8 word X 8bit 1982 RSB8X18 8 word X 18bit 4403 RSB16X8 16 word X 8bit 3424 RSB16X18 16 word X 18bit 7605 RSB16X36 16 word X 36 bit 14406 RSB32X8 32 word X 8bit 6307 RSB32X18 32 word X 18 bit 1400
# INTERNAL MACROS Gates
Single-Port RAM’s (Low Power) (Cont’)8 RSB32X36 32 word X 36 bit 26609 RSB64X18 64 word X 18 bit 268010 RSB64X36 64 word X 36 bit 5092
Dual-Port RAM’s (High Speed)1 RDB8X9 8 word X 9 bit 3562 RDB8X18 8 word X 18 bit 6083 RDB8X36 8 word X 36 bit 11124 RDB8X72 8 word X 72 bit 21565 RDB16X9 16 word X 9 bit 7256 RDB16X18 16 word X 18 bit 11937 RDB16X36 16 word X 36 bit 21298 RDB16X72 16 word X 72 bit 40509 RDB32X9 32 word X 9 bit 140010 RDB32X18 32 word X 18 bit 230011 RDB32X36 32 word X 36 bit 410012 RDB32X72 32 word X 72 bit 7798
Quad-Port RAM’s1 RQB16X18 16 word X 18 bit 22002 RQB16X36 16 word X 36 bit 37663 RQB32X18 32 word X 18 bit 47624 RQB32X36 32 word X 36 bit 7738
MEMORY BLOCKS
# Name Ram SizeGate
Count
THE MACROCELL LIBRARY (Continued)
MACROCELL EXAMPLES
INPUT MACROCELLS
Inverting CMOS Inputs and Bidirectional Input(3.3 V and 5 V System/Core Voltages)
ICI/BICIILCI
MACRO SECTIONS USED
ICI/ILCI 1/0BICI 1/0
Rev. 1.09
MACRO OUTPUTS/INPUTS
ICI/ILCI DI / PAD,ICBICI DI / BC
MACRO INPUT CAP.
ICI/ILCI PAD: 5.29pFBICI BC: 0.39pF
Function TablePAD DI
L HH L
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter5/5 V 3.3/3.3 V
FO=0 FO=2 FO=8 K (ns/pF) FO=0 FO=2 FO=8 K (ns/pF)
ICI/BICI ILCI
tPLH Propagation Delay,PAD to DI
0.18 0.19 0.23 0.12 0.23 0.24 0.29 0.15tPHL 0.16 0.18 0.22 0.15 0.20 0.22 0.27 0.18
tr Output Rise Time, DI 0.18 0.20 0.27 0.24 0.20 0.23 0.33 0.33tf Output Fall Time, DI 0.17 0.19 0.25 0.18 0.15 0.18 0.25 0.24
Capacitance per fanout = 0.05 pF (metal capacitance is not included).
5/5 V3.3/3.3 V
XX
ICI/ILCI
DIIC
XXXPAD
BICI
DIBC
H4CPlus_Series MOTOROLA
17
MACROCELL EXAMPLES (Continued)
OUTPUT MACROCELLS
Non-Inverting Output Buffers(3.3 V and 5 V System/Core Voltages)
ONnONXn
ONLXnONLn
MACRO SECTIONS USED
All 0/1Rev. 1.09
MACRO OUTPUTS/INPUTS
All PAD / DO
MACRO INPUT CAP.
ON2,ONL2 DO: 0.28pFON8,ONL8 DO: 0.56pF
ONX2 DO: 0.40pFONX8 DO: 0.47pF
ONLX2 DO: 0.30pFONLX8 DO: 0.75pF
Function TableDO PADL LH H
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter5/5 V 3.3/5 V
pF=0 pF=50 pF=100 K (ns/pF) pF=0 pF=50 pF=100 K (ns/pF)
ON2 ONLX2
tPLH Propagation Delay,DO to PAD
0.41 4.92 9.43 0.09 0.89 4.85 8.80 0.08tPHL 0.38 6.27 12.15 0.12 0.35 4.47 8.59 0.08
tr Output Rise Time, PAD 0.22 10.61 21.00 0.21 0.36 9.34 18.33 0.18tf Output Fall Time, PAD 0.23 11.80 23.37 0.23 0.18 9.55 18.92 0.19
ON8 ONLX8
tPLH Propagation Delay,DO to PAD
0.43 1.74 3.05 0.03 0.77 2.19 3.61 0.03tPHL 0.75 2.03 3.32 0.03 0.68 1.87 3.07 0.02
tr Output Rise Time, PAD 0.21 3.13 6.06 0.06 0.53 3.46 6.40 0.06tf Output Fall Time, PAD 0.46 3.29 6.11 0.06 0.48 2.79 5.10 0.05
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter5/3.3 V 3.3/3.3 V
pF=0 pF=50 pF=100 K (ns/pF) pF=0 pF=50 pF=100 K (ns/pF)
ONX2 ONL2
tPLH Propagation Delay,DO to PAD
0.70 5.19 9.69 0.09 0.55 6.95 13.35 0.13tPHL 0.86 6.56 12.27 0.11 0.53 7.58 14.63 0.14
tr Output Rise Time, PAD 0.49 10.87 21.26 0.21 0.32 14.63 28.93 0.29tf Output Fall Time, PAD 0.54 12.10 23.66 0.23 0.31 14.40 28.49 0.28
ONX8 ONL8
tPLH Propagation Delay,DO to PAD
1.06 2.49 3.92 0.03 0.57 2.41 4.25 0.04tPHL 1.15 2.72 4.29 0.03 0.95 2.49 4.03 0.03
tr Output Rise Time, PAD 0.70 3.57 6.43 0.06 0.25 4.28 8.32 0.08tf Output Fall Time, PAD 0.58 3.40 6.23 0.06 0.56 3.98 7.41 0.07
5/5 V5/3.3 V3.3/5 V3.3/3.3 Vn=2, 4, 8, 16
XXDO
ONn / ONXn / ONLXn / ONLn
XXXPAD
MOTOROLA H4CPlus_Series
18
MACROCELL EXAMPLES (Continued)
CMTL Differential Input and Bidirectional Input(3.3 V and 5 V Core Voltages) ICMD
BICMDILCMDMACRO SECTIONS USED
ICMD/ILCMD 1/0
BICMD 1/0
Rev. 1.09
MACRO OUTPUTS/INPUTS
ICMD/ILCMD DI / PAD,PAD2,IC,IC2
BICMD DI / BC,BC2
MACRO INPUT CAP.
ICMD PAD,PAD2: 5.06pF
BICMD BC,BC2: 0.130F
ND = Not Defined
Function TablePAD/BC PAD2/BC2 DI
L H LH L HL L NDH H ND
5/5 V3/3 V
CMTL SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter
5/5 V 3/3 V
FO=0 FO=2 FO=8 K (ns/pF) FO=0 FO=2 FO=8 K (ns/pF)
ICMD/BICMD ILCMD
tPLH Propagation Delay,PAD,PAD2 to DI
0.88 0.89 0.93 0.11 1.22 1.24 1.29 0.17tPHL 0.83 0.85 0.89 0.15 1.27 1.29 1.34 0.19
tr Output Rise Time, DI 0.08 0.08 0.10 0.04 0.09 0.10 0.14 0.13tf Output Fall Time, DI 0.05 0.06 0.10 0.12 0.09 0.11 0.16 0.16
INTERNAL MACROCELLS (COMBINATIONAL)
2-Input NAND Gate, 1X Drive(3.3 V and 5 V Core Voltages)
NAN2
MACRO EQUIV. GATES
NAN2 1
Rev. 1.09
MACRO OUTPUTS/INPUTS
NAN2 X / A,B
MACRO INPUT CAP.
NAN2 A,B: 0.05pF
FUNCTION TABLEA B X
L L H
L H H
H L H
H H L
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter
5V 3.3 V
FO=0 FO=2 FO=8 K (ns/pF) FO=0 FO=2 FO=8 K (ns/pF)
NAN2
tPLH Propagation Delay,A to X
0.12 0.21 0.45 0.82 0.17 0.29 0.63 1.15tPHL 0.27 0.38 0.72 1.14 0.34 0.49 0.94 1.50tPLH Propagation Delay,
B to X0.17 0.25 0.49 0.82 0.22 0.34 0.68 1.15
tPHL 0.24 0.36 0.70 1.13 0.31 0.46 0.91 1.50tr Output Rise Time, X 0.23 0.47 1.20 2.42 0.29 0.63 1.66 3.44tf Output Fall Time, X 0.20 0.40 0.99 1.96 0.22 0.47 1.23 2.54
Fanout (FO) capacitance does not include estimated metal lengths (each FO = 0.06pF).
XX
XXXPAD
BICMD
XX
DI
XXXPAD2
ICMD / ILCMDIC
IC2
DIBC2
BC
B
ANAN2 X
H4CPlus_Series MOTOROLA
19
MACROCELL EXAMPLES (Continued)
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter5 V 3.3 V
FO=0 FO=2 FO=8 K (ns/pF) FO=0 FO=2 FO=8 K (ns/pF)DFFSCH
tPLH Propagation Delay,ACLK to SQ
0.67 0.75 1.00 0.83 0.98 1.09 1.44 1.16tPHL 0.66 0.73 0.96 0.76 0.90 0.99 1.27 0.92tPLH Propagation Delay,
BCLK to Q0.66 0.69 0.77 0.26 0.95 0.99 1.10 0.36
tPHL 0.88 0.93 1.08 0.48 1.32 1.39 1.58 0.65tPLH Propagation Delay,
BCLK to QB1.13 1.16 1.23 0.23 1.74 1.77 1.87 0.33
tPHL 1.29 1.33 1.45 0.41 1.80 1.85 2.01 0.52tPLH Propagation Delay,
BCLK to SQ1.83 1.91 2.16 0.83 2.77 2.89 3.23 1.16
tPHL 1.85 1.93 2.16 0.76 2.62 2.72 2.99 0.92tPLH Propagation Delay,
CK to Q0.96 0.98 1.06 0.27 1.38 1.42 1.53 0.37
tPHL 1.09 1.14 1.28 0.48 1.62 1.68 1.88 0.64tPLH Propagation Delay,
CK to QB1.34 1.37 1.44 0.23 2.03 2.06 2.16 0.33
tPHL 1.60 1.64 1.76 0.41 2.26 2.31 2.46 0.52tPLH Propagation Delay,
CK to SQ2.18 2.26 2.51 0.83 3.28 3.39 3.74 1.16
tPHL 2.28 2.35 2.58 0.76 3.25 3.34 3.61 0.92tPLH Propagation Delay,
SDI to Q0.56 0.58 0.66 0.25 0.81 0.85 0.96 0.36
tPHL 0.75 0.80 0.94 0.48 1.13 1.20 1.39 0.65tPLH Propagation Delay,
SDI to QB0.96 0.98 1.05 0.24 1.54 1.58 1.67 0.32
tPHL 1.12 1.16 1.28 0.40 1.58 1.63 1.78 0.52tPLH Propagation Delay,
SDI to SQ1.68 1.75 1.98 0.76 2.40 2.49 2.77 0.92
tPHL 1.68 1.76 2.01 0.82 2.57 2.69 3.03 1.16tr Output Rise Time, Q 0.29 0.35 0.52 0.57 0.38 0.46 0.71 0.82tf Output Fall Time, Q 0.44 0.49 0.67 0.59 0.59 0.66 0.89 0.75tr Output Rise Time, QB 0.26 0.32 0.49 0.56 0.32 0.40 0.64 0.79tf Output Fall Time, QB 0.31 0.36 0.53 0.55 0.36 0.43 0.63 0.68tr Output Rise Time, SQ 0.20 0.44 1.17 2.44 0.25 0.60 1.63 3.44tf Output Fall Time, SQ 0.18 0.30 0.65 1.17 0.24 0.39 0.81 1.40
Capacitance per fanout = 0.05 pF (metal capacitance is not included).
INTERNAL MACROCELLS (SEQUENTIAL)
D Flip-Flop with Scan Latch 2X Drive(3.3 V and 5 V Core Voltages)
DFFSCH
MACRO EQUIV. GATES
DFFSCH 18
Rev. 1.09
MACRO OUTPUTS/INPUTS
DFFSCHQ,QB,SQ /
D,CK,SDI,BCLK,ACLK,EN
MACRO INPUT CAP.
DFFSCH
ACLK,BCLK,EN: 0.10pF CK: 0.05pF D: 0.16pF
SDI: 0.20pF
FUNCTIONAL DESCRIPTION:This macro consists of a D type Flip-Flop with Q feedback
(hold) capability. It allows scan data to be muxed into the slavestage and contains a separate scan latch for storing scan dataindependent of Q. CK clocks the Flip-Flop, BCLK controls latch-ing scan data into the slave stage and ACLK controls the finalscan data latch.
FUNCTION TABLED EN CK SDI BCLK ACLK Q QB SQ Notes
X X L X L L Q QB SQ 1
X L / X L L Q QB SQ 2
L H / X L L L H SQ 3
H H / X L L H L SQ 3
X X L X L H Q QB QB 4
X X L L H L H L SQ 5
X X L H H L L H SQ 5
X X L L H H H L L 6
X X L H H H L H H 6
1. No Clock 2. Active Clock, disabled 3. Active Clock, enabled
4. Scan-out Clock applied 5. Scan-in Clock applied 6. Flush or Ring-oscillate
DFFSCH
CK
SDIBCLK
D
QBQ
ACLKEN
SQ
MOTOROLA H4CPlus_Series
20
FUNCTIONAL DIAGRAM: DFFSCH
CMOS TIMING REQUIREMENTS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter
5 V 3.3 V
Minimum Requirement Minimum Requirement
DFFSCH
tsu Set Up Time, BCLK to ACLK 1.70 2.59
tsu Set Up Time, CK to ACLK 1.84 2.74
tsu Set Up Time, SDI to ACLK 1.67 2.50
tsu Set Up Time, SDI to BCLK 1.33 1.93
tsu Set Up Time, D to CK 0.15 0.34
tsu Set Up Time, EN to CK 0.43 0.66
th Hold Time, ACLK to BCLK -1.21 -1.71
th Hold Time, ACLK to CK -1.21 -1.87
th Hold Time, ACLK to SDI -1.08 -1.58
th Hold Time, BCLK to CK -1.07 -1.65
th Hold Time, BCLK to SDI 0.00 -0.01
th Hold Time, CK to BCLK -1.05 -1.51
th Hold Time, CK to D 0.43 0.57
th Hold Time, CK to EN 0.23 0.31
trec Recovery Time, CK to ACLK 1.97 2.93
trec Recovery Time, ACLK to CK -1.49 -2.20
tw Pulse Width, ACLK(H) 0.43 0.65
tw Pulse Width, BCLK(H) 1.28 1.89
tw Pulse Width, CK(L) 0.59 0.94
tw Pulse Width, CK(H) 1.52 2.20
CK C
CKB
*2X for DFFSCH
EN
SDI
BC
BCKB
*
*ACKB
AC AC
ACKB
SQ
QB
QC
CKBCKB
C
C C
CKB
CKB
ACLK ACKB
AC
D
BCKB
BC
BCLK
*
BC
Note: Outputs have balanced drive.
MACROCELL EXAMPLES (Continued)
H4CPlus_Series MOTOROLA
21
• Random Access MemoriesMotorola offers 26 different building blocks that can be
used to construct Single-, Dual-, and Four-Port memories. Acomprehensive guide to using these blocks and their perfor-mance is shown in the H4CPlus Series Design ReferenceGuide. (H4CPDM/D)
• Multiple Memory BlocksIt is possible to combine two or more memory blocks to
create larger memory blocks. When multiple blocks are used,
the user is responsible for creating the external decoder logicneeded. The maximum number of SRAM blocks on an arrayis restricted to 16, depending on array/SRAM sizes.
• Array SizingTo choose an array into which a design with SRAM will fit,
two considerations must be evaluated: the physical size/lay-out of the SRAM or SRAMs, and the gate utilization.
MACROCELL EXAMPLES (Continued)
METALLIZED SRAM BLOCKS
RDBXXxXX -High Speed Dual-Port SRAMEquivalent Gates: see belowPin names:
A_A(0-m) - address bus for Port AA_B(0-m) - address bus for Port BDIN_A(0-n) -input dataWB_A - Write enable bus for Port ADO_B(0-n) - data output determined by address bus, Port B
Size(Words X Bits) Name
Size(Columns X Rows)
TotalGate Count
Port A InputCapacitance
Per Address Line
Port A InputCapacitanceWB_A Line
Port B InputCapacitance
Per Address Line
8-WORD BLOCK8X9 RDB8X9 13X14 356
0.15 pF 0.18 pF 0.15 pF8X18 RDB8X18 22X14 6088X36 RDB8X36 40X14 11128X72 RDB8X72 77X14 2156
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter5.0 V 3.3 V
FO=0 FO=2 FO=8 K (ns/pF) FO=0 FO=2 FO=8 K (ns/pF)RDB8X9
tPLH Propagation Delay,A0-A2 to DO0-DO8
1.75 1.83 2.07 0.81 2.67 2.79 3.14 1.20tPHL 1.92 1.99 2.20 0.68 2.94 3.02 3.25 0.77tPLH Propagation Delay,
DIN0-DIN8 to DO0-DO81.47 1.55 1.80 0.81 2.51 2.63 2.98 1.17
tPHL 2.11 2.18 2.39 0.70 3.03 3.12 3.38 0.87tPLH Propagation Delay,
RWB0-RWB8 to DO0-DO82.34 2.43 2.68 0.83 3.74 3.86 4.20 1.13
tPHL 2.40 2.47 2.69 0.71 3.54 3.63 3.88 0.85tr Output Rise Time, DO0-DO8 0.18 0.43 1.19 2.52 0.35 0.72 1.83 3.70tf Output Fall Time, DO0-DO8 0.41 0.51 0.82 1.02 0.48 0.61 0.98 1.25
RDB8X18tPLH Propagation Delay,
A0-A2 to DO0-DO171.84 1.93 2.17 0.82 2.92 3.04 3.39 1.18
tPHL 2.07 2.14 2.35 0.70 2.99 3.08 3.34 0.88tPLH Propagation Delay,
DIN0-DIN17 to DO0-DO171.47 1.55 1.80 0.81 2.51 2.63 2.98 1.17
tPHL 2.11 2.18 2.38 0.70 3.03 3.11 3.37 0.87tPLH Propagation Delay,
RWB0-RWB17 to DO0-DO172.48 2.56 2.81 0.82 3.99 4.11 4.46 1.16
tPHL 2.64 2.70 2.89 0.63 3.77 3.85 4.09 0.80tr Output Rise Time, DO0-DO17 0.18 0.43 1.19 2.52 0.40 0.75 1.82 3.56tf Output Fall Time, DO0-DO17 0.66 0.75 1.00 0.84 0.42 0.56 0.99 1.43
Capacitance per fanout = 0.06 pF (metal capacitance is not included).
A_A(0-m)
RDBXXxXX
DIN_A(0-n)
WB_A(0-n)
DO_B(0-n)
A_B(0-m)
MOTOROLA H4CPlus_Series
22
RDB8X36tPLH Propagation Delay,
A0-A2 to DO0-DO352.10 2.19 2.45 0.87 3.43 3.54 3.88 1.12
tPHL 2.32 2.39 2.59 0.66 3.28 3.37 3.65 0.91tPLH Propagation Delay,
DIN0-DIN35 to DO0-DO351.47 1.56 1.80 0.81 2.51 2.63 2.98 1.17
tPHL 2.11 2.18 2.39 0.70 3.03 3.11 3.37 0.87tPLH Propagation Delay,
RWB0-RWB35 to DO0-DO352.89 2.98 3.23 0.83 4.52 4.64 5.00 1.19
tPHL 2.94 3.01 3.23 0.72 4.40 4.48 4.72 0.80tr Output Rise Time, DO0-DO35 0.20 0.45 1.21 2.52 0.56 0.90 1.91 3.37tf Output Fall Time, DO0-DO35 0.62 0.71 0.97 0.86 1.35 1.43 1.65 0.73
RDB8X72tPLH Propagation Delay,
A0-A2 to DO0-DO712.28 2.36 2.61 0.84 3.82 3.93 4.26 1.11
tPHL 2.62 2.69 2.88 0.65 3.72 3.80 4.04 0.80tPLH Propagation Delay,
DIN0-DIN71 to DO0-DO711.48 1.56 1.80 0.81 2.52 2.64 2.99 1.17
tPHL 2.11 2.18 2.39 0.70 3.02 3.11 3.37 0.87tPLH Propagation Delay,
RWB0-RWB71 to DO0-DO713.44 3.52 3.76 0.81 5.38 5.49 5.83 1.12
tPHL 3.47 3.53 3.73 0.66 4.79 4.87 5.11 0.80tr Output Rise Time, DO0-DO71 0.37 0.61 1.31 2.33 0.67 0.97 1.87 3.00tf Output Fall Time, DO0-DO71 0.65 0.73 1.00 0.89 0.82 0.93 1.25 1.07
TIMING REQUIREMENTS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Abbr. Parameter8-WORD BLOCK5 V 3.3 V
tDSU
Set Up Time, DINA(n) to WBA (WL = 9) 0.28 0.53DINA(n) to WBA (WL = 18) 0.12 0.27DINA(n) to WBA (WL = 36) -0.05 -0.08DINA(n) to WBA (WL = 72) -0.47 -0.46
tAWB
Set Up Time, AA(n) to WBA (WL = 9) 0.02 -0.16AA(n) to WBA (WL = 18) 0.01 -0.27AA(n) to WBA (WL = 36) -0.23 -0.61AA(n) to WBA (WL = 72) -0.52 -0.94
tASU
Set Up Time, AA(n) to WBA (WL = 9) 4.00 5.01AA(n) to WBA (WL = 18) 4.22 5.28AA(n) to WBA (WL = 36) 4.65 5.90AA(n) to WBA (WL = 72) 5.06 6.56
tDH
Hold Time, WBA to DINA(n) (WL = 9) 0.87 1.28WBA to DINA(n) (WL = 18) 1.10 1.62WBA to DINA(n) (WL = 36) 1.41 2.14WBA to DINA(n) (WL = 72) 1.98 2.85
tDH
Hold Time, WBA to AA(n) (WL = 9) 0.66 1.10WBA to AA(n) (WL = 18) 0.82 1.35WBA to AA(n) (WL = 36) 1.14 1.87WBA to AA(n) (WL = 72) 1.61 2.44
tWP
Pulse Width WBA (L) (WL = 9) 1.97 3.00WBA (L) (WL = 18) 2.20 3.28WBA (L) (WL = 36) 2.62 3.93WBA (L) (WL = 72) 3.09 4.53
CMOS SWITCHING CHARACTERISTICS(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns. Rev. 1.09
Sym Parameter5.0 V 3.3 V
FO=0 FO=2 FO=8 K (ns/pF) FO=0 FO=2 FO=8 K (ns/pF)
Capacitance per fanout = 0.06 pF (metal capacitance is not included).
MACROCELL EXAMPLES (Continued)
H4CPlus_Series MOTOROLA
23
FUNCTIONAL DIAGRAM: of High Speed Dual-Port RAM
READ CYCLE High Speed Dual-Port RAM
WRITE CYCLE High Speed Dual-Port RAM
INPUTDRIVERS
MEMORYCELL
PORT A
DECODERADDRESS
OUTPUTDRIVERS
DINA(0-n) DOB(0-n)
ROW 0_B
ROW 1_B
ROW 0_A
WB0
ROW 1_A
WB1
MEMORYCELL
AA(0-m)
WBA
PORT B
DECODERADDRESS AB(0-m)
t AA
t OH
DOUTPrevious Data
AB(0-m)
DOB(0-n)
MACROCELL EXAMPLES (Continued)
t WP
t WDO
t AWB t AH
t AA
t DDO
t DH
Data at Read Address
WBA(0-n)
AA(0-m)
DINA(0-n)
DOB(0-n)
Write Address
Read Address
t DSU
Write Data
AB(0-m)
t ASU
MOTOROLA H4CPlus_Series
24
Table 7. Electrical Considerations for H4CPlus Series Arrays
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter VDD=3V/3.3V±0.3V VDD=5V±10% Unit
VDD DC Supply Voltage -0.5 to 4.6 -0.5 to 6.0 V
Vin DC Input Voltage -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 V
Vout DC Output Voltage -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 V
I DC Current Drain per Pin, Any Single Input or Output ±50 ±50 mA
I DC Current Drain per Pin, Any Paralleled Outputs ±100 ±100 mA
I DC Current Drain VDD and VSS Pins ±100 ±100 mA
Tstg Storage Temperature -65 to +150 -65 to +150 °CTL Lead Temperature (10 second soldering) 300 300 °C
Note: Maximum ratings are those values beyond which damage to the device may occur.
RECOMMENDED OPERATING CONDITIONS (to guarantee functionality)
Symbol Parameter Min Max Unit
VDD* DC Supply Voltage, VDD = 5.0V (Nominal) 4.5 5.5 V
VDD* DC Supply Voltage, VDD = 3.0/3.3V (Nominal) 2.7 3.6 V
* For testing, only. VDD range is wider for simulation purposes.
Notes:1. All parameters are characterized for DC conditions after thermal equilibrium has been established.2. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Vss or VDD).3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; how-ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated volt-ages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to therange VSS≤ (Vin or Vout)≤VDD.
H4CPlus DC ELECTRICAL CHARACTERISTICS
H4CPlus_Series MOTOROLA
25
Table 8. DC Electrical Characteristics for H4CPlus Series Arrays (T a = -40˚C to 85˚C)
Sym. Parameter ConditionVDD=3V/3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
VIH
Input High Voltage,CMOS Inputs (3.3V and 5V core) 2.0 VDD+0.3 0.7 VDD VDD+0.3
VTTL Inputs (5V core) 2.0 VDD+0.3 2.2* VDD+0.3
VIL
Input Low Voltage,CMOS Inputs (3.3V and 5V core) -0.3 0.8 -0.3 0.3 VDD
VTTL Inputs (5V core) -0.3 0.8 -0.3 0.8
VT+
Positive Threshold Voltage,CMOS Schmitt Trigger - 0.75VDD - 0.7VDD
VTTL Schmitt Trigger N/A N/A - 2.4
VT-
Negative Threshold Voltage,CMOS Schmitt Trigger 0.25VDD - 0.25VDD -
VTTL Schmitt Trigger N/A N/A 0.8 -
VHy
Hysteresis - CMOS Schmitt TriggerVT+ to VT-
0.1VDD 0.12VDD -V
Hysteresis - TTL Schmitt Trigger N/A N/A 0.05VDD -
IOH†
Output High Current,ON32 Output Type
VDD =Min,VOH Min= 0.8VDD
-24.0 - -48.0 -
mAON16 Output Type -12.0 - -24.0 -
ON8 Output Type -6.0 - -12.0 -
ON4 Output Type -3.0 - -6.0 -
ON2 Output Type -2.0 - -3.0 -
IOL
Output Low Current,ON32 Output Type
VDD =Min,VOL Max= 0.4 Volts
24 - 48.0 -
mAON16 Output Type 12 - 24.0 -
ON8 Output Type 6 - 12.0 -
ON4 Output Type 3 - 6.0 -
ON2 Output Type 2 - 3.0 -
VOH Output High Voltage, LVCMOS VDD = Min, IOH= -100µA OVDD3-0.2 - OVDD3-0.2 - V
VOL Output Low Voltage, LVCMOS VDD = Min, IOL= +100µA - 0.2 - 0.2 V
Iin
Input Leakage Current,No Pull Resistor
Vin = VDD or VSS -5 5 -5 5
µAwith Pullup Resistor PUL; Vin = VSS -5 -100 -10 -200
with Pulldown Resistor PDL; Vin = VDD 5 100 10 200
Ioz**
Output Leakage Current,3-State Output
Output = Off-State Vout = VDD or VSS
-10 10 -10 10µA
Output Leakage Current,Open Drain Output (Device Off)
Output = Off-StateVout = VDD
-10 10 -10 10
IDD Max Quiescent Supply CurrentIout = 0mAVin = VDD or VSS
Design Dependent mA
* VIH = 2.0V at VDD = 5V±5%** Single-Drive Output† For 3.3V ± 0.3 and 5V ±10%, only. For 2.7 V consult factory.N/A = Not Applicable
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
MOTOROLA H4CPlus_Series
26
Table 9. DC Electrical Characteristics for H4CPlus Series GTL Driver (T a = -40˚C to 85˚C)
Sym. Parameter ConditionsVDD= 3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
DC Characteristics for GTL Receivers
VIHInput High Voltage,GTL Inputs
-VVR08+0.10 VDD+0.30 VVR08+0.10 VDD+0.30 V
VILInput Low Voltage,GTL Inputs
--0.30 VVR08-0.10 -0.30 VVR08-0.10 V
VIDHMinimum Input High Voltage,GTL Differential Input
- - 100 - 100 mV
VIDLInput Low Voltage,GTL Differential Input
- - 100 - 100 mV
VICM
Input Common Mode VoltageRange, VCM min -
0.40- 0.6 - V
VCM max - 1.1 - 2.0 V
IIHInput High Current,GTL Input
Vin=VTT, VDD= Max - 5 - 5 µA
IILInput Low Current,GTL Inputs
Vin=0.4V, VDD= Max - -5 - -5 µA
VVR08 GTL Ref. Voltage - 0.68 0.90 0.68 0.90 V
IDD* Typical Quiescent Supply Current - - 1.3 - 3.8 mA
DC Characteristics for GTL Drivers
VOH*
Output High Voltage,20mA Output Macros
IOH=-10µA, VDD= Min VTT -0.05 VTT +0.05 VTT -0.05 VTT +0.05V
40mA Output Macros IOH=-10µA, VDD= Min VTT -0.05 VTT +0.05 VTT -0.05 VTT +0.05
VOL
Output Low Voltage,20mA Output Macros
IOL=20mA, VDD= 3 V - 0.4 - -V
40mA Output Macros IOL=40mA, VDD= 3 V - 0.4 - -
VOL
Output Low Voltage,20mA Output Macros
IOL=24mA, VDD= 4.5 V - - - 0.4V
40mA Output Macros IOL=48mA, VDD= 4.5 V - - - 0.4
VOD
Differential Output Voltage,20mA Output Macros
IOL=20mA VTT -0.45 - - -V
IOL=24mA - - VTT -0.45 -
IOZH GTL Output Off Current High Vout=1.2V, VDD= Max - 10 - 10 µA
IOZL GTL Output Off Current Low Vout=0.4V, VDD= Max - -10 - -10 µA
* Not tested.
Notes:1. Recommended: VTT = 1.2V ± 5%, VVR08 = (2/3) VTT, RT = 25Ω/50Ω, VTT MAX = VDD+0.3V
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
H4CPlus_Series MOTOROLA
27
Table 10. Electrical Characteristics for H4CPlus CMTL Buffers (T a = -40˚C to 85˚C)
Sym. Parameter ConditionsVDD= 3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
DC Characteristics for CMTL Receivers
VIDHMinimum Input High Voltage,CMTL Inputs (Differential)
- - 100 - 100 mV
VIDLMaximum Input Low Voltage,CMTL Inputs (Differential)
- - 100 - 100 mV
VICM
Input Common Mode VoltageRange, VICM Min
VDDmax 0.6 - 1.0 - V
VICM Max VDDmin - 2.2 - 3.5 V
IIHInput High Current,CMTL Inputs (No Termination)
Vin=VOHmax, VDD= Max - 5 - 5 µA
IILInput Low Current,CMTL Inputs (No Termination)
Vin=VOLmin, VDD=Max - 5 - 5 µA
IDD* Max Quiescent Supply Current - - 1.8 - 4.7 mA
DC Characteristics for CMTL Drivers
VOH
Minimum Output High Voltage,CMTL Outputs (no Load)**
VDD= Min
- - 2.5 3.7
VCMTL Outputs (50Ω)† 1.3 2.0 2.4 3.1
CMTL Outputs (100Ω)† 1.4 2.1 2.5 3.2
CMTL Outputs IOH=0.5mA N/A N/A - 3.5
VOL
Maximum Output Low Voltage,CMTL Outputs (no Load)**
VDD= Min
- - 1.0 2.0
VCMTL Outputs (50Ω)† 1.1 2.0 1.6 2.4
CMTL Outputs (100Ω)† 1.0 1.9 1.5 2.3
CMTL Outputs IOL=20mA N/A N/A 1.7 2.7
|VOD|
Differential Output Voltage,CMTL Outputs (no Load)** VDD= Min
- - 1.0 2.5
VCMTL Outputs (50Ω)† 0.19 Typ. 0.4 1.1
CMTL Outputs (100Ω)† 0.29 Typ. 0.5 1.4
VOS
Output Offset Voltage,CMTL Outputs (no Load)** VDD= Min
- - 2.1 2.6
VCMTL Outputs (50Ω)† 1.35 1.85 2.1 2.65
CMTL Outputs (100Ω)† 1.35 1.85 2.1 2.65
IOZH CMTL Output Off Current High Vout=VDD, VDD=Max -10 10 -10 10 µA
IOZL CMTL Output Off Current Low Vout=VSS, VDD=Max -10 10 -10 10 µA
Ro Output Impedance (Typical) 100Ω < Load < 200 Ω † 50 30 Ω
* Not tested.** OD32TCMT and BOD32TCMT macros, only.† Loads across differential CMTL outputs.N/A = Not Applicable
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
MOTOROLA H4CPlus_Series
28
Table 11. Electrical Characteristics for PECL Receivers (T a = -40˚C to 85˚C)
Sym. Parameter ConditionsVDD= 3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
DC Characteristics for PECL Receivers
VIHInput High Voltage,PECL Single-Ended
-VVR38+0.10 VDD+0.30 VVR38+0.10 VDD+0.30 V
VILInput Low Voltage,PECL Single-Ended
--0.30 VVR38-0.10 -0.30 VVR38-0.10 V
VIDHMinimum Input High Voltage,PECL Differential Input
- - 100 - 100 mV
VIDLInput Low Voltage,PECL Differential Input
- - 100 - 100 mV
VICM
Input Common Mode VoltageRange, VCM min -
1.2 - 1.4 - V
VCM max - VDD-0.8 - VDD-0.8 V
IIHInput High Current,PECL Input
Vin=VDD, VDD=Max - 5 - 5 µA
IILInput Low Current,PECL Input
Vin=VSS, VDD=Max - 5 - 5 µA
IDD* Max Quiescent Supply Current - - 1.5 (ILP-)5.3 (IPX-)
-4.3 (IPD)5.1 (IPN)
mA
VVR38 PECL Reference Voltage PECL Single-Ended VDD -1.3 Typ. VDD -1.3 Typ. V
* Not tested.
Table 12. DC Electrical Characteristics for H4CPlus Series PCI Buffers (T a = -40˚C to 85˚C)
Sym. Parameter ConditionVDD= 3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
DC Characteristics for PCI Receivers
VIH Input High Voltage 0.475VDD VDD+0.5 2.0 VDD+0.5 V
VIL Input Low Voltage -0.5 0.325VDD -0.5 0.8 V
IIH Input High Leakage Current3.3 V: 0<Vin<VDD5.0 V: Vin = 2.7 V
- 10 - 70 µA
IIL Input Low Leakage Current3.3 V: 0<Vin<VDD5.0 V: Vin = 0.5 V
- -10 - -70 µA
DC Characteristics for PCI Drivers
VOH Output High Voltage3.3 V: Iout = -500 µA5.0 V: Iout = -2 mA
0.9VDD - 2.4 - V
VOL Output Low Voltage3.3 V: Iout =1500 µA5.0 V: Iout = 6 mA
- 0.1VDD - 0.55 V
AC Characteristics for PCI Drivers (Not Tested)
VOHmin Output High Voltage Minimum3.3 V: Iout = -12(VDD)mA5.0 V: Iout = -44 mA
0.3VDD - 1.4 - V
VOHmax Output High Voltage Maximum3.3 V: Iout = -32(VDD)mA5.0 V: Iout = -142 mA
- 0.7VDD - 3.1 V
VOLmin Output Low Voltage Minimum3.3 V: Iout = 16(VDD) mA5.0 V: Iout = 95 mA
0.6VDD - 2.2 - V
VOLmax Output Low Voltage Maximum3.3 V: Iout = 38(VDD) mA5.0 V: Iout = 206 mA
- 0.18 VDD - 0.71 V
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
H4CPlus_Series MOTOROLA
29
*For the bidirectional extended voltage range I/O, the bidirectional input macro must be a 3.3V System and 3.3V Core macro.N/A = Not Applicable
Table 13. DC Electrical Characteristics for H4CPlus Series (T a = -40˚C to 85˚C)
Sym. Parameter ConditionVDD= 3.3V±0.3V
Guaranteed VDD=5V±10%Guaranteed Unit
Min. Max. Min. Max.
Leakage Current for Fail-Safe and Extended Voltage Range Bidirectional I/O
Ioff
Leakage Current for bidirectionalFail-Safe I/O,No pull resistor
VDD = OVDD5 = 0 to MAX Vin= VDD or VSSOutput = Off-State
N/A N/A -20 +20
µALeakage Current for bidirectionalFail-Safe I/O,with pulldown resistor
VDD = OVDD5 = 0 to MAX Vin= VDD or VSSOutput = Off-State
N/A N/A -20 +200
Ioff*
Leakage Current for bidirectionalextended voltage range I/O,No pull resistor
VDD = OVDD3 = 0 to MAX Vin= 0 to 5.5 VOutput = Off-State
-20 +20 N/A N/A
µALeakage Current for bidirectionalextended voltage range I/O,with pulldown resistor
VDD = OVDD3 = 0 to MAX Vin= 0 to 5.5 VOutput = Off-State
-20 +200 N/A N/A
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H4CP/D
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