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Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of2 27
TS-7800-V2
TS-7800-V2 Standard Options
TS-7800-V2-DMN1I Marvell Armada 385 1.33 GHz ARM Cortex A9 1G DDR3 RAM, 4GB eMMC Flash, Temp Sensor, Real Time Clock, Full-Duplex RS-485(-40C to 85C) Option 1
Option 2
Option 3
TS-7800-V2-DMW2I Marvell Armada 385 1.33 GHz ARM Cortex A9 1G DDR3 RAM and 4GB eMMC Flash, WiFi, Temp Sensor, Real Time Clock, Full-Duplex RS-485(-40C to 85C)
Optional Components/Features SummaryAll Parts are Industrial Temp
ADD: U26
Accelerometer Option
ADD: CN44, P1, P2
mini-PCIe/mSATA Option
Included only on xxx3x Standard Option
Included only on xxWxx Standard Options
WiFi/Bluetooth Option
ADD: K2 (chip antenna). U37
w/ Chip AntennaU.FL available on request
(alternate: U.FL antenna connector)
Included only on xxx3x Standard Option
REMOVE: CN10, HD2
CPU Heat SinkIncluded on ALL Standard Options
ADD: Alpha Novatech S08CHL0A
Available AccesoriesIncluded on NO Standard Options
TS-781 "8-28V Power daughter board"
Compatable ONLY with xxx1x, xxx2x Standard Option
TS-7800-V2-DMW3I Marvell Armada 385 1.33 GHz ARM Cortex A9 1G DDR3 RAM, 4GB eMMC Flash, mPCIe, WiFi, Accelerometer, Temp Sensor, RTC, Full-Duplex RS-485(-40C to 85C)
1N
C
XOPP1
ASSEMBLY_OPTIONS
Rev.P2 --> Rev.A Changes:
Added new RTC (U41 = M41T00) on I2C bus
Add PD on MPP_10 (R57) - this disables clocks on MPP_45 and 46
Removed D7, connected SYS_RESET# to Silab pin 32
CN44 (Mini-PCIe) pin 22 needs to use DIO (use CPU_TYPE_1)
Change "CPU_TYPE_1" to be biased low (R46) to indicate Rev.A
PTP Ethernet timing will not be supported
Moved SATA Conn (CN10) away from PC/104 Conn 0.3mm
Made FPGA_RESET longer = 680 ms
Web Schematic: Some proprietary information has been withheld.
A
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of2 27
TS-7800-V2
TS-7800-V2 Block Diagram
A
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
4 27
CPU DDR
512 MB
DDR3 RAM
H3M_DQ[0]
H2M_DQ[1]
H1M_DQ[2]
J1M_DQ[3]
L2M_DQ[4]
L1M_DQ[5]
K2M_DQ[6]
L3M_DQ[7]
C1M_DQ[8]
B1M_DQ[9]
A4M_DQ[10]
C2M_DQ[11]
C4M_DQ[12]
A3M_DQ[13]
B2M_DQ[14]
B4M_DQ[15]
C7M_DQ[16]
B6M_DQ[17]
A6M_DQ[18]
C6M_DQ[19]
C9M_DQ[20]
B9M_DQ[21]
A9M_DQ[22]
B8M_DQ[23]
M2M_DQ[24]
M3M_DQ[25]
P2M_DQ[26]
N2M_DQ[27]
R3M_DQ[28]
R2M_DQ[29]
T2M_DQ[30]
U2M_DQ[31]
D1M_CB[0]
E3M_CB[1]
E2M_CB[2]
F3M_CB[3]
G2M_CB[4]
H4M_CB[5]
G4M_CB[6]
E1M_CB[7]
J2M_DQS[0]
J3M_DQSn[0]
B3M_DQS[1]
A2M_DQSn[1]
B7M_DQS[2]
A7M_DQSn[2]
P1M_DQS[3]
R1M_DQSn[3]
F2M_DQS[4]
F1M_DQSn[4]
M1M_DM[0]
D2M_DM[1]
B5M_DM[2]
U1M_DM[3]
H5M_DM[4]
B15M_A[0]
C15M_A[1]
E13M_A[2]
B13M_A[3]
D15M_A[4]
A13M_A[5]
B16M_A[6]
D16M_A[7]
C16M_A[8]
E14M_A[9]
D11M_A[10]
D14M_A[11]
E12M_A[12]
B14M_A[13]
E15M_A[14]
E10M_A[15]
C13M_BA[0]
A16M_BA[1]
A15M_BA[2]
D13M_CSn[0]
C17M_CSn[1]
D12M_ODT[0]
B11M_ODT[1]
C12M_WEn
E11M_RASn
B12M_CASn
E9M_RESETn
A12M_CKE[0]
C10M_CKE[1]
B10M_CLKOUT[0]
A10M_CLKOUTn[0]
D10M_CLKOUT[1]
D9M_CLKOUTn[1]
E5M_PCAL[0]
F5M_NCAL[0]
A17M_PCAL[1]
B17M_NCAL[1]
D18M_PCAL[2]
D17M_NCAL[2]
U7-A
CPU_MARVELL_88F6820
C174.1 uF
C172.1 uF
C166.1 uF
C170.1 uF
C177.1 uF
C178.1 uF
C179.1 uF
C180.1 uF
C181.1 uF
C186.1 uF
C171.1 uF
R105240
C167.1 uF
C175.1 uF
Twin
Die
N3A0
P7A1
P3A2
N2A3
P8A4
P2A5
R8A6
R2A7
T8A8
R3A9
L7A10
R7A11
N7A12
T3A13
M2BA0
N8BA1
M3BA2
J7CK
K7CK#
K9CKE
L2CS#
D3UDM
J3RAS#
K3CAS#
L3WE#
B2VDD0
D9VDD1
D2VDDQ3
H1VREF_DQ
T7A14
H9VDDQ7
K1ODT
E3DQ0
F7DQ1
F2DQ2
F8DQ3
H3DQ4
H8DQ5
G2DQ6
H7DQ7
C7UDQS
B7UDQS#
L8ZQ
A1VDDQ0
R1VDD7
T2RESET#
E2VSSQ4
G7VDD2
D8VSSQ3
D1VSSQ2
A8VDDQ1
B9VSSQ1
B1VSSQ0
J2VSS4
G8
VSS3
E1
VSS2
B3
VSS1
A9
VSS0
K2VDD3
K8VDD4
N1VDD5
J8VSS5
M1
VSS6
M9
VSS7
P1
VSS8
P9
VSS9
T9
VSS11
T1
VSS10
M8VREF_CA
J1TWIN_ODT1
J9TWIN_SDCKE1
L1TWIN_CS1#
L9TWIN_ZQ1
M7A15/NC
N9VDD6
R9VDD8
D7DQ8
C3DQ9
C8DQ10
C2DQ11
A7DQ12
A2DQ13
B8DQ14
A3DQ15
F3LDQS
G3LDQS#
E8VSSQ5
E9VDDQ4
F1VDDQ5
F9VSSQ6
G9VSSQ8
H2VDDQ6
E7LDM
G1VSSQ7
C1VDDQ2
C9VDDQ8
U23
RAM_DDR3_X16_96BALL_4GBIT_ITEMP
R18
931
R20
931
R21
931
R22
931
R23
931
R24
931
C190.1 uF
C191.1 uF
C199.1 uF
RAM_1.35V
RAM_D[00:39]
RAM_D09
RAM_D15
RAM_D08
RAM_D14
RAM_D12
RAM_D11
RAM_DQS2_P
RAM_DQS2_M
RAM_DQM2
RAM_DQM1
RAM_DQS1_P
RAM_DQS1_M
RAM_ODT0
RAM_RESET#
RAM_BA0
RAM_BA1
RAM_BA2
RAM_CLK_P
RAM_CLK_M
RAM_CKE0
RAM_CS0#
RAM_RAS#
RAM_CAS#
RAM_WE#
RAM_1.35V
RAM_D13
RAM_D10
RAM_D16
RAM_D23
RAM_D19
RAM_D22
RAM_D18
RAM_D21
RAM_D17
RAM_D20
RAM_VREF
RAM_A[00:15]
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_A14
RAM_A15
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_A14
RAM_A15
RAM_BA0
RAM_BA1
RAM_BA2
RAM_CS0#
RAM_ODT0
RAM_WE#
RAM_RAS#
RAM_CAS#
RAM_RESET#
RAM_CKE0
RAM_CLK_P
RAM_CLK_M
RAM_D[00:39]
RAM_D00
RAM_D01
RAM_D02
RAM_D03
RAM_D04
RAM_D05
RAM_D06
RAM_D07
RAM_D08
RAM_D09
RAM_D10
RAM_D11
RAM_D12
RAM_D13
RAM_D14
RAM_D15
RAM_D16
RAM_D17
RAM_D18
RAM_D19
RAM_D20
RAM_D21
RAM_D22
RAM_D23
RAM_D24
RAM_D25
RAM_D26
RAM_D27
RAM_D28
RAM_D29
RAM_D30
RAM_D31
RAM_DQS0_P
RAM_DQS0_M
RAM_DQS1_P
RAM_DQS1_M
RAM_DQS2_P
RAM_DQS2_M
RAM_DQS3_P
RAM_DQS3_M
RAM_DQM0
RAM_DQM1
RAM_DQM2
RAM_DQM3
RAM_1.35V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 5 27
TS-7800-V2
512 MB
DDR3 RAM
C162.1 uF
C163.1 uF
C160.1 uF
C159.1 uF
C158.1 uF
C157.1 uF
C155.1 uF
C154.1 uF
C153.1 uF
C156.1 uF
C152.1 uF
C151.1 uF
C150.1 uF
Die
Twin
N3A0
P7A1
P3A2
N2A3
P8A4
P2A5
R8A6
R2A7
T8A8
R3A9
L7A10
R7A11
N7A12
T3A13
M2BA0
N8BA1
M3BA2
J7CK
K7CK#
K9CKE
L2CS#
D3UDM
J3RAS#
K3CAS#
L3WE#
B2VDD0
D9VDD1
D2VDDQ3
H1VREF_DQ
T7A14
H9VDDQ7
K1ODT
E3DQ0
F7DQ1
F2DQ2
F8DQ3
H3DQ4
H8DQ5
G2DQ6
H7DQ7
C7UDQS
B7UDQS#
L8ZQ
A1VDDQ0
R1VDD7
T2RESET#
E2VSSQ4
G7VDD2
D8VSSQ3
D1VSSQ2
A8VDDQ1
B9VSSQ1
B1VSSQ0
J2VSS4
G8
VSS3
E1
VSS2
B3
VSS1
A9
VSS0
K2VDD3
K8VDD4
N1VDD5
J8VSS5
M1
VSS6
M9
VSS7
P1
VSS8
P9
VSS9
T9
VSS11
T1
VSS10
M8VREF_CA
J1TWIN_ODT1
J9TWIN_SDCKE1
L1TWIN_CS1#
L9TWIN_ZQ1
M7A15/NC
N9VDD6
R9VDD8
D7DQ8
C3DQ9
C8DQ10
C2DQ11
A7DQ12
A2DQ13
B8DQ14
A3DQ15
F3LDQS
G3LDQS#
E8VSSQ5
E9VDDQ4
F1VDDQ5
F9VSSQ6
G9VSSQ8
H2VDDQ6
E7LDM
G1VSSQ7
C1VDDQ2
C9VDDQ8
U24
RAM_DDR3_X16_96BALL_4GBIT_ITEMP
R106240
C142.1 uF
C140.1 uF
C144.1 uF
RAM_1.35V
RAM_D[00:39]
RAM_D28
RAM_D25
RAM_D29
RAM_D31
RAM_D24
RAM_D30
RAM_DQS0_P
RAM_DQS0_M
RAM_DQM0
RAM_DQM3
RAM_DQS3_P
RAM_DQS3_M
RAM_ODT0
RAM_RESET#
RAM_BA0
RAM_BA1
RAM_BA2
RAM_CLK_P
RAM_CLK_M
RAM_CKE0
RAM_CS0#
RAM_RAS#
RAM_CAS#
RAM_WE#
RAM_D26
RAM_D27
RAM_D06
RAM_D03
RAM_D07
RAM_D00
RAM_D04
RAM_D02
RAM_D05
RAM_D01
RAM_VREF
RAM_A[00:15]
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_A14
RAM_A15
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
A 7 27
CPU Misc
25 MHz Osc.
CPU JTAG
Tag-Connect
NC
To SiLab ?
PD
PU
PU
PU
PD
PU
CPU LEDs
CPU
NC
NC
W1JT_CLK
U3JT_RSTn
V1JT_TDI
W2JT_TDO
R4JT_TMS_CORE
V2JT_TMS_CPU
Y2CDRn
R5MRn
T4SYSRST_INn
U4SYSRST_OUTn
A19REF_CLK_XIN
A18REF_CLK_XOUT
R16RTC_ALARMn
Y19RTC_XIN
Y18RTC_XOUT
J16ISET
G15RSVD_NC
H15RSVD_NC
F16RSVD_SENSE
J17RSVD_TP
U7-B
CPU_MARVELL_88F6820GND
VCC
3
2
1
4
5
6
U20
NC7WZ14P6X_SC70
C230
27 pF
C231
27 pF
OSC
6XOUT
3GND
1XIN
2CLK1
4CLK0
5VDD
7PGND
U10
XTAL_BUFF_PL135-27_DFN6L
Y2
25 MHz
FB11
600 ohm
C388.1 uF
4JTAG_TCK
6JTAG_TDO
2JTAG_TMS
13.3V
8JTAG_TDI
10CPU_RESET#
9NC/TRST#
3GND
7NC
5GND/5V
CN77
JTAG_10PIN_TC2050_SMT
R63
6.04K
7 2RN26-B
3.3K
6
3
RN26-C3.3K
R79
51
C1041 uF
C332
.1 uF
1
2LED4
GRN1
2LED2
RED
R107240
R108240
1.8V
3.3V
PHY_25MHZ_1.8V
3.3V
CPU_JTAG_TMS
CPU_JTAG_TCK
CPU_JTAG_TDO
CPU_JTAG_TDI
CPU_RESET#
3.3V
CPU_RESET#
3.3V
CPU_JTAG_TCK
CPU_JTAG_TDI
CPU_JTAG_TDO
CPU_JTAG_TMS
FPGA_25MHZ_CLK
CPU_JTAG_RST#
CPU_JTAG_RST#
SYS_RESET#
3.3V
RED_LED#
GRN_LED#
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
A 8 27
CPU SerDes
CPU SERDES
PCIe 2
100 MHz
Differential
Clocks
PCIe
SATA
or
to FPGA
USB 3
USB 3
SATA
CN11
USB 2.0
only lanes 3 and 5
USB3 can use
6810
on single core
Not present
D19SRD0_RX_P
D20SRD0_RX_N
C19SRD0_TX_P
C20SRD0_TX_N
E19SRD1_RX_P
E20SRD1_RX_N
F19SRD1_TX_P
F20SRD1_TX_N
H20SRD2_RX_P
H19SRD2_RX_N
G19SRD2_TX_P
G20SRD2_TX_N
J20SRD3_RX_P
J19SRD3_RX_N
K20SRD3_TX_P
K19SRD3_TX_N
M20SRD4_RX_P
M19SRD4_RX_N
L20SRD4_TX_P
L19SRD4_TX_N
N20SRD5_RX_P
N19SRD5_RX_N
P20SRD5_TX_P
P19SRD5_TX_N
L17PCIe0_CLK_P
L16PCIe0_CLK_N
M17PCIe1_CLK_P
M16PCIe1_CLK_N
T19USB0_DP
T20USB0_DM
U19USB1_DP
U20USB1_DM
V19USB2_DP
V20USB2_DM
U7-C
CPU_MARVELL_88F6820
R8451
R8551
R8651
R8751
MINI_CLK_P
MINI_CLK_M
MINI_SATA0_RX_P
MINI_SATA0_RX_M
MINI_SATA0_TX_P
MINI_SATA0_TX_M
PEX_2_RX_P
PEX_2_RX_M
PEX_2_TX_P
PEX_2_TX_M
USB2_D2_P
USB2_D2_M
USB2_D1_P
USB2_D1_M
USB2_0_P
USB2_0_M
USB3_RX1_P
USB3_RX1_M
USB3_TX1_P
USB3_TX1_M
FPGA_CLK_P
FPGA_CLK_M
USB3_RX0_P
USB3_RX0_M
USB3_TX0_P
USB3_TX0_M
SATA1_RX_P
SATA1_RX_M
SATA1_TX_P
SATA1_TX_M
Jan. 20, 2018
A
Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
9 27
CPU I/O
eMMC
2nd E
th R
GM
II
CPU DIO
PD
PU
PU
PD
PD
PD
PU
PU
PU
PU
PU
PD
PD
PU
PD
PU
PU
PU
PD
PU
PU
PD
PU
PD
PU
PU
PU
PD
PD
PU
PU
PD
None
PU
PU
None
PU
PD
PD
PU
PD
PD
PU
PU
PD
PD
PD
PD
Console
Eth RGMII
PU
PU
W3MPP[0]
Y3MPP[1]
W4MPP[2]
Y4MPP[3]
W5MPP[4]
V4MPP[5]
Y7MPP[6]
V7MPP[7]
W7MPP[8]
V6MPP[9]
Y6MPP[10]
W6MPP[11]
U6MPP[12]
T7MPP[13]
T5MPP[14]
U5MPP[15]
U7MPP[16]
T6MPP[17]
W8MPP[18]
U8MPP[19]
T8MPP[20]
U10MPP[21]
V12MPP[22]
Y12MPP[23]
W12MPP[24]
W11MPP[25]
T13MPP[26]
Y10MPP[27]
V10MPP[28]
W10MPP[29]
V9MPP[30]
Y9MPP[31]
W9MPP[32]
U13MPP[33]
T12MPP[34]
U12MPP[35]
V13MPP[36]
T10MPP[37]
T11MPP[38]
T9MPP[39]
U9MPP[40]
U11MPP[41]
W13MPP[42]
Y13MPP[43]
U14MPP[44]
W14MPP[45]
Y15MPP[46]
T14MPP[47]
U15MPP[48]
W17MPP[49]
T15MPP[50]
U16MPP[51]
W16MPP[52]
W15MPP[53]
T16MPP[54]
Y16MPP[55]
U17MPP[56]
V16MPP[57]
V15MPP[58]
T17MPP[59]
U7-D
CPU_MARVELL_88F6820
2
7
RN29-B3.3K
3
6
RN29-C3.3K
4 5RN29-D
3.3K
R25
931
1 8RN29-A
3.3K
R54
2.0K
R91
51
R47
2.0K
R57
2.0K
UART0_TXD
I2C_0_CLK
I2C_0_DAT
MPP4_GE_MDC
MPP5_GE_MDIO
MPP6_GE_TXCLK
MPP7_GE_TXD0
MPP8_GE_TXD1
MPP9_GE_TXD2
MPP10_GE_TXD3
MPP11_GE_TXCTL
MPP12_GE_RXD0
MPP13_GE_RXD1
MPP14_GE_RXD2
MPP15_GE_RXD3
MPP16_GE_RXCTL
MPP17_GE_RXCLK
SPI_0_MOSI
SPI_0_CLK
SPI_0_MISO
SPI_0_BOOT_CS0#
SPI_0_WIFI_CS2#
EMMC_D2
EMMC_D1
EMMC_CLK
EMMC_D0
EMMC_D3
EMMC_CMD
3.3V
3.3V
CPU_IRQ
EN_USB_HOST_5V
SPI_0_CS3#
DETECT_9478
WIFI_IRQ#
UART0_RXD
CPU_TYPE_1
ACCEL_2_INT
FPGA_FLASH_SELECT
3.3V
GE_PHY_INT#
EN_FAN
DETECT_9478
CPU_SPEED_1
CPU_SPEED_2
CPU_SPEED_0
CPU_SPEED_3
CPU_SPEED_4
CPU_TYPE_0
SPREAD_SPECTRUM#
DETECT_MSATA
EN_EMMC_PWR
MPP10_GE_TXD3
3.30V typ
3.3V Reg.
1.38V typ
DDR3 1.35V Reg.
L5
2.2 uH
>1.6V = On
EN
<0.4V = Off
2.7-5.5V
0.8V
4VIN
3
5SW
9PGND
7FB
6RT
1COMP
PGOOD8
2SS
U14
REG_SW_4A_RT8070_DFN8
FB21
220 ohm
C24310 uF
R124287K
C5910 nF
C97560 pF
R29
36.5K
R3414.7K
R1564.99K
C8047 uF
L3
1.5 uH
>1.6V = On
EN
<0.4V = Off
2.7-5.5V
0.8V
4VIN
3
5SW
9PGND
7FB
6RT
1COMP
PGOOD8
2SS
U13
REG_SW_4A_RT8070_DFN8
FB20
220 ohm
C24210 uF
R125287K
C4510 nF
C96560 pF
R151
10.7K
R15210.7K
R3514.7K
C8147 uF C79
47 uF
1.35V
R19931
3.3V
SW_5V
PWR_GOOD
3.3V
SW_5V
PWR_GOOD
RAM_1.35V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
A 12 27
Ethernet PHY
10/100/1000 Marvell 88E1512 PHY
Strapped for PHY
address = 1
NC
NC
NC
NC
NC
NC
Gig MagJack
Link / Activity
Left LED (Green)
NC
46RX_CLK
43RX_CTRL
44RXD[0]
45RXD[1]
47RXD[2]
48RXD[3]
53TX_CLK
56TX_CTRL
50TXD[0]
51TXD[1]
54TXD[2]
55TXD[3]
7MDC
8MDIO
15CONFIG
9CLK125
16RESETn
34XTAL_IN
33XTAL_OUT
27MDIN[0]
28MDIP[0]
23MDIN[1]
24MDIP[1]
21MDIN[2]
22MDIP[2]
17MDIN[3]
18MDIP[3]
2S_INN
1S_INP
5S_OUTN
4S_OUTP
14LED[0]
13LED[1]
12LED[2]_INTn
30RSET
31HSDACN
32HSDACP
29TSTPT
U25-A
PHY_ETH_88E1512
R1554.99K
C122.1 uF
R103
240
R111
240
Left
8
7
5
4
6
3
2
1
POE
POE
Shield
Alignment
Pegs
POE
POE
11
12
10
4
6
5
3
1
2
8
7
9
22
19
18
20
17
23
24
13
14
21
15
16
T1
MAGJACK_GIG_POE
C121.1 uF
C120.1 uF
C119.1 uF
5
4
RN28-D3.3K
3 6RN28-C
3.3K
2 7RN28-B
3.3K
R100
240
R1331.62 ohm
1
2
5VCC
4
3GND
U6
DNP
18RN28-A
3.3K
3.3V
MPP5_GE_MDIO
MPP4_GE_MDCMDI_0_P
MDI_0_M
MDI_1_P
MDI_1_M
MDI_2_P
MDI_2_M
MDI_3_P
MDI_3_M
GE_PHY_INT#
PHY_25MHZ_1.8V
3.3V
ETH_ACT_LINK_LED#
MPP11_GE_TXCTL
MPP6_GE_TXCLK
MPP10_GE_TXD3
MPP9_GE_TXD2
MPP8_GE_TXD1
MPP7_GE_TXD0
MPP12_GE_RXD0
MPP13_GE_RXD1
MPP14_GE_RXD2
MPP15_GE_RXD3
MPP16_GE_RXCTL
MPP17_GE_RXCLK
ETH_ACT_LINK_LED#
ETH_RIGHT_LED#
MDI_0_P
MDI_0_M
MDI_1_P
MDI_1_M
MDI_2_P
MDI_2_M
MDI_3_P
MDI_3_M
3.3V
PHY_1512_RESET#
ETH_RIGHT_LED#
PTP FRAME
3.3V
SYS_RESET#
3.3V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
A 13 27
MSEL2 high = Fast POR
Cyclone
SPI FlashFPGA MUX
FPGA JTAG
Tag-Connect
Conn.
2 MB
IN
OUT
A4IO_B9_DATA0
B4IO_B9_ASDO
C5IO_B9_NCSO
D5DCLK_B9
C4nCONFIG_B9
D3nCE_B9
U4CONF_DONE_B3
V4nSTATUS_B3
D4TDI_B9
E5TCK_B9
E3TMS_B9
E4TDO_B9
P4MSEL2_B3
R5MSEL1_B3
T5MSEL0_B3
U3NC
V3NC
U8-C
ALTERA_CYCLONE_IV_EP4CGX22CF19C8N
1CS#
5DIN_DQ0
6CLK 8
VCC
4GND
7HOLD#_DQ3
3WP#_DQ2
2DOUT_DQ1
U19
FLASH_IS25LQ016B_2MB_SOIC8
C145.1 uF
R92
51
R75
475
1SEL_A#
15OE#
2A0
3B0
5A1
6B1
11A2
10B2
14A3
13B3
16VCC
4Z0
7Z1
9Z2
12Z3
8GND
U45
74LVC257_TSSOP16
C76
10 nF
GND
VCC
2
3
4
1
5
U33
NC7SZ125P5X_SC70
C67
10 nF
8
1
RN24-A3.3K
7
2
RN24-B3.3K
4JTAG_TCK
6JTAG_TDO
2JTAG_TMS
13.3V
8JTAG_TDI
10CPU_RESET#
9NC/TRST#
3GND
7NC
5GND/5V
CN88
JTAG_10PIN_TC2050_SMT
4 5RN8-D
10K
3 6RN8-C
10K
8 1RN39-A
51
2 7RN39-B
51
5 4RN39-D
51
6 3RN39-C
51
R522.0K
8
1
RN26-A3.3K
3 6
RN10-C
10K
1
8
RN10-A10K
D
S
G5
3
4
Q13-B
3.3V
3.3V
3.3V
FIL_2.5V
FPGA_JTAG_TDO
FPGA_JTAG_TDI
FPGA_JTAG_TCK
FPGA_JTAG_TMS
FPGA_FLASH_CS#
3.3V
SPI_0_MISO
SPI_0_CLK
SPI_0_MOSI
SPI_0_CS3#
CPU_ACCESS_FPGA_FLASH#
3.3V
2.5V
FPGA_JTAG_TMS
FPGA_JTAG_TCK
FPGA_JTAG_TDO
FPGA_JTAG_TDI
2.5V
FPGA_SPI_CS#
FPGA_SPI_CLK
FPGA_SPI_MOSI
3.3V
FPGA_SPI_MISO
EXT_SBC_RESET
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet of
TS-7800-V2
A 14 27
FPGA DIO
100 MHz
Clock
145 DIOMUX #2
Console
MUXed
Inputs
Shift Reg + Latch
Shift Reg # 1
Shift Reg + Latch
SR #2
SD Card
MUX Bias
+ 16 MUX In
+ 16 SR Out
Provides 5V Tolerance
To SR
T15IO_B4_RDN2
U16IO_B4_DIFFIO_B18n
V16IO_B4_DIFFIO_B19p
U15IO_B4_DIFFIO_B18p
V13IO_B4_DIFFIO_B12n
U13IO_B4_DIFFIO_B12p
V14IO_B4_DIFFIO_B15p
V15IO_B4_DIFFIO_B15n
C10IO_B8_DIFFIO_T9n
A9IO_B8_DIFFIO_T5p
B9IO_B8_DIFFIO_T7n
A8IO_B8_DIFFIO_T5n
A7IO_B8_DIFFIO_T4n
C7IO_B8_DIFFIO_T3n
A6IO_B8_DIFFIO_T2n
B6IO_B8_DIFFIO_T2p
T16IO_B4_DIFFIO_B21p
V18IO_B4_DIFFIO_B20n
U18IO_B4_DIFFIO_B20p
P18IO_B5_DIFFIO_R12n
N18IO_B5_DIFFIO_R10n
M18IO_B5_DIFFIO_R8p
J16IO_B6_DIFFIO_R7p
G18IO_B6_DIFFIO_R6nDEV_OE
F18IO_B6_DIFFIO_R4p
E18IO_B6_DIFFIO_R4nDEV_CLRn
D16IO_B7_DIFFIO_T19p
C16IO_B7_PLL4_CLKOUTn
B5IO_B8_PLL2_CLKOUTp
A16IO_B7_DIFFIO_T15n
B15IO_B7_DIFFIO_T16n
A14IO_B7_DIFFIO_T13n
D12IO_B7_DIFFIO_T12p
B13IO_B7_DIFFIO_T11p
A10IO_B8_DIFFIO_T8n
N6IO_B3_PLL1_CLKOUTn
P15IO_B4_PLL3_CLKOUTp
U12IO_B4_DIFFIO_B14n
R11IO_B4_DIFFIO_B13p
R12IO_B4_DIFFIO_B16p
T8IO_B3
R7IO_B3_DIFFIO_B4p
T10IO_B3_DIFFIO_B10p
V10IO_B3_DIFFIO_B9n
T9IO_B3_DIFFIO_B8n
C9IO_B8_DIFFIO_T6n
N7IO_B3_DIFFIO_B5n
B7IO_B8_DIFFIO_T4p
V17IO_B4_DIFFIO_B19n
E6IO_B8_CLKUSR
D6IO_B8_DIFFIO_T1p
A5IO_B8_PLL2_CLKOUTn
M7IO_B3_DIFFIO_B5p
V7IO_B3_DIFFIO_B6n
U7IO_B3_DIFFIO_B6p
U9IO_B3_DIFFIO_B7p
V9IO_B3_DIFFIO_B9p
C6IO_B8_DIFFIO_T1n
V11CLK14_B4_DIFFCLK_6p
G9CLK10_B8A_DIFFCLK_4n_REFCLK1n
V12CLk15_B4_DIFFCLK_6n
R13IO_B4_DIFFIO_B16n
R10IO_B3_DIFFIO_B11n
G10CLK11_B8A_DIFFCLK_4p_REFCLK1p
K17CLK5_B5_DIFFCLK_2p
K18CLK4_B5_DIFFCLK_2n
J18CLK7_B6_DIFFCLK_3p
H18CLK6_B6_DIFFCLK_3N
R14IO_B4_RUP2
T13IO_B4_DIFFIO_B17p
A12CLK8_B7_DIFFCLK_5n
N5IO_B3_PLL1_CLKOUTp
M9CLK12_B3A_DIFFCLK_7p_REFCLK0p
M10CLK13_B3A_DIFFCLK_7n_REFCLK0n
T17IO_B4_DIFFIO_B21n
R16IO_B5_DIFFIO_R14p
R18IO_B5_DIFFIO_R12p
N17IO_B5_DIFFIO_R10p
M17IO_B5_DIFFIO_R11n
K16IO_B5_DIFFIO_R9n
H16IO_B6
G16IO_B6_DIFFIO_R5p
F16IO_B6_DIFFIO_R2p
D17IO_B6_DIFFIO_R3p
C17IO_B7_PLL4_CLKOUTp
B18IO_B7_RDN4
A18IO_B7_DIFFIO_T18p
A17IO_B7_DIFFIO_T18n
C15IO_B7_DIFFIO_T16p
C14IO_B7_DIFFIO_T17n
B16IO_B7_DIFFIO_T15p
A15IO_B7_DIFFIO_T13p
C13IO_B7_DIFFIO_T14p
A13IO_B7_DIFFIO_T11n
C12IO_B7_DIFFIO_T14n
D11IO_B7_DIFFIO_T12n
A11IO_B8_DIFFIO_T8p
T18IO_B5_DIFFIO_R13n
R17IO_B5_DIFFIO_R13p
N16IO_B5_RDN3
M16IO_B5_DIFFIO_R11p
L18IO_B5_DIFFIO_R8n
J17IO_B6_DIFFIO_R7n
G17IO_B6_DIFFIO_R5n
F17IO_B6_DIFFIO_R6p
D18IO_B6_DIFFIO_R3n
C18IO_B7_RUP4
L15IO_B5
L16IO_B5_VREFB5N0
G15IO_B6_VREFB6N0
F15IO_B6_DIFFIO_R1p
E16IO_B6_DIFFIO_R2n
E15IO_B6_DIFFIO_R1n
D15IO_B7_DIFFIO_T19n
D14IO_B7_DIFFIO_T17p
D13IO_B7
E12IO_B7_VREFB7N0
P12IO_B4_VREFB4N0
R15IO_B4_PLL3_CLKOUTn
V6IO_B3_DIFFIO_B3n
P6IO_B3_DIFFIO_B1p_CRC_ERROR
R8IO_B3_VREFB3N0
T14IO_B4_DIFFIO_B17n
N15IO_B5_RUP3
T11IO_B4_DIFFIO_B13n
P10IO_B3_DIFFIO_B11p
T12IO_B4_DIFFIO_B14p
R9IO_B3_DIFFIO_B8p
P16IO_B5_DIFFIO_R14n
R6IO_B3_DIFFIO_B1n_NCEO
U6IO_B3_DIFFIO_B2n
V8IO_B3_DIFFIO_B7n
B10IO_B8_DIFFIO_T7p
D7IO_B8_DIFFIO_T3p
T6IO_B3_DIFFIO_B2p
B12CLK9_B7_DIFFCLK_5p
D9IO_B8_DIFFIO_T6p
E10IO_B7_DIFFIO_T10p
C8IO_B8
D8IO_B8_VREFB8N0
C11IO_B8_DIFFIO_T9p
D10IO_B7_DIFFIO_T10n
T7IO_B3_DIFFIO_B4n
U10IO_B3_DIFFIO_B10n
V5IO_B3_DIFFIO_B3p_INIT_DONE
K15IO_B5_DIFFIO_R9p
P13IO_B4
U8-B
ALTERA_CYCLONE_IV_EP4CGX22CF19C8N
D
S
G2
6
1
Q4-A
1SEL_A#
15OE#
2A0
3B0
5A1
6B1
11A2
10B2
14A3
13B3
16VCC
4Z0
7Z1
9Z2
12Z3
8GND
U46
74LVC257_TSSOP16
C48
10 nF
13OE#
12REG_CLK
10CLEAR#
11SER_CLK
14SER_DIN
15Q0
1Q1
2Q2
3Q3
4Q4
5Q5
6Q6
7Q7
9SER_D7
8GND
16VCC
U35
74AHC595PW_TSSOP16
C185
.1 uF
13OE#
12REG_CLK
10CLEAR#
11SER_CLK
14SER_DIN
15Q0
1Q1
2Q2
3Q3
4Q4
5Q5
6Q6
7Q7
9SER_D7
8GND
16VCC
U34
74AHC595PW_TSSOP16
C176
.1 uF
4 5RN9-D
10K
TP8
2 7RN20-B
2.2K
3 6RN20-C
2.2K
4 5RN20-D
2.2K
R153
4.99K
2
7
RN10-B10K
ISA_DATA_[00:15]
FPGA_CLK_M
FPGA_CLK_P
WIFI_32KHZ
COM1_TXD
FPGA_SILAB_CLK#
COM3_TXD
CPU_RESET#
ISA_A[01:31]
ISA_C[01:10]
ISA_D[01:17]
ISA_B[04:30]
BUF_LCD_[03:14]
BUF_DIO_[01:15]DIO_SPI_CLK
MUX_2
COM1_DCD_5V
COM1_CTS_5V
COM3_CTS_5V
3.3V
SER_DATA
COM1_DSR_5V
DETECT_9478
SYS_RESET#
WIFI_CTS
MUX_0
MUX_1
MUX_2
MUX_3
SER_LATCH
SER_CLK
SER_DATA
RED_LED#
GRN_LED#
COM1_RTS
COM1_DTR
COM3_RTS
WIFI_RTS
WIFI_RESET#
EN_WIFI_PWR
3.3V
FAN_RPM
3.3V SR_TRI_STATE
SER_DATA
SER_CLK
SER_LATCH
SD_D0
PHY_1512_RESET#
LCD_04
EN_SD_PWR
ISA_RESET
CPU_IRQ
FPGA_SILAB_DATA
DIO_SPI_CS#
CPU_ACCESS_FPGA_FLASH#
3.3V
3.3V SR_TRI_STATE
SER_CLK
SER_LATCH
WIFI_TXD
SR_TRI_STATE
U_BOOT_JMP# MUX_1
MUX_2
USE_7800_BOOT_FLASH
BUF_IRQ10
BUF_IRQ5
CAN_TXD
COM2_RXD_3V
COM3_RXD_3V
DIO_SPI_MOSI
EN_MUX_1#
FPGA_25MHZ_CLK
I2C_0_CLK
MUX_0
MUX_1
MUX_3
SD_CLK
SD_CMD
SD_D1
SD_D2
SD_D3
SER_LATCH
SILAB_TXD
TXD1_485
TXD2_485
UART0_RXD
UART0_TXD WIFI_RXD
FPGA_RESET
TXEN1_485
TXEN2_485
PTP
BUF_SPI_MISO
CAN_RXD_3V
COM1_RXD_3V
COM2_TXD
I2C_0_DAT
RXD1_485_3V
RXD2_485_3V
ISA_DATA_00
ISA_DATA_01
ISA_DATA_02
ISA_DATA_03
ISA_DATA_04
ISA_DATA_05
ISA_DATA_06
ISA_DATA_07
ISA_DATA_08
ISA_DATA_09
ISA_DATA_10
ISA_DATA_11
ISA_DATA_12
ISA_DATA_13
ISA_DATA_14
ISA_DATA_15
ISA_B04
ISA_B06
ISA_B08
ISA_B11
ISA_B12
ISA_B13
ISA_B14
ISA_B15
ISA_B16
ISA_B17
ISA_B18
ISA_B19
ISA_B20
ISA_B24
ISA_B25
ISA_B26
ISA_B27
ISA_B28
ISA_B30
BUF_LCD_03
BUF_LCD_05
BUF_LCD_06
BUF_LCD_07
BUF_LCD_08
BUF_LCD_09
BUF_LCD_10
BUF_LCD_11
BUF_LCD_12
BUF_LCD_13
BUF_LCD_14
ISA_A01
ISA_A10
ISA_A11
ISA_A12
ISA_A13
ISA_A14
ISA_A15
ISA_A16
ISA_A17
ISA_A18
ISA_A19
ISA_A20
ISA_A21
ISA_A22
ISA_A23
ISA_A24
ISA_A25
ISA_A26
ISA_A27
ISA_A28
ISA_A29
ISA_A30
ISA_A31
ISA_C01
ISA_C02
ISA_C03
ISA_C04
ISA_C05
ISA_C06
ISA_C07
ISA_C08
ISA_C09
ISA_C10
ISA_D01
ISA_D02
ISA_D09
ISA_D10
ISA_D11
ISA_D12
ISA_D13
ISA_D14
ISA_D15
ISA_D17
BUF_DIO_01
BUF_DIO_03
BUF_DIO_04
BUF_DIO_05
BUF_DIO_07
BUF_DIO_08
BUF_DIO_09
BUF_DIO_11
BUF_DIO_13
BUF_DIO_15
MUX_0SD_BOOT_JMP#
MUX_3EN_CONSOLE_JMP#
3.3V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 17 27
TS-7800-V2
Option 3 =
Accelerometer
C138.1 uF
C137.1 uF4
SCL
6SDA
8NC
5GND
10GND
12GND
11INT1
9INT2
7I2C_LSB
2CAP
1VDIO
16NC
15NC
13NC
3DNC
14VDD
U26
DNP
Accelerometer MMA8451
R56
2.0K
I2C_0_CLK
I2C_0_DAT
3.3V
ACCEL_2_INT
CPU_SPEED_0
Cyclone
Transceivers
B2TX3_P_GXB
B1TX3_M_GXB
D2RX3_P_GXB
D1RX3_M_GXB
F2TX2_P_GXB
F1TX2_M_GXB
H2RX2_P_GXB
H1RX2_M_GXB
K2TX1_P_GXB
K1TX1_M_GXB
M2RX1_P_GXB
M1RX1_M_GXB
P2TX0_P_GXB
P1TX0_M_GXB
T2RX0_P_GXB
T1RX0_M_GXB
U8-A
ALTERA_CYCLONE_IV_EP4CGX22CF19C8N
C197
.1 uF
C198
.1 uF
4
5
RN10-D10K
C390
.1 uF
C389
.1 uF
PEX_2_RX_M
PEX_2_RX_P
PEX_2_TX_M
PEX_2_TX_P
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 18 27
TS-7800-V2
Dual Host USB 3.0 USB 3.0 Ports 0 & 1
USB 2.0 Ports 1 & 2
NC
NC
NC
NC
Jumpers
ST Micro RTC
Top
Dual A
USB 3.0
4GND
1VBUS
2DAT-
3DAT+
5SSRX-
6SSRX+
7GND
8SSTX-
19FRAME
20FRAME
21FRAME
22FRAME
9SSTX+
18SSTX+
17SSTX-
16GND
15SSRX+
14SSRX-
12DAT+
11DAT-
10VBUS
13GND
CN3
CONN_USB_3_DUAL_RA
1
2
3
6
5
4
TVS6
CHOKE_TVS_USB3_ECMF022HSMX6_SMT
1
2
3
6
5
4
TVS15
TVS_USB2_NUP4114_SC88
FB28
220 ohm
FB29
220 ohm
C123.1 uF
1
2
3
6
5
4
TVS9
CHOKE_TVS_USB3_ECMF022HSMX6_SMT
1
2
3
6
5
4
TVS7
CHOKE_TVS_USB3_ECMF022HSMX6_SMT
1
2
3
6
5
4
TVS8
CHOKE_TVS_USB3_ECMF022HSMX6_SMT
C124
.1 uF
C116
.1 uF
C165
.1 uF
C118
.1 uF
1 2
JP1-A
HD_2X3_2.54MM_JUMP
3 4
JP1-B
HD_2X3_2.54MM_JUMP
5 6
JP1-C
HD_2X3_2.54MM_JUMP
1 8RN9-A
10K
2 7RN9-B
10K
3 6RN9-C
10K
6SCL
5SDA
1XIN
2XOUT
8VCC
7OUT
3BAT
4GND
U41
M41T00S_RTC_SOIC8
R77475
21
3 4
K1
C101
1 uF
12 pF
1 4
2 3
Y1
XTAL_32KHZ_SMT
1
2
3
D5
USB2_D2_M
USB2_D2_P
USB2_D1_M
USB2_D1_P
USB_HOST_5V
USB3_RX1_P
USB3_RX1_M
VDD_5V_USB3
VDD_5V_USB3
VDD_5V_USB3
VDD_5V_USB3
GND_USB3
GND_USB3
GND_USB3
GND_USB3
GND_USB3
USB3_RX0_M
USB3_RX0_P
USB3_TX0_M
USB3_TX0_P
USB3_TX1_P
USB3_TX1_M
FRAME
SD_BOOT_JMP#
EN_CONSOLE_JMP#
U_BOOT_JMP#
3.3V
3.3V
3.3V
I2C_0_CLK
I2C_0_DAT
3.3V
Jan. 20, 2018
TS-7800-V2
Technologic Systems Date
Title:
Rev: Designer Sheet ofA 19 27
PC/104 64-pin Connector
PC/104 40-pin Connector
50 lines directly into FPGA
plus 3 more read only:
29 lines directly into FPGA (bi-directional)
FETs provide 5V tolerance
provides 5V tolerance
Warning:All IRQs and data lines
are 5V tolerant, but
all other signals must
use 3.3V levels
IRQ3 and 4 must be 3.3V levels
(IRQ6, IRQ7 and ISA_32)
IRQ11 thru IRQ15 are read only
MUX #1
Provides 5V Tolerance
ISA_RESET is output only
A1IOCHK#
A2D7
A3D6
A4D5
A5D4
A6D3
A7D2
A8D1
A9D0
A10IORDY
A11AEN
A12A19
A13A18
A14A17
A15A16
A16A15
A17A14
A18A13
A19A12
A20A11
A21A10
A22A9
A23A8
A24A7
A25A6
A26A5
A27A4
A28A3
A29A2
A30A1
A31A0
A32GND
B1GND
B2RESET
B3+5V
B4IRQ9
B5-5V
B6DRQ2
B7-12V
B8ENDX#
B9+12V
B10(KEY)
B11MEMW#
B12MEMR#
B13IOW#
B14IOR#
B15DACK3#
B16DRQ3
B17DACK1#
B18DRQ1
B19RFRSH#
B20BCLK
B21IRQ7
B22IRQ6
B23IRQ5
B24IRQ4
B25IRQ3
B26DACK2#
B27TC
B28BALE
B29+5V
B30OSC
B31GND
B32GND
6566
CN5
PC104_64-PIN_SHORT
D0GND
D1MEM16#
D2IO16#
D3IRQ10
D4IRQ11
D5IRQ12
D6IRQ15
D7IRQ14
D8DACK0#
D9DRQ0
D10DACK5#
D11DRQ5
D12DACK6#
D13DRQ6
D14DACK7#
D15DRQ7
D16+5V
D17MASTER#
D18GND
D19GND
C0GND
C1SBHE#
C2LA23
C3LA22
C4LA21
C5LA20
C6LA19
C7LA18
C8LA17
C9MEMR#
C10MEMW#
C11SD8
C12SD9
C13SD10
C14SD11
C15SD12
C16SD13
C17SD14
C18SD15
C19GND/KEY
CN6
PC104_40PIN_SHORT
23EN_FET#
2A0
3A1
4A2
5A3
6A4
7A5
8A6
9A7
10A8
11A9
24VCC
1NC
22B0
21B1
20B2
19B3
18B4
17B5
16B6
15B7
14B8
13B9
12GND
U42
QS3861_QSOP24
2
7
RN14-B2.2K
1
8
RN14-A2.2K
3 6RN12-C
2.2K
4 5RN12-D
2.2K
5 4RN14-D
2.2K
6
3
RN14-C2.2K
1SEL_A#
15OE#
2A0
3B0
5A1
6B1
11A2
10B2
14A3
13B3
16VCC
4Z0
7Z1
9Z2
12Z3
8GND
U47
74LVC257_TSSOP16
C49
10 nF
1
MT1
MT125 1
MT2
MT125
C50
10 nF
C51
10 nF
2
7
RN12-B2.2K
1
8
RN12-A2.2K
1 8RN20-A
2.2K
72RN7-B
10K
G
S D
2
61
Q9-A
G
S D
5
34
Q9-BG
S D
2
61
Q10-A
G
S D
5
34
Q10-B
G
S D
2
61
Q11-A
G
S D
5
34
Q11-B
G
S D
2
61
Q12-A
G
S D
5
34
Q12-B
G
S D
2
61
Q13-A
SW_5V
SW_5V
ISA_B[04:32]
ISA_A[01:31]
SW_5V
4.3V
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
ISA_DATA_[00:15]
ISA_DATA_[00:15]
3.3V
ISA_D[01:17]
ISA_C[01:10]
3.3V
IRQ7
IRQ6
IRQ5
8V_30V
ISA_A10
ISA_A31
3.3V
3.3V
ISA_D09
ISA_B32
IRQ5
LCD_14
IRQ14
IRQ12
IRQ7
3.3V
SER_DATA
IRQ6
IRQ15
IRQ11
ISA_B32
MUX_0
MUX_1
MUX_2
MUX_3
ISA_RESET
SD_WP
BUF_IRQ5
EN_MUX_1#
ISA_A01
ISA_B04
ISA_B06
ISA_B08
ISA_B11
ISA_B12
ISA_B13
ISA_B14
ISA_B15
ISA_B16
ISA_B17
ISA_B18
ISA_B19
ISA_B20
ISA_B24
ISA_B25
ISA_B26
ISA_B27
ISA_B28
ISA_B30
ISA_A11
ISA_A12
ISA_A13
ISA_A14
ISA_A15
ISA_A16
ISA_A17
ISA_A18
ISA_A19
ISA_A20
ISA_A21
ISA_A22
ISA_A23
ISA_A24
ISA_A25
ISA_A26
ISA_A27
ISA_A28
ISA_A29
ISA_A30
ISA_C01
ISA_C02
ISA_C03
ISA_C04
ISA_C05
ISA_C06
ISA_C07
ISA_C08
ISA_C09
ISA_C10
ISA_DATA_08
ISA_DATA_09
ISA_DATA_10
BUF_LCD_14ISA_DATA_11
ISA_DATA_12
ISA_DATA_13
ISA_DATA_14
ISA_DATA_15
ISA_D01
ISA_D02
ISA_D10
ISA_D11
ISA_D12
ISA_D13
ISA_D14
ISA_D15
ISA_D17
3.3V
3.3V
3.3V
4.3V
ISA_DATA_00
ISA_DATA_01
ISA_DATA_03
ISA_DATA_04
4.3V
IRQ10BUF_IRQ10
ISA_DATA_07
ISA_DATA_05
ISA_DATA_02
ISA_DATA_06
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 20 27
TS-7800-V2
Option 3 =Option 2 =Option 1 =
Option 1 =Option 2 =Option 3 =
LCD Port
LCD07 thru LCD14 are always open
drain outputs, initialized to high
LCD04 is always output
active high-low, init to zero
LCD03, LCD05, LCD06 init to inputs
when outputs, active high-low
These are programmable I/O
All LCD lines are 5V tolerant
They can be used as inputs
Pull-up resistors for
the open drain outputs
current thru resistor
sink 8 mA, but only source
Open drain outputs can
provides 5V tolerance
Shift Reg + Latch
SiLab SR
Res. Straps
Option
Strap
Indicates Rev.A
CPU Straps
4 Res. Straps
for Board
Config
R43R42 R44R45
0 10 0
Resistor Strapping Table1 = POP, 0 = DNP
MSB LSB
Option 1
Option 3
TS-7800-V2-DMN1I
0 00 1 Option 2 TS-7800-V2-DMW2I
0 10 1 TS-7800-V2-DMW3I
R89
51R76
475
4 5RN13-D
2.2K
3 6RN13-C
2.2K
4 5RN16-D
2.2K
3 6RN16-C
2.2K
2 7RN13-B
2.2K
2 7RN16-B
2.2K
1 8RN13-A
2.2K
1 8RN16-A
2.2K
14D6
12D4
10D2
8D0
6WR#
4BIAS
2GND
11D5
9D3
7D1
5EN
3RS
15V
13D7
CN7
HD_2X7_2.54MM_LCD
23EN_FET#
2A0
3A1
4A2
5A3
6A4
7A5
8A6
9A7
10A8
11A9
24VCC
1NC
22B0
21B1
20B2
19B3
18B4
17B5
16B6
15B7
14B8
13B9
12GND
U43
QS3861_QSOP24
C52
10 nF
13OE#
12REG_CLK
10CLEAR#
11SER_CLK
14SER_DIN
15Q0
1Q1
2Q2
3Q3
4Q4
5Q5
6Q6
7Q7
9SER_D7
8GND
16VCC
U36
74AHC595PW_TSSOP16
C115
.1 uF
R44
DNP2.0k
2.0k
R45
DNP
R42
DNP
R43
DNP2.0k
2.0k
R58
6.04K
R59
6.04K
R60
6.04K
R46
2.0K
SW_5V
LCD_[03:14]
LCD_[03:14]
LCD_08
LCD_07
LCD_11
LCD_12
LCD_09
LCD_13
LCD_10
LCD_14
3.3V
LCD_13
LCD_11
LCD_09
LCD_07
LCD_05
LCD_03
LCD_14
LCD_12
LCD_10
LCD_08
LCD_06
LCD_[03:14]
4.3V
BUF_LCD_[03:14]
LCD_03
LCD_05
LCD_06
LCD_08
LCD_07
LCD_10
LCD_09
LCD_12
LCD_11
LCD_13
BUF_LCD_08
LCD_04
BUF_LCD_03
BUF_LCD_05
BUF_LCD_06
BUF_LCD_07
BUF_LCD_10
BUF_LCD_09
BUF_LCD_12
BUF_LCD_11
BUF_LCD_13
CPU_SPEED_0
CPU_SPEED_1
CPU_SPEED_2
CPU_SPEED_3
CPU_SPEED_4
CPU_TYPE_0
CPU_TYPE_1
3.3V
3.3V
3.3V CPU_SPEED_1
CPU_SPEED_3
CPU_SPEED_2
3.3V CPU_SPEED_4
SPREAD_SPECTRUM#
CPU_TYPE_1
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 21 27
TS-7800-V2
DIO
Port
open drain outputs, initialized to high
DIO_01 thru DIO_15 (odds) are always
They are programmable In or out
when output, active high-low
DIO_04 and DIO_08 initialize to inputs
SPI_MISO is 5V tolerant
SPI_MOSI, CLK, and Frame
are 3.3V level outputs
They can be used as inputs
All DIO lines are 5V tolerant
provides 5V tolerance
CAN Transceiver
24V
16
14
12
10
8
6
4
2
15
13
11
9
7
5
3
1
CN8
HD_2X8_7800
18RN15-A
2.2K
27RN15-B
2.2K
36RN15-C
2.2K
45RN15-D
2.2K
18RN17-A
2.2K
27RN17-B
2.2K
36RN17-C
2.2K
45RN17-D
2.2K
4 5RN31-D
51
3 6RN31-C
51
2 7RN31-B
51
1 8RN31-A
51
4 5RN32-D
51
3 6RN32-C
51
2 7RN32-B
51
1 8RN32-A
51
1
2
3
6
5
4
TVS13
TVS_USB2_NUP4114_SC88
1
2
3
6
5
4
TVS14
TVS_USB2_NUP4114_SC88
23EN_FET#
2A0
3A1
4A2
5A3
6A4
7A5
8A6
9A7
10A8
11A9
24VCC
1NC
22B0
21B1
20B2
19B3
18B4
17B5
16B6
15B7
14B8
13B9
12GND
U44
QS3861_QSOP24
4RXD
1TXD
5VREF
8EN#
3VCC
7CANH
6CANL
2GND
U49
TJA1050_SOIC
C161.1 uF
21
3
TVS17
NUP2105L_SOT23
C141.1 uF
3
6
RN27-C3.3K
4
5
RN27-D3.3K
R104
240
R102
240
3
6
RN11-C10K
3.3V
DIO_SPI_CLK
DIO_SPI_MISO
DIO_SPI_CS#
DIO_[01:15]
3.3V
DIO_04
DIO_08
3.3V
DIO_15
DIO_01
DIO_03
DIO_05
DIO_07
DIO_09
DIO_11
DIO_13
4.3V BUF_DIO_[01:15]
DIO_01
DIO_03
DIO_04
DIO_05
DIO_07
DIO_08
DIO_09
DIO_11
DIO_13
DIO_15
SW_5V
CAN_RXD_5V
CAN_H
CAN_L
CAN_TXD
DIO_SPI_MOSI
BUF_DIO_01
BUF_DIO_03
BUF_DIO_04
BUF_DIO_05
BUF_DIO_07
BUF_DIO_08
BUF_DIO_09
BUF_DIO_11
BUF_DIO_13
BUF_DIO_15
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 22 27
TS-7800-V2
COM1
COM2
RS-232 Transceiver
RS-485 Drivers
Header
DB9M
Header
COM3
COM1
Level shifter
3.3V <-- 5V
RS-232 Transceiver
DB-9M
6TX-_(DSR)
4RX+_(DTR)
9RX-_(RI)
1TX+_(DCD)
3TXD
7RTS
5GND
2RXD
8CTS
11FRAME2
10FRAME1
CN9
CONN_DB9M_RA_TH
C184.1 uF
C183.1 uF
C134.1 uF
C133.1 uF
T4
T3
R5
R4
R3
V-
V+
Vcc
GND
C2-
C2+
C1-
C1+
R2
R1
T2
T1
1213
14
15
16
17
3
25SD#
24EN_RX
6
7
22 23
2
10
11
20
21
8
5
26
19 18
27
4
9
28
1
U48
SP213_SOIC28
V-
V+
Vcc
GND
C2-
C2+
C1-
C1+
R2
R1
T2
T1
1
2
3
4
5
6
7
89
10
11
12 13
14
15
16
U9
SP202_SOIC16
C196.1 uF
C139.1 uF
C194.1 uF
C195.1 uF
6TX-_(DSR)
4RX+_CANH_(DTR)
9RX-_CANL_(RI)
1TX+_(DCD)
3TXD
7RTS
5GND
2RXD
8CTS
10NC
HD5
HD_COM_2X5_2.54MM
6485_TX+
4485_RX+
9485_RX-
1485_TX-
3TXD
7RTS
5GND
2RXD
8CTS
10NC
HD3
HD_COM_7800_2X5_2.54MM
4TXD
1RXD
3TXEN
2RXEN#
8VCC
6X+
7X-
5GND
U18
SP485EEN_SOIC8
4TXD
1RXD
3TXEN
2RXEN#
8VCC
6X+
7X-
5GND
U17
SP485EEN_SOIC8
C192.1 uF
8.5V
1 2
3
TVS4
TVS_8.5V_DUAL_SOT23
8.5V
1 2
3 TVS5
TVS_8.5V_DUAL_SOT23
5
4
RN19-D2.2K
8
1
RN25-A3.3K
7
2
RN25-B3.3K
3
6
RN25-C3.3K
4
5
RN25-D3.3K
19OE
1DIR
2A1
3A2
4A3
5A4
18B1
17B2
16B3
15B4
6A5
7A6
8A7
9A8
14B5
13B6
12B7
11B8
20VCC
10GND
U30
74LVC245_TSSOP20
1
8
RN19-A2.2K
6
3
RN19-C2.2K
2
7
RN19-B2.2K
C147.1 uF
C146.1 uF
1
2
TVS19
6V
1
2
TVS18
6V
1
2
TVS20
6V
1
2
TVS21
6V
R1321.62 ohm
R31
DNP
R32
DNP
CPU_RESET#
SW_5V
COM1_TXD
COM2_232_RXD
COM2_232_TXD
COM2_232_TXD
COM2_232_RXD
COM1_DTR
COM1_RTS
COM1_DCD_5V
COM1_DSR_5V
COM1_CTS_5V
RXD1_485_5V
TXEN1_485
RXD2_485_5V
COM3_CTS_5V
COM3_RXD_5V
COM3_RTS
COM3_TXD
SW_5V
TXEN2_485
SW_5V
SW_5V
FRAME
3.3V
RXD2_485_5V
CAN_RXD_5V
RXD1_485_5V
COM3_RXD_5V
CAN_H
CAN_L
DIO_SPI_MISO
COM2_RXD_3V
COM3_RXD_3V
TXD1_485
TXD2_485
BUF_SPI_MISO
CAN_RXD_3V
COM1_RXD_3V
COM2_TXD
RXD1_485_3V
RXD2_485_3V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 23 27
TS-7800-V2
eMMC 4GOptionally up to 64GB
Micro SD Card Socket
Full-Size SD Card Socket
SD Card and USB Power Switch
eMMC 3.3V switch
C173.1 uF
C387.1 uF
C187.1 uF
C382.1 uF
C381.1 uF
C188.1 uF
C1071 uF
A3DATA_0
A4DATA_1
A5DATA_2
B2DATA_3
M6CLK
M5COMMAND
E6VCC
P6GND
P4GND
N5GND
N2GND
K8GND
H10GND
E7GND
C4GND
F5VCC
J10VCC
K9VCC
C6VCCQ
P3VCCQ
N4VCCQ
P5VCCQ
B3DATA_4
B4DATA_5
B5DATA_6
B6DATA_7
K5RESET#
C2VDD_I
G5GND
M4VCCQ
A6TOSH_GND
J5TOSH_GND
U21
EMMC_MICRON_4GB_BG153_ITEMP
C189
.1 uF
7DATA_0
8DATA_1
1DATA_2
2DATA_3
5CLK
3COMMAND
4VDD
6GND
10FRM2
9FRM1
11FRM3
12FRM4
CN14
CONN_MICRO_SD
3
6
RN6-C10K
1
8
RN6-A10K
4
5
RN6-D10K
7DATA_0
8DATA_1
9DATA_2
1DATA_3
5CLK
2COMMAND
4VDD
10CARD_DET#
12WP_SW
13FRAME
11COMMON
3GND
6GND
CN2
CONN_SD_FULL_SIZE_OST
C42
10 nF
6VDD
3EN_FET1
2EN_FET2
7GND
4DRAIN_1
5SOURCE_1
8SOURCE_2
1DRAIN_2
U29
SLG_DUAL_FET_SW_SMT8
C148
.1 uF
2 7RN43-B
47K
3 6RN43-C
47K
2
7
RN6-B10K
5 4RN43-D
47K
18RN43-A
47K
6VDD
3EN_FET1
2EN_FET2
7GND
4DRAIN_1
5SOURCE_1
8SOURCE_2
1DRAIN_2
U28
SLG_DUAL_FET_SW_SMT8
2 7RN44-B
47K
3 6RN44-C
47K
54RN44-D
47K
18RN44-A
47K
C336.1 uF
EMMC_3.3V
EMMC_D3
EMMC_D2
EMMC_D1
EMMC_D0
EMMC_CLK
EMMC_3.3V
EMMC_CMD
SD_D3
SD_CMD
SD_CLK
SD_D1
SD_D2
SD_3.3V
SD_3.3V
SD_WP
SD_D0
SD_D1
SD_D2
SD_D3
SD_CMD
SD_CLK
USB_HOST_5V
SD_3.3V
SW_5V
EN_SD_PWR 3.3V
SW_5V
EN_USB_HOST_5V
3.3V
SD_D0
EMMC_3.3V
SW_5V
EN_EMMC_PWR
3.3V3.3V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 24 27
TS-7800-V2
Option 3 =
Option 3 =
Option 3 =
7mm Stack Height
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SATA 0
to center of bd.
SATA 1
CPU DIO = PCIe Reset#
PCIe / mSATA mSATA / PCIe
/ RESERVED
/ RESERVED
/ RESERVED
/ RESERVED
/ RESERVED
/ RESERVED
/ RESERVED
/ RESERVED
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
RESERVED /
3.3v /
GND /
1.5V /
/ GND
/ GND
GND /
/ GND
/ +B 3.3V /
/ -B GND /
/ GND 1.5V /
/ GND TW_CLK /
/ -A TW_DATA /
/ +A GND /
/ GND
/ GND
/ 3.3V
/ 3.3V
GND /
/ NC (mSATA SEL)
/ VENDOR
/ VENDOR 1.5 /
/ DA/DSS
/ PRESENCE DECTION
GND /
3.3V /
1WAKE#
3COEX1
5COEX2
7CLK_REQ#
9GND
11REF_CLK-
13REF_CLK+
15GND
17UIM_C8
19UIM_C4
21GND
23PE_RX-
25PE_RX+
27GND
29 GND
31PE_TX-
33PE_TX+
35GND
37 GND
39 3.3V_AUX
413.3V_AUX
43GND
45 RESERVED
47RESERVED
49RESERVED
51RESERVED
23.3V_AUX
4GND
61.5V
8UIM_PWR
10UIM_DATA
12UIM_CLK
14UIM_RESET
16UIM_VPP
18GND
20DISABLE#
22PE_RST#
243.3V_AUX
26GND
281.5V
30SMB_CLK
32SMB_DATA
34GND
36USB_D-
38USB_D+
40GND
42LED_WWAN#
44LED_WLAN#
46LED_WPAN#
481.5V
50GND
523.3V
53TAB_GND
55MNT_HOLE
54TAB_GND
56MNT_HOLE
CN44
DNP
mini-PCIe Socket
C43
10 nF
C44
10 nF
C46
10 nF
C47
10 nF
1GND
4GND
7GND
6RX+
5RX-
3TX-
2TX+
9FRM
8FRM
CN10
CN_SATA_VERT_TH
DNP
PEM
P1
DNP
6mm PEM Standoff
PEM
P2
DNP
1GND
4GND
7GND
6RX+
5RX-
3TX-
2TX+
9FRM
8FRM
CN11
CN_SATA_VERT_TH
C53
10 nF
C63
10 nF
C64
10 nF
C65
10 nF
1
2
3
D3
6
3
RN7-C10K
R55
2.0K
MINI_SATA0_RX_P
MINI_SATA0_RX_M
MINI_SATA0_TX_M
MINI_SATA0_TX_P
3.3V
3.3V
CPU_TYPE_1
USB2_0_M
USB2_0_P
MINI_CLK_P
MINI_CLK_M
SATA1_TX_P
SATA1_TX_M
SATA1_RX_M
SATA1_RX_P
DETECT_MSATA
1.8V
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 25 27
TS-7800-V2
Option 3 =Option 2 =
Option 2 =Option 3 =
Regulator
3.74V typ
WiFi 3.6V
Radio Module
WiFi / Blutooth
SPI Buffers
C25110 uF
0.8V
0.3V = L
1000 mA2.2-6V
1.0V = H
8VIN 1
VOUT
4GND
5EN
3FB
6NC
2NC
7NC
9PAD
U37
LDO 1000 mA
DNP
LDO AP7361 ADJLDO AP7361 ADJ
R532.0K
Out
Out
Out
18VBAT
28GND
33IRQ#
36GND
8BT_TXD
34I2C_SCL
35I2C_SDA
10BT_RTS 12
VDD_IO
1GND1
27SDIO_D3
26SDIO_D2
25SDIO_D1
24SDIO_D0
23SDIO_CMD
22SDIO_CLK
5NC
6NC
4NC
3NC
14GPIO_3
15GPIO_4
2MODE_SDIO#
16UART_TXD
17UART_RXD
7RESET#
13GND2
11BT_CTS
9BT_RXD
30GPIO_18
32GPIO_20
29GPIO_17
31GPIO_19
20RTC_CLK
19CHIP_EN
37PAD
21GND3
K2
DNP
Microchip 3000 Chip AntennaMicrochip 3000 Chip Antenna
C25210 uF
C143.1 uF
R626.04K
R3614.7K
R512.0K
R81
51
GND
VCC
2
3
4
1
5
U32
NC7SZ125P5X_SC70
R80
51
GND
VCC
2
3
4
1
5
U31
NC7SZ125P5X_SC70
R78
51
SW_5V WIFI_3.6V
WIFI_3.6V
3.3V
EN_WIFI_PWR
WIFI_RESET#
WIFI_CTS
WIFI_RTS
SPI_0_MISO
SPI_0_WIFI_CS2#
SPI_0_MOSI
SPI_0_CLK
3.3V
WIFI_32KHZ
WIFI_IRQ#
WIFI_TXD
CN99_SPI_MOSI
3.3V
SPI_0_MOSI
WIFI_RXD
CN99_SPI_CLK
3.3V
SPI_0_CLK
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 26 27
TS-7800-V2
Option 3 =
5V Power In
Interface to TS-781 Buck Reg.
For Optional 8V-28V Power In
Main 5V Power Sw.
FB26
220 ohm
1+
2-
CN4
CONN_PWR_2POS_5MM
1
3
5
2
4
6
HD2
HD_2X3_2.54MMDNP
G
SD
N-Channel
Boost
Buffer
3DRAIN
4DRAIN
1VDD
7CAP
2ON
8GND
5SOURCE
6SOURCE
U16
FET_SW_CUR_LIMIT_TDFN8
C54
10 nF
C126.1 uF
D
S
G2
6
1
Q6-A
D
S
G5
3
4
Q6-B
R109240
4
5
RN42-D47K
2 7RN42-B
47K
D
S
G2
6
1
Q5-A
GND
VCC
3
2
1
4
5
6
U15
NC7WZ14P6X_SC70
D
S
G5
3
4
Q5-B
C257
10 uF
R120
115K
R90
51
C99
220uF
FB27
220 ohm
D
S
G2
6
1
Q7-A
D
S
G5
3
4
Q7-B
1FAN_-
3RPM
2FAN_+
CN1
DNP
1 8RN7-A
10K
D
S
G2
6
1
Q8-A
3
6
RN24-C3.3K
1
2
3
D1
R129
1.62 ohm
D
S
G5
3
4
Q8-B
18RN42-A
47K
R1604.99K
8V_30V
5V_A
SW_5V
5V_A
5V_A
DETECT_9478
3.3V
3.3V
5V_A
FPGA_RESET
SW_5V
EN_FAN
3.3V
EXT_SBC_RESET#
FAN_RPM
EXT_SBC_RESET
Jan. 20, 2018Technologic Systems Date
Title:
Rev: Designer Sheet ofA 27 27
TS-7800-V2
USB Device Port and SiLab uC
USB
Scale = 5.3%
A/D full scale = 2.50V
I2C
USB Device
Scale = 44%
SiLab LED
Micro Port
5 Channel 10-bit A/D - 5V full scale
DIO_04 can be Wakeup
R131
1.62 ohm
FB6
600 ohmC149.1 uF
C193.1 uF
C25510 uF
SiLabs
A/D
8USB_VBUS
5USB_DM
4USB_DP
7PWR_IN
U22
SILAB_C8051F381_QFN32
C125.1 uF
C25310 uF
C25410 uF
2
3
1
U40
R73
475
R136
10.7K
R13710.7K
SiL_3.3V
R139
10.7K
R14110.7K
5 4RN18-D
2.2K
R121
42.2K
R3036.5K
R14810.7K
FB9
600 ohm
1
2
3
6
5
4
TVS12
TVS_USB2_NUP4114_SC88
D
S
G5
3
4
Q4-B
1 8RN18-A
2.2K
3 6RN18-C
2.2K
R101240
1
2LED3
Green
SiLab
Micro B
5GND
15V
2D-
3D+
7FRM
6FRM
4SENSE
9FRM
8FRM
CN12
CONN_USB_MICRO-B_RA
1
2
3
D4
R127
287K
R3714.7K
1 3 5 7 9
2 4 6 8 10
HD4
R142
10.7K
R14310.7K
R144
10.7K
R14510.7K
R146
10.7K
R14710.7K
12R138
10.7K
R14010.7K
R12242.2K
4
5
RN26-D3.3K
1 8RN11-A
10K
27RN11-B
10K
4 5RN11-D
10K
R3914.7K
USB_SILAB_M
USB_SILAB_P
SILAB_3.3V
USB_SILAB_M
USB_SILAB_P
UART0_TXD
SILAB_3.3V
I2C_0_DAT
I2C_0_CLK
3.3V
USB_5V_DET USB_5V_DET
ADC_2
8V_30V
5V_A
SILAB_4.7V
5V_A
EN_SILAB_LED
SILAB_4.7V
ADC_0
ADC_1
ADC_2
ADC_3
ADC_4
SILAB_TXD
ADC_1
ADC_0
ADC_3
ADC_4
AN_3.3V
AN_3.3V
AN_ADC_3
AN_ADC_3
MON_SYS_RESET#
MON_SYS_RESET#
DIO_04
SILAB_3.3V
SYS_RESET#
