Optimizing Power Consumption of Automotive Systems

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006-2008.

Optimizing Power Consumption of Automotive Systems Requiring Periodic Wake UpAA303

June, 2007

Carl Culshaw, Automotive Systems EngineerArmin Winter, Automotive Field Applications Engineer

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1Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006-2008.

Agenda

►Introduction►Low-Power Wake-up System Requirements►Typical Application Timing Diagram►Parameters Contributing to Current Consumption►Typical Block Diagram►Different Low Power Scenarios►Low-Power Calculator►Current Consumption Diagrams►Low-Power Approaches►Summary

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Introduction

►Why is low-power management important?• Car battery limitations: capacity, physical dimension, weight, cost,…

• Number of Electronic Control Units (ECU’s) in cars is constantly growing (E.g. BMW 7series -> ~70 ECU’s)

• More and more ECU’s need to be powered during the non-operational mode of the car (ignition off).

• OEMs specify an average standby current consumption of less than300μA for each ECU, many of them going even further down to a requirement of less than 100 μA.

To keep battery life at a maximum, smart concepts for power saving during standby mode are required!

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Low-Power Wake-up System Requirements

►Cyclic wake-up ECU system requirements:

►Periodic wake-up to read analog inputs and/or refresh watchdog

►Wake-up on external event (switch detection)

►Very fast wake-up timings in order to save current or to operate an actuator very quickly (e.g. unlock door)

►BCM periodic LIN communication to trigger anti-theft unit

►Wake-up on CAN/LIN bus activity

►Blinking LED (e.g. VW door )

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Typical Application Timing Diagram

Tstop: Time while MCU is in low-power mode or switched off depending on low-power concept.Trun: Trun = MCU is in Run Mode, e.g. reading digital & analog Tosc: Oscillator start up time, plus time required to start SW execution (e.g. Clock quality check,

RESET sequence). If MCU starts based on internal clock, Tosc = 0.Tlin: Duration of LIN communication.Tsum: Tstop + Tosc + Trun

LIN

HW (fix)t[ms]

LIN

I[mA]

Sw

itche

s

Sw

itche

s

Sw

itche

sO

scst

art

Tsum (incl. Tosc)

Tlin

Tstop

Tosc

Trun

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The Power Problem

►2 Elements to total power• Dynamic Power – Run Current• Static Power – Stop Current

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The Power Problem - Dynamic

►Dynamic PowerBasically caused by charging and discharging the gates of the millions of MOS transistors and their interconnects.

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The Power Problem – Dynamic cont’d

Current proportional to capacitance & switching speed

Smaller technology = smaller transistors =smaller gatessmaller capacitances = reduced power

Increased frequencies = faster switching speedslarger currents = increased power

Fortunately…the reduced capacitance wins out over the faster switching speeds

lower overall dynamic Power

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The Power Problem - Static

► Static Power

Static leakage is a result of leakage current due to the finite-resistance ofthe off transistors between power and ground that exist whenever power isapplied to a CMOS circuit. Current highly dependent on the threshold voltage.As technology scales to ever smaller dimensions, supply voltage levels arelikewise scaled. To improve circuit speed, the threshold voltages are also decreased.This decrease in threshold voltage results in an exponential increase in the sub threshold leakage current !Becoming a much larger part of the total power equation!

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The Power Problem - Trends

► Static & Dynamic Power trends (Frequency fixed)

Technology shrinking

Pow

er

Dynamic

Static

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Parameters contributing to current consumption Current Consumption

Dynamic Static

Specified:• System Architecture

(Tsum, Trun, Tlin)

Influenceable:• ECU architecture • On-chip auto wake-up timer & RC for fast wake-up• Current consumption mA/MHz • Clock gating / Clock distribution• Avoiding glitches• Self Timed Blocks• Activity Reduction• Bus frequency• Algorithm

Specified or fixed:• Vdd• Si technology• Leakage

Influenceable:• Low leakage design • Power gating • RAM segmentation • Multiple Supply Voltages

(e.g. separate RAM Vreg)

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Typical Block Diagram

System Basis Chip(SBC CAN/LIN)

MCUVbatSPI

VregWdog

CAN P/L

RelayDrv.

Keys

CAN SPI

LIN1 LIN P/LLIN P/LLIN2

I/O Interface & Sensing

PowerActuator

PowerActuator

PowerActuator

SPI

Vbat

Vbat

Vbat

Switch Detection IC

(MSDI)

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Different Low-Power Scenarios

► Scenario 1: SBC performs periodic wake-up

pros:+ SBC can manage different wake-up events, thus allowing the MCU to be

unpowered in low-power modes+ MCU does not contribute to low power consumption at all

cons:- wake-up timing is longer (Vdd stabilization time, RESET timinig)

have Vdd1=5V stable before releasing the reset- time needed for the oscillator of the MCU to start-up

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Different Low Power Scenarios Cont‘d

► Scenario 2: MCU performs periodic wake-up

pros:+ faster recovery/start-up time+ SBC in low-power mode can still manage wake-up events+ SBC wake-up on current demand feature

cons:- In idle state, two devices (SBC & MCU) contribute to power consumption

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Different Low Power Scenarios Cont‘d

► Scenario 3: MSDI provides periodic wake-up

pros:+ faster recovery/start-up time.+ SBC in low power mode can still manage wake-up events+ SBC wake-up on current demand feature+ Advantages compared to discrete solution:

+ Power Dissipation + Operating Voltage Range+ Board Space Utilization + Number of Solder Joints+ Ground Offset Protection+ Quiescent Current with Wake up

cons:- In idle state, three devices (SBC, MCU & MSDI) contribute

to power consumption

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Low-Power Calculator

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Current Consumption Diagrams

Current vs. Time Diagram

050

100150200250300

60 100

140

180

220

260

300

340

380

420

460

500

Tsum [ms]

I [uA

] Scenario 1Scenario 2

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Current Consumption Diagrams Cont‘d

Zoomed Current vs. Time Diagram

55

60

65

70

75

300 320 340 360 380 400

Tsum[ms]

I[uA] Scenario 1

Scenario 2

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Low-Power Approaches

►Technology• Reduce Interconnect Capacitance

Electro migration and Low - e Insulators• SOI - Technologies

~ 25% total Capacitance ReductionDTMOS - Devices

• Combined Si - III/V-SemiconductorsSpeed Benefit allows Voltage Scaling

►Circuit• Drive Parameterized Standard Cells• Clock Distribution

Buffer Insertion & SizingTolerable SkewVoltage Swing Reduction

• Energy – Recovery CMOS►Logic

• Avoiding Glitches• Self Timed Blocks (asynchronous)• Gate Resizing (parameterized std-cells)• Gated Clock• Activity Reduction

►Architecture (µC)• ‘Power Management’

Different operating modesDynamic Voltage Scaling (Snug-ARM)

• To Cache or not to CacheEliminate of Chip CommunicationMemory Partitioning/Cache

• Performance Oriented ClockingDynamic Frequency Scaling (Snug-ARM)

►Algorithm• Complexity• Inherent Dissipation• Implementation Overhead

►System• ‘Power Management’• Multiple Supply Voltages• Clock Distribution• Local Operation

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Summary

►To keep battery life at a maximum, smart concepts for power saving during standby mode are required!

►In this presentation it is shown, which parameters have influence on power consumption, and how current consumption of an ECU requiring periodic wake-up can be optimized.

►The demonstrated xl-sheet calculator helps to compare different ECU architectures, taking application requirements as well as silicon capabilities into account.

►Freescale has the right technologies and device architectures inplace to provide 1st class system solutions addressing today’s and future low-power requirements!

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006-2008.

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Optimizing Power Consumption of Automotive Systems