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Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
- Optical techniques for ‘connection’ has been moving from left to right- Tremendous increase in data rates for rack-to-rack, chip-to-chip, intra-chip applications- With more volumes, more opportunities and more challenges
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
-19 in US, 12 in Europe, 3 in Asia, 1 in Russia, 1 in South America - Google spent 2.4 billion US dollars for data centers in 2007
Data Centers: Google
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
- Interconnects are vital for performance, power consumption, costs
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
- Various interconnect standards
- Higher and higher data rates. Why? Demands for more bandwidth Serialization
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
Data transferred sequentially !!
Data received sequentially !!
Serial Interconnect: Single connection medium
Data transferred concurrently !!
Data received concurrently !!
Parallel Interconnect: Multiple connection medium
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
- Hard to maintain synchronization between data in different parallel channels
Why Serialization for I/O?
- Smaller sizes for I/O
Gigabit Media Independent Interface (GMII)
: Total 24 lines for 1 Gb/s
Serial Gigabit Media Independent Interface(SGMII)
: Total 8 lines for 1.25 Gb/s
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
- Various interconnect standards
- Higher and higher data rate. Sustainable?
Optical interconnect based on dielectric waveguides- Metal-based interconnects becomes more lossy at higher frequencies
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
Block diagram for optical interconnect
Different approaches:
-Si Photonics“A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard0.13-m CMOS SOI Technology”, IEEE Journal of Solid-State Circuits, Vol. 41, p. 2945, 2006(이슬아)
- GaAs VCSEL with MMF or Optical PCB“Terabit/s-Class Optical PCB Links Incorporating 360-Gb/s Bidirectional 850 nm ParallelOptical Transceivers”, Journal of Lightwave Technology, Vol. 30, p. 560, 2012
Optical Interconnect
Prof. Woo-Young ChoiSilicon Photonics (2012/2)
Block diagram for optical interconnect
Electronics?
- TIA/LM (정현용)- PLL/CDR (권대현)
Electronic Circuits for Optical Systems: Transimpedance Amplifier (TIA)
& Limiting Amplifier (LA)
Hyun-Yong Jung([email protected])
High-Speed Circuits & Systems Laboratory
Contents
Electrical interconnects vs. optical interconnects
Electronic circuits for optical interconnects
TIA design
LA design
Recent research topics
Electrical Interconnects
Transmitter- Serializer: slow parallel data fast serial data- Phase-Locked Loop (PLL): generate reference clock- Pre-emphasis: compensate high-frequency loss
Receiver- Equalizer: compensate high-frequency loss- Limiting amplifier: amplify signal up to digital level- Clock and Data Recovery (CDR): recover synchronous clock and data- De-serializer: fast serial data slow parallel data
Requirements for The First Block
(Voltage / Power) Gain
(Channel) Bandwidth
Noise figure
RF Receiver Front-End Optical Receiver Front-End
(Transimpedance) Gain
(Broadband) Bandwidth
(Input) Noise current
Receiver Basics
(Transimpedance) Gain
(Broadband) Bandwidth
(Input) Noise current
DGain R
12 D pd
BWR C
2, 2n in
D pd
kTIR C
► Resistor performs a
current-to-voltage conversion.
Trade-off between gain, speed and noise !!
Integrated Total Noise
Output Noise Spectrum of Circuit
Circuit bandwidth ↑ Integrated total noise ↑
Bandwidth vs. Noise
BW = 1.4 fB No ISI High noise
BW = 0.35 fB High ISI Low noise
BW = 0.7 fB No ISI Medium Noise
* ISI: Inter-Symbol Interference** fB: data rate
Bandwidth vs. Noise
Inter-Symbol Interference (ISI) vs. Noise
Optimum bandwidth depends on data rates !!
Transimpedance Amplifier (TIA)
Common-gate TIA (CG-TIA) Regulated-cascode TIA (RGC-TIA)
Rin
1
1in
m
Rg
Rin
1
11in
m mB B
Rg g R
TIA design consideration- High gain- Large bandwidth- Low noise- Low input impedance
Transimpedance Amplifier (TIA)
(Shunt-Shunt) Feedback Amplifier
- Low input impedance & High transimpedance !!
(Transimpedance) Gain
(Broadband) Bandwidth
(Input) Noise current
A
1 FAGain R
A
12 F pd
ABWR C
2,2
, 2
4 n An in
F F
VkTIR R
11in FR R
A
Rin
Advanced Techniques
Shunt Peaking
• Inductor implementation :(a) Spiral inductor(b) Active inductor
(a) Large power consumption & chip area(b) PVT variation
Requirements for Limiting Amplifier
• General Considerations Input capacitance Low input capacitance the TIA bandwidth Bandwidth (BW) TIA: 70% of data rate minimize the noise
Limiting Amplifier: greater BW (usually equal to the data rate) Noise Large BW greater integrated noise
High trans-impedance gain of TIA hard at high speed Gain
Cascaded Gain stages
A, w0A=gainW0=bandwidth
N-stages
A, w0 A, w0 A, w0
3 0 00.92 1N
dBw w wN
NtotA A
0 0( / ) /N Ntot totA B w w B A
30.9
dB Ntot
w BN A
Normalized BW as a function of N for Atot = 100 (40dB)
Less than 15%
• N is higher gain per stage is small noise ↑ Typical high-gain limiters employ
no more than five gain stages
Advanced Techniques
(a) Resitively-loaded differential pairs. (b) Active feedback added. (c) Inductive peaking added. (d) Negative capacitance added.
Recent Research Topics
Power consumption of optical system should be minimized to take over a substantial fraction of interconnect applications.
Thank you for listening !!
Hyun-Yong Jung([email protected])
High-Speed Circuits & Systems Laboratory
Contents
Optical transceiver
Phase Locked Loop (PLL)
Clock and Data Recovery (CDR)
PLL vs. CDR
Simulation results
Optical transceiver
Generating clock Transmitter: Phase Locked Loop Circuit Receiver: Clock and Data Recovery Circuit
PRBS
Pat
tern
Gen
erat
or&
Bit-
Erro
r Rat
e (B
ER) T
este
r
N-p
aral
lel …
N-p
aral
lel …
Fibe
r
Phase Locked Loop
Providing clock to system
1971Intel 4004Clock speed : 108kHz
Systems withAsynchronous data
Crystal oscillator
Characteristics• Extremely precise• Large size• Few kHz ~ few MHz
Phase Locked Loop
Providing clock to system
2000~Intel CPUClock speed : few GHz
Systems withAsynchronous data
Crystal oscillator
Characteristics• Extremely precise• Large size• Few kHz ~ few MHz
Phase Locked Loop
Providing clock to system
2000~Intel CPUClock speed : few GHz
Systems withAsynchronous data
ElectricalOscillator
Characteristics• Small size• High speed clock generation
Phase Locked Loop
Simple electrical VCO
Systems which need clock signal
Electrical oscillator high speed clock
Problem Process variation Voltage variation Temperature variation Device mismatch
Variation of target frequency Intrinsic noise
Adequate clock generation X
Phase Locked Loop
ReferenceClock
DividedClock
IUp
IDown
DFF
DFFReset
Up
DownR1
C1C2
Fixed-rateFrequency Divider
÷N
OutputClock
Vload
Clkpi+1 Clkni+1
Clkni
ContVbias
Delay cell
Clkpi
Delay cellDelay cell
PFD
CP
LP
FD
VCO
The purpose of PLL Providing clock specific frequency Regardless of variations Target frequency by User Reference clock (crystal or equipment)
Fixed-rate Frequency Divider Clock generated by VCO high speed Decreasing frequency VCO clock to reference clock (crystal oscillator clock)
Phase/Frequency Detector (Sensing) Reference clock Target frequency Sensing the difference between reference clock and VCO clock Order making fast clock or slow clock
ReferenceClock
DividedClock
IUp
IDown
DFF
DFFReset
Up
DownR1
C1C2
Fixed-rateFrequency Divider
÷N
OutputClock
Vload
Clkpi+1 Clkni+1
Clkni
ContVbias
Delay cell
Clkpi
Delay cellDelay cell
PFD
CP
LP
FD
VCO
Charge pump Transmitting order of PFD to VCO
Voltage Controlled Oscillator Controlling the frequency by converting voltage The results of sensing applied to VCO by feedback loop
ReferenceClock
DividedClock
IUp
IDown
DFF
DFFReset
Up
DownR1
C1C2
Fixed-rateFrequency Divider
÷N
OutputClock
Vload
Clkpi+1 Clkni+1
Clkni
ContVbias
Delay cell
Clkpi
Delay cellDelay cell
PFD
CP
LP
FD
VCO
Phase Locked Loop
PFD CP VCO
Frequency
Voltage
[VCO charateristics]
Target frequency
Up
Down
ReferenceClock
VCOClock
ReferenceClock
VCOClock
ReferenceClock
VCOClock
VCO clock more faster
VCO clock more slower
Current in
Current out
V↓
V↑
Clock and Data Recovery
Asynchronous data transmitted with serial link Noisy + Asynchronous data Similar with PLL Input Data
PLL vs. CDR
Clock edge periodic ↔ Data edge random
PLL Phase & Frequency detecting possible
CDR Phase detecting possible , Frequency detecting impossible
Additional block is needed for frequency detecting PLL or FD(Frequency Detector)