OPERATION OF TRANSFORMERLESS INVERTERS, PARALLEL … · IV Figure 2.19 3Level Triangular carrier signals modification block. 27 Figure 2.20 3Level inverter SPWM comparator. 28 Figure

POLITECNICO DI MILANO

Scuola di Ingegneria Industriale e

dell’Informazione

Corso di laurea magistrale in Ingegneria Elettrica

OPERATION OF TRANSFORMERLESS INVERTERS, PARALLEL CONNECTED,

WITH MODIFIED SPWM AND SVM

Relatore: Prof. Castelli Dezza Francesco

Correlatore: Ing. Mazzucco Irino

Tesi di laurea magistrale di:

Arcangelo Nardone Matr. 853201

Anno accademico 2017/2018

Acknowledgments

I would like to thank Prof. Castelli Dezza Francesco, as my tutor at Politecnico di Milano.

He has been very available, helpful and our discussions have always been interesting and

productive.

I really thank EPS Elvi Energy that gave me the opportunity to realize my thesis work

and Ing. Marchegiani Gabriele who introduced me to the firm.

A great thank goes to Ing. Mazzucco Irino who, as my tutor at EPS Elvi Energy, followed

me in this journey and gave an important help for the realization of the final work. Moreover,

I thank the whole team I met there.

I

Table of contents

OPERATION OF TRANSFORMERLESS INVERTERS, PARALLEL CONNECTED,

WITH MODIFIED SPWM AND SVM

ACKNOWLEDGMENTS

TABLE OF CONTENTS ........................................................................................ I

LIST OF FIGURES ............................................................................................. III

LIST OF TABLES .............................................................................................. VII

ABSTRACT ........................................................................................................ IX

SOMMARIO ...................................................................................................... XI

STATE OF THE ART ......................................................................... 1

GRID-CONNECTED PARALLEL INVERTERS WITH TRANSFORMER ................................................ 1

PV PANELS PARASITIC CAPACITANCE ........................................................................................3

SOLUTIONS IN LITERATURE ..................................................................................................... 4

1.3.1 Transformer on the AC side .......................................................................................... 4

1.3.2 DC-DC Converter with High Frequency Transformer ................................................ 4

1.3.3 Parallelization with coupled inductors ......................................................................... 5

1.3.4 Triangular carrier signals synchronization ................................................................. 6

1.3.5 Timer interrupt synchronization using Controller Area Network (CAN)

communication ...................................................................................................................... 8

CASE STUDY .................................................................................. 11

SIMULINK MODEL .................................................................................................................. 11

2.1.1 General model description ........................................................................................... 11

Inverter ............................................................................................................................... 13

LCL Filter ............................................................................................................................ 15

Grid ..................................................................................................................................... 16

2.1.2 Current controller ........................................................................................................ 17

2.1.3 Inverter modulations .................................................................................................. 23

II

Sinusoidal Pulse Width Modulation ..................................................................................... 23

Space Vector Modulation ..................................................................................................... 29

Considerations on switching frequency..................................................................................31

MODIFIED SPWM ................................................................................................................ 33

MODIFIED SVM ................................................................................................................... 34

TEST RESULTS .............................................................................. 35

SPWM ................................................................................................................................. 35

3.1.1 2Level Inverter ............................................................................................................. 37

3.1.2 3Level Inverter ............................................................................................................. 51

SVM .................................................................................................................................... 56

3.2.1 2Level Inverter ............................................................................................................ 57

3.2.2 3Level Inverter ............................................................................................................ 63

FURTHER MODULATION TECHINIQUES .................................... 67

2LEVEL SVM ALGORITHM MODIFICATION............................................................................. 67

Results .................................................................................................................................. 69

3LEVEL ZERO COMMON MODE SVM ..................................................................................... 71

ZCM theory ............................................................................................................................ 71

Simulink model .................................................................................................................... 75

Results .................................................................................................................................. 78

LABORATORY TESTS ................................................................... 83

TEST BENCH .......................................................................................................................... 83

LCL FILTER .......................................................................................................................... 84

MEASUREMENTS .................................................................................................................. 84

PWM SYNCHRONIZATION ..................................................................................................... 85

CONCLUSIONS .............................................................................. 87

CONCLUSIONS ....................................................................................................................... 87

FUTURE WORK...................................................................................................................... 89

REFERENCES ................................................................................................... 90

APPENDIX A ....................................................................................................... I

APPENDIX B ...................................................................................................... V

APPENDIX C .................................................................................................. XIII

III

List of figures

Figure 1.1 PV parallel inverter topologies: (a) decentralized inverters; (b) centralized inverter;

(c) centralized n parallel inverters with multi-winding transformer; (d)

centralized n parallel inverters with n transformers; (e) centralized n parallel

inverters with a single transformer; (f) centralized n parallel transformerless

inverters. 1

Figure 1.2 Model of two parallel inverters with parasitic capacitances to ground and zero-

sequence circulating current. 2

Figure 1.3 DC-DC Converter with High Frequency Transformer. 4

Figure 1.4 Parallelization with three single-phase IPTs (Inter-Phase Transformer). 5

Figure 1.5 Parallelization with three-phase IPT. 5

Figure 1.6 Single-phase IPT. 5

Figure 1.7 Simplified zero-sequence circuit of two parallel connected inverters. 6

Figure 1.8 Timer of the master and CAN transmission. 8

Figure 1.9 Timer of the slave. 8

Figure 2.1 Simulink model. 12

Figure 2.2 Simulink powergui block. 12

Figure 2.3 Simulink model of 2Level inverter. 13

Figure 2.4 Simulink model of 3Level inverter. 14

Figure 2.5 LCL Filter. 15

Figure 2.6 Equivalent grid. 16

Figure 2.7 Current controller. 17

Figure 2.8 Simulink model of a grid-connected inverter with current control loop. 18

Figure 2.9 Simplified plant for PI controller. 18

Figure 2.10 PidTuner interface. 19

Figure 2.11 Bode diagram of Gclosed-loop with φ=60°. 20



Figure 2.14 SPWM and Current controller. 23

Figure 2.15 2Level inverter SPWM with modified triangular carrier signal. 24

Figure 2.16 2Level Triangular carrier signal modification block. 25

Figure 2.17 3Level inverter SPWM with modified triangular carrier signals. 26

Figure 2.18 3Level inverter modified triangular carrier signals. 27

IV

Figure 2.19 3Level Triangular carrier signals modification block. 27

Figure 2.20 3Level inverter SPWM comparator. 28

Figure 2.21 SVM and Current controller. 29

Figure 2.22 2Level inverter SVM modulation with modified triangular carrier signal. 30

Figure 2.23 3Level inverter SVM modulation with modified triangular carrier signal. 30

Figure 2.24 Frequency selection. 31

Figure 2.25 Logic of inverters modifications based on frequency selection. 31

Figure 2.26 SPWM triangular carrier signal modification. 33

Figure 2.27 SVM triangular carrier signal modification. 34

Figure 2.28 0-axis PI controller with Ts. 34

Figure 3.1 Measured quantities in the Simulink model. 36

Figure 3.2 2Level SPWM Inverter 1 voltages and currents; same frequency. 37

Figure 3.3 2Level SPWM Inverter 2 voltages and currents; same frequency. 37

Figure 3.4 Current ripples. 38

Figure 3.5 Inverter active and reactive power. 39

Figure 3.6 2Level SPWM current controller quantities. 39

Figure 3.7 2Level SPWM inverter dq0 currents. 40

Figure 3.8 2Level SPWM inverter dq0 errors. 40

Figure 3.9 2Level SPWM PI controller outputs. 41

Figure 3.10 2Level SPWM dq0 voltages. 41

Figure 3.11 Comparison between modulating and carrier signals. 42

Figure 3.12 2Level SPWM grid voltages and currents. 43

Figure 3.13 2Level SPWM ZSCC; same frequency. 43

Figure 3.14 Equivalent LC filter. 44

Figure 3.15 2Level SPWM Inverter 1 currents; different frequencies. 45

Figure 3.16 2Level SPWM inverter dq0-quantities; different frequencies. 46

Figure 3.17 2Level SPWM inverter dq0 voltages; different frequencies. 46

Figure 3.18 2Level SPWM modulating and carrier signals; different frequencies. 47

Figure 3.19 2Level SPWM ZSCC; different frequencies. 47

Figure 3.20 2Level SPWM inverter output waveforms; different frequencies with correction.

48

Figure 3.21 2Level SPWM ZSCC; different frequencies with modification using b_sw1. 48

Figure 3.22 2Level SPWM ZSCC; different frequencies with modification using b_sw1 and

b_sw2. 49

Figure 3.23 Triangular carrier signal. 49

Figure 3.24 Modulating signal compared with Modified triangular carrier signal. 50

Figure 3.25 3Level SPWM inverter voltages and currents; same frequency. 52

Figure 3.26 3Level SPWM ZSCC; same frequency. 52

V

Figure 3.27 3Level SPWM grid steady-state currents; different frequencies. 53

Figure 3.28 3Level SPWM inverter dq0 voltages; different frequencies. 53

Figure 3.29 3Level SPWM ZSCC; different frequencies. 54

Figure 3.30 3Level SPWM grid currents; different frequencies with modification. 54

Figure 3.31 3Level SPWM ZSCC; different frequencies with modification using b_sw1. 55

Figure 3.32 3Level SPWM ZSCC; different frequencies with modification 55

Figure 3.33 2Level SVM ZSCC; same frequency. 57

Figure 3.34 2Level SVM inverter currents; same frequency. 58

Figure 3.35 2Level SVM inverter dq0 currents; same frequency. 58

Figure 3.36 2Level SVM grid voltages and currents; same frequency. 59

Figure 3.37 2Level SVM modulating signal vs triangular carrier signal. 59

Figure 3.38 2Level SVM ZSCC; different frequencies. 60

Figure 3.39 2Level SVM ZSCC; different frequencies with modification using b_sw1. 60

Figure 3.40 2Level SVM ZSCC; different frequencies with modification 61


Figure 3.42 3Level SVM ZSCC; same frequency. 63

Figure 3.43 3Level SVM inverter voltages and currents; same frequency. 63

Figure 3.44 3Level SVM ZSCC; different frequencies. 64

Figure 3.45 3Level SVM modulating signals vs modified triangular carrier signal. 64


Figure 3.47 3Level SVM ZSCC; different frequencies with modification using b_sw1 and

b_sw2. 65


Figure 4.1 Zero-vector time modification in Sector1. 67

Figure 4.2 2Level SVM with k. 68

Figure 4.3 2Level SVM ZSCC modified with k; same frequency. 69

Figure 4.4 2Level SVM ZSCC modified with k; different frequencies. 69

Figure 4.5 2Level SVM with k grid currents; difference frequency. 70

Figure 4.6 3Level ZCM SVM inverter hexagon. 72

Figure 4.7 Reference times for Sector 1. 74

Figure 4.8 Reference times for Sector 4. 74

Figure 4.9 3Level inverter ZCM SVM. 75

Figure 4.10 Sawtooth carrier signal generation. 76

Figure 4.11 Modified sawtooth carrier signal generation. 77

Figure 4.12 ZCM leg b signals. 77

Figure 4.13 Classical SVM CMV. 78

Figure 4.14 ZCM SVM CMV. 79

Figure 4.15 ZCM SVM CMV zoom. 79

VI

Figure 4.16 ZSCC for classical SVM. 79

Figure 4.17 ZSCC for ZCM SVM. 79

Figure 4.18 ZCM SVM ZSCC; grid-connected with different inverter frequencies. 80

Figure 4.19 ZCM SVM load and grid currents. 80

Figure 4.20 Currents with DC component. 81

Figure 4.21 Currents without DC component. 81

Figure 5.1 Scheme for laboratory tests. 83

Figure 5.2 ZSCC and inverter current. 84

Figure 5.3 ZSCC and inverter current zoom. 84

Figure 5.4 ZSCC and inverter current with modification. 85

Figure 5.5 ZSCC and inverter current with modification zoom. 85

VII

List of tables

Table 1 Inverter parameters. 13

Table 2 LCL parameters. 15

Table 3 PI parameters: kp and ki. 21

Table 4 0-axis PI parameters for SPWM. 33

Table 5 0-axis PI parameters for SVM. 34

Table 6 2Level SPWM different VDC_Bus. 50

Table 7 2Level SPWM same VDC_Bus. 51

Table 8 2Level SPWM percent THD. 51

Table 9 3Level SPWM different VDC_Bus. 56

Table 10 3Level SPWM same VDC_Bus. 56

Table 11 3Level SPWM percent THD. 56

Table 12 2Level SVM different VDC_Bus. 62

Table 13 2Level SVM same VDC_Bus. 62

Table 14 2Level SVM percent THD. 62

Table 15 3Level SVM different VDC_Bus. 66

Table 16 3Level SVM same VDC_Bus. 66

Table 17 3Level SVM percent THD. 66

Table 18 2Level SVM with k; different VDC_Bus. 70

Table 19 2Level SVM with k percent THD. 70

Table 20 Pole Voltage and Common Mode Voltage. 71

Table 21 ZCM SVM time intervals. 73

Table 22 Switches conditions in Sector 1. 74

Table 23 Switches conditions in Sector 4. 74

Table 24 ZCM SVM grid currents THD. 81

IX

Abstract

The thesis deals with grid-connected parallel inverters. It tries to find a valid alternative to the

most common topologies. The initial scenario represents two parallel inverters, grid-

connected, each through a transformer on the AC side. In addition, they are connected on the

DC side through an equivalent parasitic capacitance, due to PV panels. In this situation a

problem arises: a current flows in the capacitance and can even reach high values (tens of

Ampere). It is called zero-sequence circulating current (ZSCC).

Anyway, the solution with transformers allows to reduce that current but introduces

disadvantages. A transformer often represents encumbrance, weight, costs and problems of

transportation.

Thus, an alternative solution should be found to reduce the ZSCC. In literature, some studies

have already been carried out. [1] demonstrates that, thanks to the synchronization of the

triangular carrier signals of the two inverters, the ZSCC reduces in amplitude. This solution

results valid but it is very difficult to synchronize two different waveforms due to the practical

differences in the instruments and, even if it was possible, it would be a problem when the

number of the inverters increases. Other papers suggest solutions depending on the type of

modulation adopted for the inverters: Sinusoidal Pulse Width Modulation (SPWM) or Space

Vector Modulation (SVM), in case of both 2Level or 3Level inverters.

According to these studies, the aim is to work on the modulation of the inverters so to reduce

the ZSCC, instead of using transformers, thus to increase the whole efficiency of the system.

The modifications vary depending on the modulation: for SPWM, it will act on the triangular

carrier signal [2] while for SVM both on the triangular carrier signal and on the hexagon of the

SVM itself [3][4].

Good results have been obtained, with reduction of ZSCC depending on each considered case.

X

The structure consists of 6 chapters:

• Chapter 1 State of the art. In the first chapter there is an introduction of what the

current technology presents, which are the problems and where they come from. Some

solutions, already present in literature, are described.

• Chapter 2 Case study. Here, it focuses on the actual model and solutions as the main

object of the thesis. It is reported how the equivalent scheme is and its Simulink model.

An introduction of the techniques is carried out. Then, there is a detailed analysis of

the modified modulations.

• Chapter 3 Test results. According to previous chapter, results of each simulation are

reported, and a comparison is done to understand what differs between them and

which can be more advantageous than another.

• Chapter 4 Further modulation techniques. In addition to previous modulations,

new ones are studied. It tries to look for more ways to get to the same goals.

• Chapter 5 Laboratory tests. In this section, some laboratory results are presented

based on a similar technique.

• Chapter 6 Conclusions. The last chapter contains a summary of all the results

obtained during the work and some comments on their behaviour and significance.

There also are opinions on which future work could be.

XI

Sommario

La tesi tratta l’argomento di inverter in parallelo collegati alla rete. Si cerca di trovare una

valida alternativa alle topologie più comuni. Lo scenario iniziale rappresenta due inverter in

parallelo, collegati alla rete, ciascuno attraverso un trasformatore sul lato AC. Inoltre, sono

collegati sul lato DC attraverso una capacità parassita equivalente, dovuta ai pannelli

fotovoltaici. In questa situazione sorge un problema: una corrente scorre nella capacità e può

raggiungere anche valori elevati (decine di Ampere). È nota come corrente di circolazione di

sequenza omopolare (ZSCC).

Ad ogni modo, la soluzione con trasformatori consentirebbe di ridurre tale corrente ma

introduce degli svantaggi: un trasformatore rappresenta spesso ingombro, peso, costi e

problemi di trasporto.

Pertanto, si dovrebbe trovare una soluzione di diverso genere per ridurre la ZSCC. In

letteratura, alcuni tentativi sono già stati effettuati. [1] dimostra che, grazie alla

sincronizzazione delle portanti triangolari dei due inverter, la ZSCC si riduce in ampiezza.

Questa soluzione risulta valida, ma è molto difficile sincronizzare due diverse forme d'onda a

causa delle differenze tra gli strumenti e, anche se fosse possibile, sarebbe un problema quando

il numero degli inverter aumenta. Altri studi suggeriscono soluzioni basate sul tipo di

modulazione adottata per gli inverter: Sinusoidal Pulse Width Modulation (SPWM) o Space

Vector Modulation (SVM), sia per inverter 2Livelli che 3Livelli.

L'obiettivo posto è di lavorare sulla modulazione degli inverter in modo da ridurre la ZSCC,

anziché utilizzare i trasformatori, in modo da aumentare l’efficienza totale del sistema. Le

modifiche variano a seconda della modulazione: per SPWM, si agirà sulla portante triangolare

[2] mentre per SVM sia sulla portante triangolare che sull'esagono del SVM stesso [3] [4].

In generale si sono ottenuti risultati positivi, con relativa riduzione di ZSCC a seconda dei casi.

XII

La struttura è composta da 6 capitoli:

• Capitolo 1 State of the art. Il primo capitolo presenta un'introduzione sull’attuale

tecnologia, quali sono i problemi e da dove provengono. Alcune soluzioni, già presenti

in letteratura, sono descritte.

• Capitolo 2 Case study. Di seguito, ci si concentra sul modello e sulle soluzioni che

rappresentano il fulcro del lavoro. Viene riportato lo schema equivalente, il suo

modello Simulink e un'introduzione alle tecniche. Successivamente, è presentata

un'analisi dettagliata delle modulazioni modificate.

• Capitolo 3 Test results. Continuando, vengono riportati i risultati di ciascuna

simulazione e viene effettuato un confronto per capire cosa differisce e quale

situazione sia più vantaggiosa.

• Capitolo 4 Further modulation techniques. Oltre alle modulazioni precedenti, ne

vengono studiate di nuove. Si cerca di trovare altre soluzioni per il conseguimento

degli stessi risultati.

• Capitolo 5 Laboratory tests. In questa sezione, sono presentati alcuni risultati di

laboratorio sulla base di una tecnica simile a quelle analizzate in precedenza.

• Capitolo 6 Conclusions. L'ultimo capitolo contiene un riepilogo di tutti i risultati

ottenuti durante il lavoro e alcuni commenti sul loro comportamento e significato.

Sono date anche opinioni su quale potrebbe essere il lavoro futuro.

1.1 Grid-connected parallel inverters with transformer

1

State of the art

The first chapter deals with the problematics and solutions of the topic from a general

point of view. It contains an explanation of the causes and how the techniques, present in

literature, try to solve them.

Grid-connected parallel inverters with transformer

The most spread configurations in the past years presented a solution in which each

inverter had its own transformer, or inverters were connected to it in many different ways [5].

Figure 1.1 PV parallel inverter topologies: (a) decentralized inverters; (b) centralized inverter; (c) centralized n parallel inverters with multi-winding transformer; (d)

centralized n parallel inverters with n transformers; (e) centralized n parallel inverters with a single transformer; (f) centralized n parallel transformerless inverters.

1 State of the art

2

The use of transformers was necessary since the galvanic isolation, in photovoltaic

installations, was mandatory in different countries; in addition, transformers allow to filter

out the DC components present in the generated currents, so that they don’t reach the grid as

the standards and regulations state. This, anyway, could be obtained without transformers

using any solution that makes the DC current stay below a certain limit. The latter statement

gives the opportunity of finding a different configuration in which transformers are removed

allowing a reduction of costs, volume and weight, and obviously power losses, increasing the

system efficiency. Usually, configurations (c)-(f) in Figure 1.1 are used, since parallel inverters

ensure higher efficiency in the low power range. In fact, the power is divided per each inverter

so that they can be disconnected and reconnected depending on the required power. Apart

from this, a drawback is introduced: when inverters operate in parallel, a zero-sequence

circulating current appears. This is due a parasitic capacitance between the PV panels and the

ground. Thus, a path for that current exists and studies on its limitation have to be done.

Figure 1.2 Model of two parallel inverters with parasitic capacitances to ground and zero-sequence circulating current.

1.2 PV panels parasitic capacitance

3

PV panels parasitic capacitance

In this paragraph, a detailed study of the parasitic capacitance origin is carried out.

[6] has been recalled in help for the explanation and for the modelling of the capacitance. Since

PV panels are non-ideal components, a leakage current can occur depending on the value of

the parasitic capacitance between the panels themselves and the ground.

As Figure 1.2 shows, leakage current flows both on the DC and the AC side; this causes

problems like: conducted and radiated EMI, grid current distortion, losses in the PV system,

harmonic components injected into the grid and unsafe condition for work. Unlike the serious

problematics caused by the parasitic capacitance, its value is often of difficult identification.

[7] [8] [9] give values based on qualitative analysis: they assume that the capacitance depends

on the size of the module, the height above the ground, the size of the structure on which the

panel is installed and on weather conditions. [6] introduces a novel model in which the total

capacitance is considered as the sum of the cell-to-frame capacitance, the cell-to-rack

capacitance and the cell-to-ground one.

𝐶𝑃𝑉 = 𝐶𝑐𝑓 + 𝐶𝑐𝑟 + 𝐶𝑐𝑔 Eq. (1.1)

This calculation allows to give a more precise value to the parasitic capacitance even if some of

the terms can be neglected depending on the specific conditions of the PV panels.

Even if this situation is caused by the presence of grounding, it can’t be avoided due to safety

reason, since PV systems are often connected to other sources of power or devices, and to

intrinsic characteristics of the PV panels.

An electrical voltage exists between the PV cell and the frame and it can cause electrons loose

from the material used in the PV module and discharge through grounded frame. Most of the

PV panels are made of P-type cells which lead to polarization and negative potential is

generated; they are neutralized through grounding negative pole. When a PV module

generates electricity, its surface area becomes charged and acts like a capacitor. This

capacitance is referred as parasitic capacitance. During the operation, PV module is also

connected to the inverter where the fluctuating voltage constantly changes the state of charge

of parasitic capacitance and causes a displacement current proportional to the capacitance and

to the voltage amplitude. This leads to a leakage current: even if not dangerous, it

superimposes to possible residual current that could occur through touching a live line through

a damaged insulation and can seriously hinder its detection. Hence, grounding of PV modules

becomes very important [10].

1 State of the art

4

Solutions in literature

In literature, many methods of reducing zero-sequence circulating current have been

already presented [1], [11], [12], [13], [14]. They involve both hardware and software solutions.

1.3.1 Transformer on the AC side

The first attempt considers the configuration with transformer on the AC side [15], [16]:

it is useful if the impedance of the transformer, related to its short-circuit percent voltage 𝑉𝑐𝑐,

is high enough to limit the ZSCC, but it has the drawback of making the system bulky and

costly. In addition, transformers introduce power loss thus decreasing the whole efficiency.

1.3.2 DC-DC Converter with High Frequency Transformer

A similar solution presents transformer on the DC side: it is a high-frequency transformer

usually in a DC-DC dual active bridge converter that allows galvanic isolation, switching loss

reduction, EMI improvement and higher efficiency. Anyway, this configuration needs a trade-

off between the minimization of losses and the maximization of the power conversion. This is

done by minimizing the leakage inductance of the HF transformer and adding inductors to

adjust the phase-shift angle, between the two bridges, respectively.

Figure 1.3 DC-DC Converter with High Frequency Transformer.

1.3 Solutions in literature

5

1.3.3 Parallelization with coupled inductors

A further hardware configuration consists in parallelizing the AC side of the two inverters

using coupled inductors built on a single magnetic core. These are inter-phase reactors that

provide high zero-sequence impedance. They can be built both as one reactor per phase or as

3-limb and 5-limb transformers. This ensures that, if the two inverters output currents are

perfectly balanced, flux can’t flow in the core producing no voltage drop and consequentially

no current exists.

Figure 1.4 Parallelization with three single-phase IPTs (Inter-Phase Transformer).

Figure 1.5 Parallelization with three-phase IPT.

Figure 1.6 Single-phase IPT.

It is possible to analyse separately each phase and study the behaviour of the fluxes. The

instantaneous value of the currents 𝑖𝑎1 and 𝑖𝑎2 tends to be the same because the IPT imposes

a high impedance to their difference; when both currents are identical, no flux is generated

through the magnetic core, closing in the air. Hence, when the two currents are equal, the

impedance imposed by the IPT is the leakage inductance. So, the magnetic flux through the

magnetic path is only generated by a difference in the phase currents.

1 State of the art

6

Therefore, neglecting the leakage flux, the magnetic flux through the core is given.

𝜑𝑚 = 𝜑1 − 𝜑2 =𝑁 ∙ (𝑖𝑎1 − 𝑖𝑎2)

𝑅 Eq. (1.2)

with:

• N = number of turns;

• R = reluctance of the core.

1.3.4 Triangular carrier signals synchronization

This study analyses an alternative method of zero-sequence circulating current reduction:

it regards a software solution. Starting from the zero-sequence equivalent circuit of two

parallel connected inverters, it is possible to derive the equations for the explanation.

Figure 1.7 Simplified zero-sequence circuit of two parallel connected inverters.

with:

• 𝐶𝑃𝑉1 and 𝐶𝑃𝑉2 parasitic capacitances between PV panels and ground;

• 𝑉01(𝑡) and 𝑉02(𝑡) zero-sequence voltages of the inverters;

• 𝐿𝑓0 zero-sequence equivalent inductance of the three-phase filter;

• 𝐼01(𝑡) and 𝐼02(𝑡) zero sequence currents.

If each harmonic component (h) of the zero-sequence current is considered and the

parameters of the system are the same 𝑋02,ℎ = 𝑋01,ℎ = 𝑋0,ℎ, it results that the zero-sequence

current.

𝐼0𝑟,ℎ = (V01,h - V02,h) ∙1

𝑗 ∙ (𝑋0,ℎ) Eq. (1.3)


7

The difference (V01,h - V02,h) can be reported as V0r,h. From Eq. (1.3), it is possible to notice that

𝐼0𝑟,ℎ can be reduced both by increasing the value of the inductance (adding common mode

inductance filter or using IPT, as in the previous paragraph) and by acting on V0r,h.

As [1] suggests, zero-sequence inverter voltages present three main harmonic components:

DC, 3 ∙ 𝑓𝑔𝑟𝑖𝑑 and 𝑓𝑠𝑤 (switching frequency).

𝑉01(𝑡) = 𝑉01𝐷𝐶

+ √2 ∙ 𝑉013∙𝑓𝑔𝑟𝑖𝑑∙ 𝑠𝑖𝑛(3 ∙ 𝜔𝑔𝑟𝑖𝑑 ∙ 𝑡 + 𝛼1𝑔𝑟𝑖𝑑) +

√2 ∙ 𝑉01𝑠𝑤∙ 𝑠𝑖𝑛(2𝜋 ∙ 𝑓𝑠𝑤 ∙ 𝑡 + 𝛽1𝑠𝑤)

Eq. (1.4)

𝑉02(𝑡) = 𝑉02𝐷𝐶+ √2 ∙ 𝑉023∙𝑓𝑔𝑟𝑖𝑑

∙ 𝑠𝑖𝑛(3 ∙ 𝜔𝑔𝑟𝑖𝑑 ∙ 𝑡 + 𝛼2𝑔𝑟𝑖𝑑) +

√2 ∙ 𝑉02𝑠𝑤∙ 𝑠𝑖𝑛(2𝜋 ∙ 𝑓𝑠𝑤 ∙ 𝑡 + 𝛽2𝑠𝑤)

Eq. (1.5)

Combining Eq. (1.4) and Eq. (1.5), V0r,h can be derived.

V0r(𝑡) = [𝑉01𝐷𝐶− 𝑉02𝐷𝐶

] + [√2 ∙ 𝑉013∙𝑓𝑔𝑟𝑖𝑑∙ sin(3 ∙ 𝜔𝑔𝑟𝑖𝑑 ∙ 𝑡 +

𝛼1𝑔𝑟𝑖𝑑) − √2 ∙ 𝑉023∙𝑓𝑔𝑟𝑖𝑑∙ sin(3 ∙ 𝜔𝑔𝑟𝑖𝑑 ∙ 𝑡 + 𝛼2𝑔𝑟𝑖𝑑)] + [√2 ∙ 𝑉01𝑠𝑤

∙

sin(2𝜋 ∙ 𝑓𝑠𝑤 ∙ 𝑡 + 𝛽1𝑠𝑤) − √2 ∙ 𝑉02𝑠𝑤∙ sin(2𝜋 ∙ 𝑓𝑠𝑤 ∙ 𝑡 + 𝛽2𝑠𝑤)] =

𝑉0𝑟𝐷𝐶+ 𝑉0𝑟3∙𝑓𝑔𝑟𝑖𝑑

+ 𝑉0𝑟𝑠𝑤

Eq. (1.6)

By some manipulations, if the two inverters have the same DC voltage and the same phase-

shift angle, depending on the grid frequency, it can be stated that V0r(𝑡) depends only on the

shift angles of the two triangular carriers. Next equation takes into account this difference.

𝑉0𝑟(𝑡) = 𝑉0𝑟𝑠𝑤 = 2 ∙ √2 ∙ 𝑉0𝑠𝑤

∙ 𝑠𝑖𝑛 (𝛽1𝑠𝑤−𝛽2𝑠𝑤

2)

∙ 𝑐𝑜𝑠 (4𝜋 ∙ 𝑓𝑠𝑤 ∙ 𝑡 + 𝛽1𝑠𝑤+𝛽2𝑠𝑤

2)

Eq. (1.7)

Thus, if the difference 𝛽1𝑠𝑤−𝛽2𝑠𝑤 tends to 0, zero-sequence voltage does too, reducing the

zero-sequence circulating current.

1 State of the art

8

1.3.5 Timer interrupt synchronization using Controller Area

Network (CAN) communication

This technique has been introduced in [16], to find a solution to common-mode voltage

imposed on the parasitic capacitance. Each inverter operates with its own DSP and, even if the

DSPs come from the same manufacturer, their timer speeds are different, and it results

difficult to generate synchronous PWM. To avoid large voltage across the parasitic capacitance,

it is used a synchronization method through controller area network (CAN) communication.

A master-slave configuration is adopted: the master sends CAN data periodically and the slave

only receives them.

Figure 1.8 Timer of the master and CAN transmission.

In Figure 1.8, master transmits data via CAN when 𝑇𝑀 = 0 with a transmission interrupt

latency of α. Then, the transmitted data frame arrives to the slave and a CAN receiving

interrupt is generated to acquire the data with a receiving latency of β. Thus, the total time to

transmit and receive data is 𝐿𝑇 = 𝛼 + 𝐿𝐹 + 𝛽. Then, 𝑑 = 𝑀𝑛 − 𝐿𝑇, where 𝑀𝑛 is the timer master

closest to the CAN receiving, and 𝑟 = 𝑅𝑇 − 𝑆𝑛, the difference between the time to receive the

input and the starting point of receive interrupt is generated, are defined.

Figure 1.9 Timer of the slave.


9

Finally, 𝑇 = 𝑑 + 𝑟 can be defined. Now, given ccp as the timer period, it is possible to describe

how PWM is synchronized: when the receiving interrupt occurs in the upward mode, if 𝑇 > 0

and 0 < 𝑇 < 𝑐𝑐𝑝

2, the timer of the slave results faster than that of the master and the slave’s

timer is increased by 𝑐𝑐𝑝 + 𝑇; then, if 𝑇 < 0 and 𝑇 >𝑐𝑐𝑝

2, the slave’s timer is slower than the

master’s one and slave’s timer is decreased by 𝑐𝑐𝑝 − 𝑇. An opposite control occurs if the

downward mode is considered. This should allow to realize a PWM synchronization and

minimize as possible the zero-sequence circulating current generated by the common-mode

voltage across the parasitic capacitance.

A similar solution is to use an optical fibre to make digital signal flow. This includes a trigger

that allows the master inverter to be synchronous with its slave; anyway, it is useless when

inverters are far among them since signals could not travel properly. Thus, this solution can

be realized in small environment, where inverters are positioned close to each other.

2.1 Simulink model

11

Case study

Unlike previous chapter, this tries to introduce a completely different approach:

eliminating the transformers, it acts on the modulation of the inverters. This procedure

should allow to reduce the zero-sequence circulating current and different configurations

have been investigated.

Simulink model

To start, it is useful to introduce which is the Simulink model that has been implemented.

It is described in a general way, in the first part, then it goes more in detail focusing on each

modulation both for 2Level and 3Level inverter.

2.1.1 General model description

The presented model has been realized using Simulink blocks, but each scheme has been

drawn as new. It contains a parallel path of two identical inverters with a LCL filter in series.

Moreover, there is a path on the DC side made up with a connection, for each inverter, of the

negative pole to ground through the parasitic capacitance. Then, there is a point of common

connection on the AC side where a block, representing the grid, is connected. As Figure 2.1

depicts, the capacitances create a path where it is possible to measure the zero-sequence

circulating current through a current measurement block. In addition, each inverter gives as

output a three-phase voltage and a three-phase current as Figure 2.1 shows; it could seem that

they are measured after the LCL filter, but it will be described later how it actually works.

Regarding the parasitic capacitance, as said, it is the sum of that of each inverter.

1

𝐶𝑒𝑞=

1

𝐶𝑃𝑉1+

1

𝐶𝑃𝑉2 Eq. (2.1)

where:

• 𝐶𝑃𝑉1 and 𝐶𝑃𝑉2 are 10 μF, thus 𝐶𝑒𝑞 results 5 μF.

2 Case study

12

Figure 2.1 Simulink model.

Since Simulink world requires some specific blocks to make simulations work, in this case

powergui block has to be used in order to make electrical/power system blocks run. In

addition, this block allows to perform THD analysis of the signals and other functionalities.

Figure 2.2 Simulink powergui block.

For the used model and the simulations, a discrete solver has been used to discretize the

system with a sample time of 1𝑒−6 𝑠. Anyway, this situation is only valid in Simulink; in real

world is very difficult to acquire at a sample time of the μs.

Let’s now investigate on what Inverter, LCL filter and Grid blocks contain.

2.1 Simulink model

13

Inverter

It contains two topologies depending on 2Level or 3Level inverter. The only difference

between Inverter 1 and Inverter 2 is the IGBT signals coming from two different modulation

blocks. In Figure 2.3 and Figure 2.4, the two inverter topologies are represented. For this

model, DC voltage is kept constant: 𝑉𝐷𝐶_𝐵𝑢𝑠 = 700 𝑉.

Inverter parameters have been considered the same both for 2Level and 3level inverter.

Output Parameters Value

Nominal power 33kW

Max power AC 33.3 kVA

Nominal voltage AC 380 V

Switching frequency 10 kHz

Table 1 Inverter parameters.

2Level inverter has 6 IGBT/Diodes, 2 per each leg of the inverter and from the middle point of

each leg, phase A, B and C are derived respectively. IGBT/Diode receives as input a signal that

regulates its functioning in terms of open and close; port m of the block represents just current

and voltage measurements.

Figure 2.3 Simulink model of 2Level inverter.

2 Case study

14

Similarly, a 3Level inverter model has been built with 12 IGBT/Diodes and 2 freewheeling

diodes per leg. These specific diodes allow different current paths so to have all the

configurations proper of a 3Level inverter. Moreover, in this case, the DC voltage is divided in

two by a middle point connected then to the freewheeling diodes; this inverter is called Neutral

Point Clamped (NPC) inverter.

Figure 2.4 Simulink model of 3Level inverter.

2.1 Simulink model

15

LCL Filter

Unlike inverters, that can differ depending on model configurations, LCL filter is kept

always the same for any simulation. It is built with two inductances and a capacitance in a

T-shape model.

Figure 2.5 LCL Filter.

Figure 2.5 shows a three-phase inductance on the left called L1 and one on the right called L2.

A three-phase capacitance C, derived in the middle of the two inductances, is delta-connected.

There is then a last block: it is a three-phase measurement block that gives out phase-to-phase

voltages and line currents after L1.

Table 2 reports the parameters values.

Parameter Value

L1 660 μH

L2 330 μH

C (Δ-connected) 5 μF

Table 2 LCL parameters.

2 Case study

16

Grid

The block on the right in Figure 2.1 represents the equivalent grid. It contains a

Three-Phase Programmable Voltage Source that simulates the grid and other functions useful

for the rest of the model.

Figure 2.6 Equivalent grid.

GRID block imposes: 𝑉𝑔𝑟𝑖𝑑,𝑅𝑀𝑆,𝑝ℎ−𝑝ℎ = 380 𝑉 and 𝑓𝑔𝑟𝑖𝑑 = 50 𝐻𝑧.

A three-phase measurement block, which receives, on the left, a three-phase line after the point

of common connection, is used for three-phase voltage and current measurements.

Then, voltage is used for two goals:

• it is transformed in dq0-components, through a Park transformation block, so to have

𝑉𝑑_𝑔𝑟𝑖𝑑 , used for the current controller equation. (0-component is also called

homopolar);

• it is the input of PLL block; the K block is a gain of value 1/380 just to make the PLL

work better. PLL (Phase Locked Loop) is used to track the frequency and phase of a

sinusoidal three-phase signal and it has as input the vector containing the normalized

three-phase signal and as outputs: measured frequency [Hz] and ramp 𝜔 ∙ 𝑡 varying

between 0 and 2π, synchronized on zero crossings of the fundamental (positive-

sequence) of phase A.

2.1 Simulink model

17

2.1.2 Current controller

The control is carried out on dq0-axes and it is the same independently on the modulation

adopted. The only difference stays in the output voltage: for SPWM it is on abc-components

while for SVM on αβ-components. This is well shown in Figure 2.7, where both

transformations are considered.

Figure 2.7 Current controller.

The inverter output abc three-phase current, in Figure 2.1, is transformed in dq0-components;

this allows PI controllers to work better using continuous signals. Then, measured dq0-

currents are compared with reference ones. These are chosen so to obtain the desired current

values at the inverter output. From Table 1, it is possible to derive the inverter output current

of each phase.

𝐼𝑅𝑀𝑆 =

𝑃3

𝑉𝑅𝑀𝑆,𝑝ℎ−𝑝ℎ

√3

=

33000 𝑊3

380 𝑉

√3

= 50 𝐴 Eq. (2.2)

Since Simulink works with peak values, it has been chosen 𝑖𝑑_𝑟𝑒𝑓 = √2 ∙ 50 𝐴 while 𝑖𝑞_𝑟𝑒𝑓 =

𝑖0_𝑟𝑒𝑓 = 0 𝐴; this generally allows to generate a balanced abc three-phase current if the PI

controllers are well regulated. The difference of the two currents, on d-, q- and 0-axis, gives an

error that becomes the input of a PI controller. PI is based on two parameters: 𝑘𝑝 and 𝑘𝑖,

proportional and integral term respectively. They have been derived thanks to the MATLAB

tool pidTuner. It gets as input the plant that has to be controlled and, regulating frequency and

phase margin, gives out the parameters of the controller.

2 Case study

18

In the case study many configurations exist but for each of them the d- and q-axis PI controller

remains the same; only 0-axis PI controller changes its parameters according to the considered

modulation.

Thus, the plant has been drawn based on the Simulink model.

Figure 2.8 Simulink model of a grid-connected inverter with current control loop.

The current controllers of the two inverters are equal, so here just one is shown. Since the

current for the control is measured after L1, the rest of the LCL filter and the Grid are

commented out (they don’t take part to the plant realization). Thus, L1 is the only quantity to

be considered in the PI parameters characterization. In addition, even the inverter and its

modulation should be considered; due to a fast response given by these blocks, it is assigned

gain equal to 1 to them. A simplified equivalent plant can be realized.

Figure 2.9 Simplified plant for PI controller.

2.1 Simulink model

19

To realize and run pidTuner, a short MATLAB script is written down.

𝐿1 = 660𝑒 − 6;

𝑠 = 𝑡𝑓 (′𝑠′);

𝑝𝑖𝑑𝑇𝑢𝑛𝑒𝑟 (1/(𝑠 ∙ 𝐿1)); Eq. (2.3)

It presents the open loop formula 1/(𝑠 ∙ 𝐿1) but the pidTuner processes the closed loop one

automatically.

𝐺𝑜𝑝𝑒𝑛−𝑙𝑜𝑜𝑝 = 1

𝑠 ∙ 𝐿1;

𝐺𝑐𝑙𝑜𝑠𝑒𝑑−𝑙𝑜𝑜𝑝 = 𝐺𝑜𝑝𝑒𝑛−𝑙𝑜𝑜𝑝

1 + 𝐺𝑜𝑝𝑒𝑛−𝑙𝑜𝑜𝑝=

𝑠 ∙ 𝐿1

𝑠2 ∙ 𝐿12 + 𝑠 ∙ 𝐿1=

1

1 + 𝑠 ∙ 𝐿1

Eq. (2.4)

In addition, in Eq. (2.3), the second line represents the definition of the s variable that

introduces to Laplace domain. This three code lines run a tool in which it is possible to regulate

controller type, domain, bandwidth and phase margin.

Figure 2.10 PidTuner interface.

Once frequency domain is selected, the bandwidth is decided considering that usually the

control loop, that is the inner one, is one decade below that of the outer loop, formed by the

inverter and its modulation. Since the inverter has a frequency of 10 kHz, 62800 rad/s, the

bandwidth is set to 6280 rad/s. This happens to allow the inverter to switch in time before it is

regulated. Then, the phase margin is chosen: a higher value ensures more robust system. Thus,

three simulations have been carried out from 𝜑 = 60° up to 𝜑 = 90°: they are the lowest and

highest values to ensure stability. φ stands for phase margin.

2 Case study

20

Figure 2.11 Bode diagram of Gclosed-loop with φ=60°.



Figure 2.11 to Figure 2.13 show the decreasing overshoot value at 𝑓𝑐𝑢𝑡−𝑜𝑓𝑓 , frequency at which

the slope turns to be -20 dB/dec, with increasing robustness of the system.

2.1 Simulink model

21

In addition, for different φ, PI parameters change.

Phase margin kp ki

60° 3.59 1.3e4

75° 4.004 6737

90° 4.144 455.5

Table 3 PI parameters: kp and ki.

Simulations in the following use the parameters obtained with φ=90°, for dq-axes only.

Once PI controllers are built, coupling terms are added together with the d-axis component of

the grid voltage. Now, it is possible to obtain the dq0-components of the modulating signal.

A further differentiation can be done: depending on SPWM or SVM, dq0 is transformed in abc

or αβ0 respectively. Finally, in Figure 2.7, an output port is shown called 𝑏_𝑠𝑤 𝑜𝑟 𝑘; it is the

control variable used for the modification of the SPWM or SVM respectively.

The proposed control scheme is based on the grid-connected inverter equations [17].There is

only one difference between scheme and equations: in the first a LCL filter in present while in

the equations only a L will be considered. This assumption can be done since the equivalent

inductance of the LCL filter varies less than 1% from the inductance of L1.

Starting from abc-components, through Park transformation (Appendix A), it is possible to

obtain dq-components of the voltage loop in Figure 2.8:

𝑣𝑑 = 𝐿 ∙𝑑 𝑖𝑑𝑑𝑡

− 𝜔 ∙ 𝐿 ∙ 𝑖𝑞 + 𝑉𝑑_𝑔𝑟𝑖𝑑 Eq. (2.5)

𝑣𝑞 = 𝐿 ∙

𝑑 𝑖𝑞

𝑑𝑡+ 𝜔 ∙ 𝐿 ∙ 𝑖𝑑 Eq. (2.6)

where:

• 𝑖𝑑 and 𝑖𝑞 are the d-axis and q-axis inverter currents, respectively;

• 𝑉𝑑_𝑔𝑟𝑖𝑑and 𝑉𝑞_𝑔𝑟𝑖𝑑are the d-axis and q-axis grid voltages, respectively;

• 𝑣𝑑 and 𝑣𝑞 are the d-axis and q-axis inverter output voltages, respectively;

and w is the grid angular frequency obtained by the PLL.

In Eq. (2.6), 𝑉𝑞_𝑔𝑟𝑖𝑑 is not considered since only d-component exists for balanced three-phase

voltages, as previously said.

2 Case study

22

Given Eq. (2.5) and Eq. (2.6), the aim is to adapt these equations to the real scheme in which

PI controllers appear.

𝑉𝑑 = (𝑘𝑝𝑑 +𝑘𝑖𝑑

𝑠) ∙ (𝑖𝑑

∗ − 𝑖𝑑) − 𝜔 ∙ 𝐿 ∙ 𝐼𝑞 + 𝑉𝑑_𝑔𝑟𝑖𝑑 Eq. (2.7)

𝑉𝑞 = (𝑘𝑝𝑞 +

𝑘𝑖𝑞

𝑠) ∙ (𝑖𝑞

∗ − 𝑖𝑞) + 𝜔 ∙ 𝐿 ∙ 𝐼𝑑 Eq. (2.8)

where:

• 𝑖𝑑∗ and 𝑖𝑞

∗ are the reference values for 𝑖𝑑 and 𝑖𝑞, respectively;

• 𝑘𝑝𝑑 and 𝑘𝑖𝑑 are the d-axis proportional and integral terms of the PI controller;

• 𝑘𝑝𝑞 and 𝑘𝑖𝑞 are the q-axis proportional and integral terms of the PI controller.

In Figure 2.7 there is a last block to be analysed: LP. It represents a low-pass filter block used

to filter out higher frequencies in the 0-axis current measure. Since switching frequency is

10 kHz, the time constant τ of the filter has been assumed equal to 5𝑒−4 𝑠, 2 kHz.

Anyway, this block has only been used for SVM. It came in help since, as results will show, this

modulation presents more distorted waveform of 0-axis current with respect to SPWM; thus,

eliminating some higher frequencies, that can further distort the signal, can be an advantage

as the signal enters the PI controller. The same reasoning can be carried out for SPWM: it

seems not to need this additional block since its 0-axis signal already presents a very low

contribution.

Furthermore, it is to say that previous assumptions are not completely true; until now, they

are valid only from a simulation point of view. As mentioned, the model acquires each 1𝑒−6 𝑠,

that means 1 MHz of sampling frequency. In real life, sampling frequency stays around

10÷20 kHz for common technologies or can reach 50÷100 kHz for advanced ones. If these

frequencies were considered, there would be a change in the model parameters such as PI

terms and time constant of the low-pass filter on 0-axis.

2.1 Simulink model

23

2.1.3 Inverter modulations

Continuing the model description, the output waveforms of the current controller are the

input modulating signals for any modulation. Thus, the latter ones are introduced.

Sinusoidal Pulse Width Modulation

Sinusoidal PWM is the easiest modulation to be implemented since it works with

abc-components, as modulating signal, compared with a triangular carrier signal. In the case

study, a small variation occurs since a modification in the modulation is necessary.

Figure 2.14 SPWM and Current controller.

In Figure 2.14, modulations of both the inverters are taken into account. As in Figure 2.7,

parameter 𝑏_𝑠𝑤 appears: it is used to modify the triangular carrier signal; it enters the

modulation block called PWM. Two parameters exist so it is possible to modify only one of the

inverters or both. If only Inverter 1 modulation is modified, it means that Inverter 2 has to

work dependently on Inverter 1, to ensure that no ZSCC flows, as it was a master-slave

configuration. The second solution allows more independence between them and each inverter

can work with its own correction. This is useful when number of inverters increases since it

becomes difficult to make many inverters follow only one.

2 Case study

24

Now, the modulation block can be analysed in depth: as mentioned, 2Level and 3Level

inverters are under study thus both the modulations are considered.

The former is easier since it presents the modulating signal and only one triangular carrier

signal. In our case, another block has been realized: it allows the modification of the triangular

waveform.

Figure 2.15 2Level inverter SPWM with modified triangular carrier signal.

The three input ports va, vb and vc represent the modulating signals coming from the current

controller; port 𝑏_𝑠𝑤 carries the 0-axis error that acts as to correct the new triangular carrier

signal in Triangular carrier signal modified block. Block vt is the ideal triangular waveform built

with a repeating sequence block: it needs only the period and the amplitude of the wave. In this

case are given 3 points for the time values [0 𝑇𝑠/2 𝑇𝑠], where 𝑇𝑠 is the switching period

equivalent to (1/𝑓𝑠), 𝑓𝑠 stands for switching frequency, and at each point corresponds an output

value as the amplitude of the waveform [-𝑉𝐷𝐶 𝑉𝐷𝐶 -𝑉𝐷𝐶], where 𝑉𝐷𝐶 is the DC bus voltage.

For what concerns the modified waveform, it is not a default block.

It is built with the target not to modify the triangular waveform itself but to make it follow

specific lower and upper limits depending on the incoming 0-axis error. This allows a different

modulation since the sinusoidal modulating waves will intercept different points of the

triangular wave giving as output different PWM signals.

2.1 Simulink model

25

Figure 2.16 2Level Triangular carrier signal modification block.

Simulink model, in Figure 2.16, presents two integrator blocks: both receive, as external initial

conditions, 𝑏_𝑠𝑤 and then a Boolean signal from the comparator shown in the lower part. The

third input is a constant value 2 ∙ 𝑉𝐷𝐶_𝐵𝑢𝑠 ∙ 𝑓𝑠 for the upper integrator while the same parameter

multiplied by a square wave for the lower one. The upper integrator generates a sawtooth,

since it integrates a constant value: each period, the sawtooth reaches the maximum while its

lower value is modified by the external condition given by 𝑏_𝑠𝑤. The obtained sawtooth signal

is compared twice: first, with 2 ∙ 𝑉𝐷𝐶_𝐵𝑢𝑠 and it always results lower giving as output a 0 Boolean

value so that the integrators always rise from 0 to a positive value; second, it is compared

with𝑉𝐷𝐶_𝐵𝑢𝑠 to generate a square waveform. This signal is multiplied by 2 ∙ 𝑉𝐷𝐶_𝐵𝑢𝑠 ∙ 𝑓𝑠 and goes

in the lower integrator thus to transform a square wave into a triangular wave, modified

according to 𝑏_𝑠𝑤. This path includes a memory block, that gives out the input from the

previous time step, applying a one integration step sample-and-hold to its input signal.

Finally, the signal is scaled so to have a waveform between −𝑉𝐷𝐶_𝐵𝑢𝑠 and +𝑉𝐷𝐶_𝐵𝑢𝑠.

Back to Figure 2.15, after the carrier signal explanation, it is possible to see how it is compared

with the modulating signals. It happens, on each phase, through a comparator that gives as

output the signal directed to the upper IGBTs in Figure 2.3, if the comparison is verified,

otherwise, the negated signal goes to the lower IGBTs in Figure 2.3.

2 Case study

26

A similar modulation is carried out for the 3Level inverter. The main difference is in the

triangular carrier signal. Since, in this case, the inverter has to provide three level of voltage at

its output, two triangular carrier signals are used.

Figure 2.17 3Level inverter SPWM with modified triangular carrier signals.

The logic is identical to that of 2Level inverter: there is a block in which the triangular carrier

signals are modified and then they are compared with the modulating signals to give out the

PWM ones.

In the block 𝑣𝑡 + / 𝑣𝑡 − the modification occurs according to the following scheme: both

triangular signals are modified on the basis of 𝑏_𝑠𝑤. The sub-plots equal Figure 2.16 apart

from the fact that the upper one regulates the positive triangular wave and the lower the

negative one. In addition, it is possible to select also the ideal triangular carrier signal.

2.1 Simulink model

27

Figure 2.18 3Level inverter modified triangular carrier signals.

To go more in detail, it is possible to show what the two above blocks contain and how the

modification of the 3Level triangular carrier signal happens.

Figure 2.19 3Level Triangular carrier signals modification block.

It is immediate to see that the implementation is the same for the two signals; only the last

step differs so that to give a positive and a negative signal respectively.

2 Case study

28

Then, Comparator block is analysed: it contains the modulating and the two triangular carrier

signals giving out the twelve IGBT ones. For each phase, the signal, coming from comparison

with the 𝑣𝑡 +, commands the first and the third IGBT of the same leg while the signal from

𝑣𝑡 −commands the second and the fourth IGBT of Figure 2.4.

Figure 2.20 3Level inverter SPWM comparator.

2.1 Simulink model

29

Space Vector Modulation

SVM presents solutions both for 2Level and 3Level inverter. In this case are studied

modulations that act both on modulating and carrier signals.

First, an overview on how SVM is implemented.

Figure 2.21 SVM and Current controller.

Like SPWM, also here two parallel modulations are considered. From the current controllers,

the αβ modulating signal and two parameters called 𝑏_𝑠𝑤 and k are obtained. The former is

used for 2Level and 3Level inverter; the latter to modify the modulation itself only in 2Level

inverter and will be presented in Chapter 4.

The case of 𝑏_𝑠𝑤 is very similar to SPWM: the generation of modulating signal is unvaried

while the triangular one is modified. The only difference stays in the amplitude of the carrier

signal. In fact, it is assumed to be 𝑇𝑠/2 thus the modulating signal, out of the SVM, has the

same order of magnitude.

Figure 2.22 shows that the modulating signal doesn’t come directly from the current controller

as sinusoidal three-phase signal: in fact, it introduces S-function block called SVM_2L. It

contains a C-code that describes how SVM is implemented, based on the classical theory [18].

Appendix B explains the theory and reports the C-code.

2 Case study

30

Figure 2.22 2Level inverter SVM modulation with modified triangular carrier signal.

Consider now 3Level inverter. The logic is the same as for previous explanation with only two

differences. The first is in the C-code, derived from theory in Appendix C; the other stays in

the number of output signals since 3Level inverter presents 12 IGBTs.

Figure 2.23 3Level inverter SVM modulation with modified triangular carrier signal.

2.1 Simulink model

31

Considerations on switching frequency

In the simulations, it has been decided to introduce a difference in the frequencies of the

two inverters so to recreate the real condition in which at least one inverter differs from the

reference switching frequency.

Figure 2.24 Frequency selection.

Due to this modification, it is important that the modulation still works in a real condition,

and not only when the two inverters have the same frequency.

The difference usually rises due to non-ideal oscillators that generate the frequencies. Anyway,

it is assumed very small: 𝑓𝑠 = 𝑓𝑠𝑤 = 10000 𝐻𝑧 and 𝑓𝑠𝑎 = 10001 𝐻𝑧. Thus, for example, Inverter

2 changes frequency according to Figure 2.24. In addition, since also Inverter 2 modulation

can be modified, when the triangular carrier signal modification occurs, Figure 2.16 and

Figure 2.19 receive as input the constant 2 ∙ 𝑉𝐷𝐶_𝐵𝑢𝑠 ∙ 𝑓𝑠𝑎 rather than 2 ∙ 𝑉𝐷𝐶_𝐵𝑢𝑠 ∙ 𝑓𝑠.

A further reasoning is carried out. From results it will appear that, modifying the inverter

whose frequency deviates mostly from 𝑓𝑠𝑤 is more efficient even than modifying both inverters.

When both are modified, a superposition of phenomena can occur worsening the modification

effect. Thus, a logic has been implemented to select the inverter whose modulation has to be

modified.

Figure 2.25 Logic of inverters modifications based on frequency selection.

2 Case study

32

Inverter 1 and Inverters 2 frequencies are respectively 𝑓𝑠1 and 𝑓𝑠2. They are compared with 𝑓𝑠

and the absolute value is considered. Then, when the difference 𝑓𝑠1 − 𝑓𝑠 is greater than 𝑓𝑠2 − 𝑓𝑠,

the comparator gives out a Boolean signal 1, otherwise 0. Then a switch is introduced: if the

Boolean signal is 1 the block switches on the upper signal vt while if it is 0 goes to vt_modified.

Instead, the other inverter has an inverse logic: the two blocks on the left are interchanged.

Anyway, it has to highlight that this logic can work well only in Simulink world and it has been

experimented with only two inverters; in practice, when the number of inverters increases, it

becomes difficult to make them communicate and to implement a logic that takes them all into

account. In addition, it can happen that many have the same frequency making a comparison

meaningless.

2.2 Modified SPWM

33

Modified SPWM

SPWM modification principle is introduced.

Figure 2.26 SPWM triangular carrier signal modification.

The main idea is to optimize the value of 𝑏_𝑠𝑤 so that the modulation allows a significant

reduction of the zero-sequence circulating current. As Figure 2.14 shows, both inverters

modulations can be modified by 0-axis error; this is true and useful when more inverters are

considered in parallel instead of having many inverters relying on just one. So, it is possible to

define, with enough accuracy, the values 𝑏_𝑠𝑤 assumes for both 2Level and 3Level inverter.

SPWM kp0 ki0

2Level Inverter 20 10

3Level Inverter

Table 4 0-axis PI parameters for SPWM.

Figure 2.26 shows a PI controller also on 0-axis and it hadn’t already been defined. Thus, Table

4 reports which are the parameters. The choice was to adopt a certain value of proportional

term so that 𝑏_𝑠𝑤 reaches the right quantity, modifying the triangular carrier signal in the most

proper manner. Since the triangular waveform exists between ±𝑉𝐷𝐶_𝐵𝑢𝑠, equal to ±700 V, and

the 0-axis error is around 1 V, 𝑘𝑝0 = 20 seems to be an appropriate value to modify the

triangular wave. Then, 𝑘𝑖0 = 10 has been chosen for the integral part: it is a quite low value

since the error already starts and evolves around 0, thus it doesn’t need a strong contribution

from this term.

2 Case study

34

Modified SVM

The technique presented for SPWM is also valid for SVM, even if the second is controlled

with αβ quantities rather than abc ones.

Figure 2.27 SVM triangular carrier signal modification.

As SPWM, the error on 0-axis is used to correct the triangular carrier signal. Anyway, in this

case, it assumes a completely different value that is between 0 and 𝑇𝑠/2: this means that the

correction has to be low enough to get compared with the carrier signal.

SVM kp0 ki0

2Level Inverter 5e-6 1e-7

3Level inverter

Table 5 0-axis PI parameters for SVM.

The presented values are already reported to the order of magnitude of 𝑇𝑠; they can also be

rewritten as 𝑘𝑝0 = 5𝑒−2 and 𝑘𝑖0 = 1𝑒−3 considering an additional gain equal to 𝑇𝑠 into the

model.

Figure 2.28 0-axis PI controller with Ts.

3.1 SPWM

35

TEST RESULTS

This chapter contains the results obtained by the simulations. Its intent is to show how

the different techniques behave and their comparison to the cases in which they are not

adopted. Many configurations will be analysed so to consider different scenarios.

SPWM

Results for both 2Level and 3Level inverter configurations follow. The measured

quantities are the same, so to understand which modulation behaves better. To simplify the

description, it is introduced the Simulink model containing the measurement blocks of the

considered quantities. They report inverter voltages and currents, grid voltages and currents,

dq0-axes voltages and currents and especially the zero-sequence circulating current, the

quantity under analysis. The cited dq0-components regard the transformed abc inverter

currents used for the current control and their relative errors. After the PI controllers, dq0

errors of the voltages are obtained and d-axis grid voltage is added. In the end, the dq0 voltages

are transformed on abc-axes and become the modulating signals of the PWM. The simulation

is run according to model in Figure 3.1.

3 Test results

36

Figure 3.1 Measured quantities in the Simulink model.

3.1 SPWM

37

3.1.1 2Level Inverter

First, the ideal case with the same frequency for the two inverters is analysed. Since it

already presents a sort of correction, due to synchronization of the triangular carrier signals,

all the quantities behave as expected.

Figure 3.2 2Level SPWM Inverter 1 voltages and currents; same frequency.

Figure 3.3 2Level SPWM Inverter 2 voltages and currents; same frequency.

As Figure 3.2 and Figure 3.3 show, the two inverters have the same trend both in voltages and

currents. Then, since the grid is connected to the inverters output, it imposes its voltage and,

thanks to Table 1, it is also possible to derive inverter output current.

3 Test results

38

Figures show the maximum values as default; thus, voltage and current are:

�̂�𝑖𝑛𝑣 1,𝑝𝑒𝑎𝑘,𝑝ℎ−𝑝ℎ = �̂�𝑖𝑛𝑣 2,𝑝𝑒𝑎𝑘,𝑝ℎ−𝑝ℎ = √2 ∙ 𝑉𝑔𝑟𝑖𝑑,𝑅𝑀𝑆,𝑝ℎ−𝑝ℎ =

√2 ∙ 380 𝑉 = 537.4 𝑉 Eq. (3.1)

𝐼𝑖𝑛𝑣 1,𝑝𝑒𝑎𝑘 = 𝐼𝑖𝑛𝑣 2,𝑝𝑒𝑎𝑘 = √2 ∙

𝑃

√3 ∙ 𝑉𝑔𝑟𝑖𝑑,𝑅𝑀𝑆,𝑝ℎ−𝑝ℎ

=

√2 ∙ 33000 𝑊

√3 ∙380 𝑉 = 71 𝐴

Eq. (3.2)

About currents, their waveforms present a first transient until 0.02 s: at this time, one period

of the grid frequency, 𝑓𝑔𝑟𝑖𝑑 = 50 𝐻𝑧, the PLL starts working and another short transient occurs

until the steady state is reached. In addition, it is important to notice that currents present

ripples at the inverter frequency; this case 10 kHz.

Figure 3.4 Current ripples.

3.1 SPWM

39

Before proceeding with the analysis of the currents, it can be introduced a power

measurement, as in Figure 3.1. To cancel out ripples and higher frequencies of P and Q, two

low-pass filters are used with a time constant of 1𝑒 −2 𝑠. Results respect values in Table 1.

Figure 3.5 Inverter active and reactive power.

Next step is to analyse how currents are generated and how their control is carried out. This

means to transform them on dq0-axes and compare with reference values, with consequent

errors and compensations. Figure 3.6 presents dq0-axes inverter currents, dq0-axes current

errors, before the PI controllers, and dq0-axes voltage errors, after the PI controllers,

respectively. This result is valid for both inverters.

Figure 3.6 2Level SPWM current controller quantities.

3 Test results

40

Each subplot of Figure 3.6 shows significant results. In the first one, only d-axis component,

in blue, exists due to the symmetry in abc currents while q-component, in red, presents only

some ripples around 0; 0-component, in green, stays on 0.

Figure 3.7 2Level SPWM inverter dq0 currents.

The second subplot zooms on the comparison between measured values and reference ones: it

gives out dq0 errors. They assume values around 0: it means that the measured values match

the references and control works well.

Figure 3.8 2Level SPWM inverter dq0 errors.

3.1 SPWM

41

PI outputs are voltages on dq0-axes.

Figure 3.9 2Level SPWM PI controller outputs.

Figure 3.10 is similar to Figure 3.9 with the addition of d-axis grid voltage and coupling terms

as

Eq. (2.7) and Eq. (2.8) state.

Figure 3.10 2Level SPWM dq0 voltages.

From Appendix A, d-axis can be derived, considered that plots show peak values.

3 Test results

42

𝑉𝑑_𝑔𝑟𝑖𝑑 = √2 ∙ 𝑉𝑔𝑟𝑖𝑑,𝑅𝑀𝑆,𝑝ℎ−𝑝ℎ = √2 ∙ 380 𝑉 = 537.4 𝑉 Eq. (3.3)

Their relevance can be understood better as they are transformed on abc-axes and then

compared with the triangular carrier signal.

Figure 3.11 Comparison between modulating and carrier signals.

The intersection of the sinusoidal modulating signal with the triangular carrier one gives PWM

signal to IGBTs. When the sinusoidal is greater than the triangular, IGBT conducts, on the

contrary it doesn’t.

Once inverters have been analysed, grid quantities are introduced.

As already said, voltages are imposed by the grid, thus they are balanced three-phase voltages;

currents, instead, are the sum of the two currents coming from the inverters.

3.1 SPWM

43

Figure 3.12 2Level SPWM grid voltages and currents.

The last quantity under analysis is the zero-sequence circulating current. It is measured

between the two negative poles of the DC buses, through the parasitic capacitances of the PV

panels.

Figure 3.13 2Level SPWM ZSCC; same frequency.

Figure 3.13 shows how the ZSCC behaves in presence of two inverter with the same frequency;

it has a low amplitude, even if presents a superposition of many frequencies. This is due to

different phenomena in the model such as 50 Hz and 10 kHz signals and the cut-off frequency

of the equivalent LC filter. The latter exists due to the loop including the two inductances of

the LCL filters, C is neglected since it is Δ-connected, and the parasitic capacitances that are

assumed in series.

3 Test results

44

Figure 3.14 Equivalent LC filter.

The inductances have been divided by 3 since they are compared with a homopolar

capacitance.

Thus, the resonance frequency in the loop can be derived according to the following equations.

𝜔0 = 1

√𝐿𝐶𝑃𝑉

Eq. (3.4)

𝐿 = 2 ∙ (𝐿1

3+

𝐿2

3) = 660𝑒−6 H Eq. (3.5)

𝐶𝑃𝑉 =

1

1𝐶𝑃𝑉1

+1

𝐶𝑃𝑉2

= 5𝑒−6 F Eq. (3.6)

𝑓0 =𝜔0

2𝜋 =

1

2𝜋 ∙ √𝐿𝐶𝑃𝑉

= 2770.5 Hz Eq. (3.7)

In addition, other frequencies are generated due to the combinations of 50 Hz,10 kHz and

2770.5 Hz, according to Prosthaphaeresis Formulas.

sin 𝛼 + sin 𝛽 = 2 ∙ sin𝛼 + 𝛽

2∙ cos

𝛼 − 𝛽

2 Eq. (3.8)

This will introduce: 4975 Hz, 5025 Hz, 3614.75 Hz, 6385.25 Hz, 1360.25 Hz,1410.25 Hz. Anyway,

these values are just as reference since the ones in the simulations deviate of some Hz.

3.1 SPWM

45

Once the ideal case has been studied, the difference in frequencies is introduced. In this case,

the model without and with the modification of the triangular carrier signal is presented to

make a comparison and understand if some advantages are brought.

The first step doesn’t consider the modification; Inverter 2 frequency is assumed 1 Hz higher

than the other: this implies a shift in the two triangular carrier signals. The unbalance

introduces oscillations in current ripples for both inverters. Anyway, the two inverters balance

each other so to give out to the grid a perfect three-phase current as previously happened.

Figure 3.15 2Level SPWM Inverter 1 currents; different frequencies.

This phenomenon can be better noted moving on dq0-axes; it happens identically for both

inverters.

3 Test results

46

Figure 3.16 2Level SPWM inverter dq0-quantities; different frequencies.

Unlike Figure 3.6, 0-axis component presents a great contribution in this case. In addition,

even dq0-axes modulating signal contains the oscillation due to different frequencies.

Figure 3.17 2Level SPWM inverter dq0 voltages; different frequencies.

Since they are not constant anymore, abc sinusoidal waveforms won’t be a perfect three-phase

signal. Below, the high frequency triangular carrier signal is compared to 50Hz modulating

one.

3.1 SPWM

47

Figure 3.18 2Level SPWM modulating and carrier signals; different frequencies.

The unbalance can be also seen in the ZSCC, as expected. It presents an oscillating waveform

that doesn’t move between a constant band of values and in addition reaches 16 A, that is much

higher than the 0.8 A of the previous case.

Figure 3.19 2Level SPWM ZSCC; different frequencies.

This is due to 𝛥𝑓, the difference between the two inverters frequencies: 𝛥𝑓 = |𝑓𝑠 − 𝑓𝑠𝑎|. Since

they differ of 1 Hz, the two waveforms get aligned after a cycle in 1 s.

3 Test results

48

To demonstrate the theory in Modified SPWM, the results including the modification are

introduced. Regarding the inverter output currents, since the PI controllers result to work well,

they follow the reference and behave good for both inverters.

Figure 3.20 2Level SPWM inverter output waveforms; different frequencies with correction.

Anyway, the focus is on the ZSCC; an improvement has to be obtained with respect to the

previous case and Figure 3.21 and Figure 3.22 can demonstrate that the modification actually

works. As already explained in paragraph 2.1.3, there is the possibility of modifying just one

inverter or both.

Figure 3.21 2Level SPWM ZSCC; different frequencies with modification using b_sw1.

3.1 SPWM

49

Figure 3.22 2Level SPWM ZSCC; different frequencies with modification using b_sw1 and b_sw2.

In both cases, the modification works, if they are compared with Figure 3.19. Anyway, when

both inverters are modified, ZSCC presents more peaks at higher values then the case in which

only one is modified. This doesn’t mean that the technique is not efficient, but it tells that a

trade-off shell be considered between having lower values of current or more freedom in

controlling the inverters.

Previous plots have been obtained using the technique of triangular carrier signal modification

presented in Figure 2.16. In fact, the carrier signal presents a different shape with respect the

ideal one and it makes sense to show how it happens and especially how it is related with the

modulating signals.

Figure 3.23 Triangular carrier signal.

3 Test results

50

As Figure 3.23 shows, there is a difference between the two waveforms; while the first behaves

as a perfect triangular wave bounded between ±700 V, the second one oscillates of some Volt

according on 𝑏_𝑠𝑤. The oscillation occurs around the lower limit since the modification block

just acts on those values, while the upper one never goes beyond 700 V.

Figure 3.24 reports how the sinusoidal modulating signals intercept the new carrier one

differently to Figure 3.11.

Figure 3.24 Modulating signal compared with Modified triangular carrier signal.

A last consideration can be done: since PV panels can’t work exactly at the same conditions

due to shadowing, or weather uncertainty, or other factors, it can be assumed that the two DC

buses could have different voltages. A difference of 50 V is introduced, 𝑉𝐷𝐶_𝐵𝑢𝑠2 = 650 𝑉. In

order to simplify the following explanation, data are collected in a table; values are expressed

as peak values.

Table 6 2Level SPWM different VDC_Bus.

Concerning the other quantities, such as currents and voltages, the current controllers behave

as to make them follow the same waveform as it happened when equal DC buses where

considered.

It is useful to report also a table of the case with same 𝑉𝐷𝐶_𝐵𝑢𝑠.

Quantity Same

frequency

Different frequencies

No modification Modification

b_sw1 b_sw1 & b_sw2

ZSCC 1.8 A 15 A 3.5 A 5 A

3.1 SPWM

51

Quantity Same

frequency



b_sw1 b_sw1 & b_sw2

ZSCC 0.5 A 16 A 2 A 3 A

Table 7 2Level SPWM same VDC_Bus.

A further study to understand better the improvement brought by the modification regards the

THD analysis. Through powergui, it is possible to make the FFT (Fast Fourier Transform)

analysis and obtain the percent THD. It is computed on phase A of the currents.

THD Grid Inverter 1 Inverter 2

Without modification 1.55 % 6.41 % 6.25 %

With modification 1.18 % 5.24 % 5.29 %

Table 8 2Level SPWM percent THD.

The inverters currents high values are due to ripples; anyway, the modification seems to

improve of 1% the THD. About grid currents, THD improvement is small and this means that

the LCL filters out well the ripples so to have an acceptable value of grid currents THD.


This paragraph deals with the same arguments and results as the previous one. It contains

an analysis of currents and voltages and then a comparison between the different ZSCCs

depending on the configuration adopted.

First, the case in which the inverters have the same frequency is considered. As for 2Level,

current controllers result to work well and both inverters present good output waveforms.

3 Test results

52

Figure 3.25 3Level SPWM inverter voltages and currents; same frequency.

This configuration also ensures good grid quantities, as Figure 3.12.

Regarding the ZSCC, since still no frequency variation exists between the two inverters, it

presents very low amplitude as expected.

Figure 3.26 3Level SPWM ZSCC; same frequency.

The situation completely changes when the difference is applied. This provides an unbalance

in the system as occurred for 2Level and the results get modified.

It is immediately visible in the current waveforms: at steady state, they present a light

distortion near the peaks.

3.1 SPWM

53

Figure 3.27 3Level SPWM grid steady-state currents; different frequencies.

Even dq0-quantities provide an additional example of how the difference in frequencies

disturbs the system. Thus, dq0 voltages are shown. While dq-axes show non-constant

quantities, 0-axis reports the 1 Hz harmonic with a significant high amplitude.

Figure 3.28 3Level SPWM inverter dq0 voltages; different frequencies.

The precedent problems are obviously present also in the ZSCC. Its waveform is not bounded

between considerable small values and behaves as Figure 3.19.

3 Test results

54

Figure 3.29 3Level SPWM ZSCC; different frequencies.

It is now to introduce the results obtained thanks to the modification and show the

improvement in each quantity. First, it happens for the grid currents as Figure 3.30 shows in

comparison with Figure 3.27.

Figure 3.30 3Level SPWM grid currents; different frequencies with modification.

The goodness of the adopted method can be further demonstrated by showing how ZSCC

changes. It is reported the modification acting on one inverter and on both.

3.1 SPWM

55

Figure 3.31 3Level SPWM ZSCC; different frequencies with modification using b_sw1.

Figure 3.32 3Level SPWM ZSCC; different frequencies with modification using b_sw1 and b_sw2.

In this case, using both modifying parameters means to have a worse initial transient,

acceptable due its short duration.

As for previous paragraph, also 3Level presents a configuration in which one of the two DC

buses differs from the other of 50 V. The results are resumed in a table, together with those of

same DC buses case.

Quantity Different frequencies

3 Test results

56

Same

frequency No modification

Modification

b_sw1 b_sw1 & b_sw2

ZSCC 1 A 11 A 1.5 A 2 A

Table 9 3Level SPWM different VDC_Bus.

Quantity Same

frequency



b_sw1 b_sw1 & b_sw2

ZSCC 0.25 A 11 A 1 A 0.5 A

Table 10 3Level SPWM same VDC_Bus.

As before, the THD analysis can be carried out. It is computed on phase A of inverters and grid

currents.




Table 11 3Level SPWM percent THD.

Also in this case, 1% less is obtained for inverters currents and especially grid currents THD

goes below 1%.

SVM

In the following paragraph, it has been used the scheme of Figure 3.1 with the only

difference that Current Controller blocks produce αβ-components, in this case, instead of abc-

ones. The aim is to investigate the same quantities of SPWM to highlight similarities and

differences and understand if SVM behaves as well as SPWM. Both 2Level and 3level inverters

will be analysed and many results will be reported according to all the modifications.

3.2 SVM

57


The first case considers same frequency for the two inverters without any modification.

Unlike SPWM, SVM already presents some problems regarding the ZSCC; in fact, it is not

limited at all and shows peaks of the order of tens of Ampere.

Figure 3.33 2Level SVM ZSCC; same frequency.

As known, ZSCC is proportional to current ripples, in turn, proportional to the homopolar-axis

current. When no modification occurs, this signal passes unvaried in the current controller

and is a part of the modulating signals when they are transformed in αβ-components. The

latter ones generate, through the S-function, signals containing that error and the comparison

with the carrier signal doesn’t result clean; this happens in a worse way with respect to SPWM.

The mentioned closed loop influences each quantity, and ZSCC results as showed. A solution

to reduce the ripples would be to increase L1 but it results in changing the LCL filter, that is a

hardware solution.

This result will influence the other quantities, especially the inverter output ones. In fact,

currents present an increase in the ripple peaks exactly when the amplitude of the ZSCC

increases.

3 Test results

58

Figure 3.34 2Level SVM inverter currents; same frequency.

Figure 3.35 shows better how currents are modified in terms of ripples; dq0-axes currents can

be reported as a proof that homopolar current can’t be negligible.

Figure 3.35 2Level SVM inverter dq0 currents; same frequency.

Anyway, thanks to the LCL filters, the abc currents injected into the grid will not result

distorted anymore. They are, as always, the sum of the two inverters currents.

3.2 SVM

59

Figure 3.36 2Level SVM grid voltages and currents; same frequency.

Moving to the modulation itself, notice that it differs from SPWM. The comparator works with

the same logic, but the inputs are different. The modulating signals are the IGBTs reference

times of each phase, from the S-function, while the triangular carrier signal varies between 0

and 𝑇𝑠/2, where 𝑇𝑠 is the switching period.

Figure 3.37 2Level SVM modulating signal vs triangular carrier signal.

Inverter 2 frequency is now changed. Before applying any modification, it is interesting to

report how ZSCC behaves.

3 Test results

60

Figure 3.38 2Level SVM ZSCC; different frequencies.

It shows that after 1 s a cycle is completed according to the 1 Hz difference between the two

inverters frequencies, as it happened for SPWM in Figure 3.19.

In the following, the modifications are introduced. Unlike SPWM, that presented only two

cases, now, a third one is considered. This is due to a non-perfect achievement of the expected

results. In fact, if Inverter 1 is modified, a further oscillation at approximately 10 Hz is added

to the waveform and its peaks reach values around 15 A.

Figure 3.39 2Level SVM ZSCC; different frequencies with modification using b_sw1.

Then, the modification on both inverters ensures a small improvement in the ZSCC.

3.2 SVM

61

Figure 3.40 2Level SVM ZSCC; different frequencies with modification using b_sw1 and b_sw2.

Even if in the first transient it seems to show relatively low values, the waveform increases up

to 15 A not leading to a good result in terms of limited amplitude.

The goal is obtained adding a new modification that interests only the inverter whose

frequency is changed. In fact, modifying only Inverter 2, a better result occurs.


ZSCC has now a bounded trend within considerably low values with respect to those obtained

in the previous cases. Anyway, it is a must to say that this solution can’t be considered in

practice: often it is difficult to know which inverter has to be modified and there can be more

than two inverters.

3 Test results

62

As done for SPWM, even for SVM, the case of different DC buses is studied. When no

modifications are adopted, both for same and different frequencies, the ZSCC presents high

peaks. Otherwise, considering the three modifications, the results are almost the same.

Quantity Same

frequency


No

modification

Modification

b_sw1 b_sw1 & b_sw2 b_sw2

ZSCC 20 A 35 A 15A 15 A 8 A

Table 12 2Level SVM different VDC_Bus.

Quantity Same

frequency


No

modification

Modification


ZSCC 25 A 30 A 15A 15 A 5 A

Table 13 2Level SVM same VDC_Bus.

Then, THD values of currents, when modification on both inverters is considered, are

reported. Even if the solution doesn’t bring to optimal results, the THD analysis presents an

enhancement when the modification of the inverter is adopted.




Table 14 2Level SVM percent THD.

As a conclusion for this paragraph, it can be stated that the modification of the triangular

carrier signal doesn’t result so efficient since the only positive result is obtained when only the

inverter, whose frequency is changed, is modified; as said, this is difficult to implement in

practice.

3.2 SVM

63


The procedure is the same of the 2Level case. First, the analysis of two inverters with the

same frequency is carried out. The ZSCC is reported as follow, introducing the same problem

as 2Level did, even if up to 0.8 s ZSCC is 0.

Figure 3.42 3Level SVM ZSCC; same frequency.

As usual, this high amplitude is correlated with the inverter current ripples that increases

accordingly.

Figure 3.43 3Level SVM inverter voltages and currents; same frequency.

3 Test results

64

Anyway, as happened before, LCL filter acts to eliminate these ripples and to make clean

waveforms flow into the grid. Thus, grid currents behave as Figure 3.36.

Before introducing the results with any modification, ZSCC behaves even worse with respect

2Level when 𝑓𝑠𝑎 = 10001 𝐻𝑧.

Figure 3.44 3Level SVM ZSCC; different frequencies.

In the following there is how modulation works: it is like 2Level SVM, but, due to increased

number of the IGBTs, more signals are present: S-function gives as output 6 signals to be

compared with the triangular carrier one, already modified in the following.

Figure 3.45 3Level SVM modulating signals vs modified triangular carrier signal.

In Figure 3.45, first plot shows three signals, one per phase; each one controls the upper IGBT

in the leg and, when negated, the third one from the top. The same happens for the second

plot: they control the second IGBT from the top and the lower one, when negated.

3.2 SVM

65

This is the equivalent of Figure 3.37. Here, waveforms are less smooth; it is for the modulation

index basically. In fact, if a higher modulation index was adopted, they would show a less

evident discontinuity; it can be demonstrated by simulations as well. In our case, this

discontinuity, when a step of around 1𝑒−5 𝑉 occurs, is due to the change of sector, typical of

the SVM.

Modification of the triangular carrier signal, compared with the IGBTs reference times, has

been introduced; now, even for 3Level, three different modifications are analysed.

First, only Inverter 1 is modified and ZSCC presents high peaks around 12 A.


Since it doesn’t get the goal, 2 inverters are modified, and it introduces a quite good match.

Figure 3.47 3Level SVM ZSCC; different frequencies with modification using b_sw1 and b_sw2.

In this case, ZSCC reaches 4 A with some peaks up to 8 A but, at least, results bounded between

limited values.

3 Test results

66

Modification of only Inverter 2 has been studied and it brought to similar results as

Figure 3.47 with a small decrease in amplitude.


Last, resuming tables are built up to show the differences in the case of different DC buses for

the two inverters. Then percent THD values are also reported.

Quantity Same

frequency


No

modification

Modification


ZSCC 50 A 50 A 12 A 8 A 8 A

Table 15 3Level SVM different VDC_Bus.

Quantity Same

frequency


No

modification

Modification


ZSCC 13 A 60 A 12 A 8 A 8 A

Table 16 3Level SVM same VDC_Bus.




Table 17 3Level SVM percent THD.

4.1 2Level SVM algorithm modification

67

FURTHER MODULATION

TECHINIQUES

This chapter introduces two different modulation, one for 2Level and the other for 3Level

inverter, as to obtain results similar to previous cases, not acting on the triangular carrier

signal.

2Level SVM algorithm modification

In previous chapters, changes to 2Level inverter modulation were investigated; they dealt

with a modification of the carrier signal keeping the algorithm, that creates the modulating

signals, unaltered. Now, the algorithm itself is analysed.

In [19] and [20], the theory is well introduced: it states that it is possible to modify the elapsing

time of the zero-vectors through a recombination of them. This would redistribute the

reference time signals going to the IGBTs. Starting from Appendix B, the modification is

actuated when the triangular carrier signal is related to the states of each sector; as said, the

aim is to variate the state in which zero-vector stays.

Figure 4.1 Zero-vector time modification in Sector1.

4 Further modulation techiniques

68

In Figure 4.1 a new variable is introduced that is k. It is a signal containing the 0-axis error

coming from the current PI controller as it happened in previous cases. This parameter has

the dimension of time and proper 𝑘𝑝 and 𝑘𝑖 values should be found to make it fit with the

modulation.

Since 𝑇𝑠 can be expressed just as a gain, and it results the sum of the actuation times of each

vector, the correction on zero-vector, through k, should be limited to a small value with respect

to 𝑇𝑠. In our case 𝑘𝑝 = 1𝑒−3 and 𝑘𝑖 = 100 have been chosen.

The modification in Simulink happens as follow.

Figure 4.2 2Level SVM with k.

Simulink model presents a modification only on Inverter 1 modulation so the presence of k1

in Figure 4.2 is explained. The choice was done since the modulation on both the inverters led

to almost the same results.

An extract of the S-function C-code is reported: it is built on the base of the theory presented

in Figure 4.1, changing variables according to each sector.

// Sector, intervals and reference times calculation // if (H2 > 0) { if (H1 > H2) {// Sector 1 // Tt4 = H1 - H2; Tt6 = 2*H2; Tt0 = Tc - Tt4 - Tt6; Tta = k1[0]; Ttb = Tt4 + k1[0]; Ttc = Tt4 + Tt6 + k1[0]; } Out [0] = Tta; Out [1] = Ttb; Out [2] = Ttc;

4.1 2Level SVM algorithm modification

69

Results

In this paragraph, same cases of 3.2.1 are analysed. Anyway, only the results when the

modification is applied are reported, since, when it is not, waveforms are the same.

The first case presents inverters with same frequency and correction with k is applied; when

the correction doesn’t act, the result is equal to Figure 3.33.

Figure 4.3 2Level SVM ZSCC modified with k; same frequency.

As expected, the modification allows the ZSCC to stay inside a low band without reaching too

much high amplitudes. Moreover, it is possible to see that different frequencies are present in

the signal, darker is the blue higher is the frequency, as for previous results.

Then, Inverter 2 frequency is changed, and the obtained waveform follows; without

modification, ZSCC results as Figure 3.38.

Figure 4.4 2Level SVM ZSCC modified with k; different frequencies.


70

ZSCC is still quite distorted and presents relative high amplitude; anyway, its peaks are almost

half of those when no correction is applied.

In addition, a study with different DC buses is done: results are quite similar and can be

resumed as follow.

Quantity

Same frequency Different frequencies

No modification Modification No modification Modification

ZSCC 25 A 8 A 30 A 15 A

Table 18 2Level SVM with k; different VDC_Bus.

As a further proof that the modulation works quite good, grid currents are shown. In all the

cases they follow almost perfectly the references.

Figure 4.5 2Level SVM with k grid currents; difference frequency.

Even if waveforms seem to be very smooth, it is to underline that this modified modulation

introduces a small increase in THD.

Quantity

Same frequency Different frequencies

No modification Modification No modification Modification

THD % 1.04 % 1.97 % 0.85 % 2.41 %

Table 19 2Level SVM with k percent THD.

4.2 3Level Zero Common Mode SVM

71

3Level Zero Common Mode SVM

Unlike 2Level inverter SVM, this configuration doesn’t allow the same modification. In

fact, how Appendix C explains, 3Level inverter has a different representation of the voltage

vectors since more combinations exist due to the increased number of the switches. 27

combinations and 24 sectors describe the new hexagon. So, it would be not so efficient to

modify only the inner hexagon, as it was a 2Level inverter, because when the reference voltage

vector goes beyond, the modification is no longer available. Thus, a new solution is

investigated: it focuses on modifying the external hexagon, acting on those states that generate

or contribute to the circulation of the zero-sequence circulating current.

ZCM theory

The modulation deviates a bit from the main goal of this work. In fact, it modifies the

Common Mode Voltage (CMV), that consequentially should mitigate the ZSCC. CMV is

obtained as the combination of the phase voltages referred to the middle point of the DC bus,

called pole voltages; Figure 2.4 shows how these voltages can be measured and the equation

follows.

𝑉𝐶𝑀 =1

3∙ (𝑉𝐴0 + 𝑉𝐵0 + 𝑉𝐶0) Eq. (4.1)

Since pole voltages depend on the switches condition, if open or not, even 𝑉𝐶𝑀 depends on

them. Among 27 states of the 3Level inverter, only 7 present 𝑉𝐶𝑀 = 0 and they can be resumed

in Table 20.

States VA0 VB0 VC0 VCM

000 0 0 0 0

10-1 𝑉𝐷𝐶/2 0 −𝑉𝐷𝐶/2 0

01-1 0 𝑉𝐷𝐶/2 −𝑉𝐷𝐶/2 0

-110 −𝑉𝐷𝐶/2 𝑉𝐷𝐶/2 0 0

-101 −𝑉𝐷𝐶/2 0 𝑉𝐷𝐶/2 0

0-11 0 −𝑉𝐷𝐶/2 𝑉𝐷𝐶/2 0

1-10 𝑉𝐷𝐶/2 −𝑉𝐷𝐶/2 0 0

Table 20 Pole Voltage and Common Mode Voltage.


72

All the other states generate a 𝑉𝐶𝑀. This result suggests that acting only on the mentioned states

may bring to a reduction of CMV. Thus, a modulation is carried out considering a new hexagon

whose vertices are the 6 states of Table 20 and has state 000 as the centre.

Figure 4.6 3Level ZCM SVM inverter hexagon.

Calculations are carried out as Appendix B does for 2Level inverter; in fact, the new hexagon

results as that of 2Level just rotated of 30° and with an amplitude of the vectors of 𝑉𝐷𝐶/𝑠𝑞𝑟𝑡(2)

instead of 𝑉𝐷𝐶 ∙ 𝑠𝑞𝑟𝑡(2/3).

This new configuration reduces the DC bus utilization since the hexagon is smaller ad its

inscribed circumference amplitude is lower.

𝐵𝑢𝑠 𝑢𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛 𝑟𝑒𝑑𝑢𝑐𝑡𝑖𝑜𝑛 𝑓𝑎𝑐𝑡𝑜𝑟 =

𝑉𝐷𝐶

√2

√23

∙ 𝑉𝐷𝐶

=√3

2= 0.866 Eq. (4.2)

It is worth to examine how this condition influences the system under analysis. Since grid-

connection implies that a given AC voltage is required at the inverter output, DC bus voltage

has to change according to the previous factor: this means that, in our case, DC bus voltage

should assume the following value.

𝑉𝐷𝐶_𝐵𝑢𝑠′ = 0.866 ∙ 𝑉𝐷𝐶_𝐵𝑢𝑠 = 0.866 ∙ 700 𝑉 = 606.2 𝑉 Eq. (4.3)


73

Back to the modulation, a table is built up containing the application times calculated

according to the position of the reference voltage vector.

Sector Active

states Conditions

Application

times Reference times

1 0-11 – 1-10 h1>0

-h2>h1

t0-11=h1-h2=t1 t1-10=2h1=t2

t000=Ts-t0-11-t1-10

ta1=Ts-t2 tb1=Ts tc1=t1

ta2=Ts-Ts tb2=Ts-t0

tc2=Ts

2 1-10 – 10-1 h1>0 else

t1-10=-h1-h2=t1 t10-1=h1+h2=t2

t000=Ts-t2-t6

ta1=t0 tb1=0 tc1=0

ta2=Ts-Ts tb2=Ts-t1 tc2=t1+t0

3 10-1 – 01-1 h1>0 h2>h1

t10-1=2h1=t1 t01-1=-h2-h1=t2

t000=Ts-t10-1-t01-1

ta1=Ts-t1 tb1=Ts-t2

tc1=0

ta2=Ts-Ts tb2= Ts-Ts

tc2=t0

4 01-1 – -110 h10

h2>-h1

t01-1=-h1+h2=t1 t-110=-2h1=t2

t000=Ts-t01-1-t-110

ta1=Ts-0 tb1=t1+t2

tc1=0

ta2=t2 tb2=Ts

tc2=t2+t0

5 -110 - -101 h10 else

t-110=h1+h2=t1 t-101=-h1-h2=t2

t000=Ts-t-110-t-101

ta1=Ts-0 tb1=Ts-t1

tc1=t2

ta2=Ts-t0 tb2=Ts-Ts

tc2=Ts

6 -101 – 0-11 h10

-h2>-h1

t-101=-2h1=t1 t0-11=h1-h2=t2

t000=Ts-t-101-t0-11

ta1=Ts-0 tb1=0

tc1=t1+t2

ta2=t1 tb2=t1+t0

tc2=Ts

Table 21 ZCM SVM time intervals.

To determine the reference times that regulate the switches, a comparison to a carrier signal

is introduced. In this case, a sawtooth is considered instead of a triangular signal with both

period and amplitude of 𝑇𝑠.


74

In the following only Sector 1 and 4 will be analysed.

Since ZCM SVM implies a choice of non-consecutive states, between one state and another 2

IGBTs switch; the sequence can be reported accordingly. Unlike 2Level SVM, this case

introduces changes such as discontinuity, as said, and the necessity to modify even the

comparison with the carrier signal. In fact, the first leg presents negated signals, the second

leg has the sawtooth signal shifted of t1 for Sector 1 and 2, t2 for Sector 3 and 4 and of t0 for

Sector 5 and 6; in addition, odd sectors have negated signals while even ones don’t. The third

leg, instead, doesn’t present any variation.

Table 22 Switches conditions in Sector 1.

t1 t1 t0 t0 t2 t2

0 0 0 0 1 1

-1 -1 0 0 -1 -1

1 1 0 0 0 0

a1 0 0 0 0 1 1

a2 1 1 1 1 1 1

b1 0 0 0 0 0 0

b2 0 0 1 1 0 0

c1 1 1 0 0 0 0

c2 1 1 1 1 1 1

Table 23 Switches conditions in Sector 4.

t2 t2 t0 t0 t1 t1

-1 -1 0 0 0 0

1 1 0 0 1 1

0 0 0 0 -1 -1

a1 0 0 0 0 0 0

a2 0 0 1 1 1 1

b1 1 1 0 0 1 1

b2 1 1 1 1 1 1

c1 0 0 0 0 0 0

c2 1 1 1 1 0 0

Figure 4.7 Reference times for Sector 1.

Figure 4.8 Reference times for Sector 4.


75

Simulink model

Once the theoretical part has been explained, a Simulink model is implemented. The

strategy is the same as for 2Level or 3Level SVM.

Figure 4.9 3Level inverter ZCM SVM.

In Figure 4.9, leg a presents inverse logic according to what previously said. Then, the

modification for leg b is carried out through 2 additional blocks. Unlike other modulations,

now S-function gives out 8 signals: 6 are those for the switches and 2 are necessary to modify

signals of leg b. An extract of the S-function code is reported below.

// Sector, intervals and reference times calculation // if (H1 > 0) { if (-H2 > H1) {// Sector 1 // Tt1 = -H1 - H2; Tt2 = 2 * H1; Tt0 = Tc - Tt1 - Tt2; T_a1 = Tc-Tt2; T_a2 = Tc-Tc; T_b1 = Tc; T_b2 = Tc-Tt0; T_shift2=Tt2; T_pol2=0; T_c1 = Tt1; T_c2 = Tc;


76

} else if (H2 > H1) {// Sector 3 // } else {// Sector 2 // } } else if (H2 > (-H1)) {// Sector 4 // } else if ((-H2) > (-H1)) {// Sector 6 // } else {// Sector 5 // } Out [0] = T_a1; Out [1] = T_a2; Out [2] = T_b1; Out [3] = T_b2; Out [4] = T_shift2; Out [5] = T_pol2; Out [6] = T_c1; Out [7] = T_c2;

It has already been mentioned that the carrier signal is different: it is an ideal sawtooth signal

only for leg a and c.

Figure 4.10 Sawtooth carrier signal generation.

The first block from the left represents the default sawtooth bounded between ±1, with a

period equal to 𝑇𝑠, thus an addition of 1 and then a division by 1/2 is done to obtain a sawtooth

between 0 and 1; finally, the signal is multiplied by 𝑇𝑠, so to have a sawtooth with amplitude

and period of 𝑇𝑠.


77

Regarding leg b, instead, the ideal signal has to be modified since it is shifted by a certain

quantity according to selected sector. This quantity is the fifth output of the S-function and

takes into account the shifting time for each sector.

Figure 4.11 Modified sawtooth carrier signal generation.

Considering PHASEx, previous scheme generates a modified carrier signal; in fact, the block

rem gives out the reminder of the division between the ideal sawtooth, plus the shifting signal,

and a constant 𝑇𝑠: this allow to obtain a waveform between 0 and 𝑇𝑠 that considers the phase

shift.

A last block is then described: it contains the logic to generate leg b signals. In fact, they have

to be negated or not according to the chosen polarity coming from the modulation.

Figure 4.12 ZCM leg b signals.

The two switches let the above signal pass if pol is greater than the threshold, set to 0, otherwise

the lower signal passes. Odd sectors have 𝑝𝑜𝑙 = 0 thus they are negated and it is coherent to

Table 22; on the contrary, even sectors have 𝑝𝑜𝑙 = 1 thus they pass unaltered as Table 23

shows.


78

Results

Following results are based on the same cases of previous modulations. In addition, the

analysis deals also with load-connected inverters.

It is considered a resistive load as the equivalent resistance of the grid.

𝑅𝑔𝑟𝑖𝑑 =

𝑉𝑔𝑟𝑖𝑑,𝑅𝑀𝑆,𝑝ℎ−𝑝ℎ

√3𝐼𝑔𝑟𝑖𝑑,𝑅𝑀𝑆

=

380 𝑉

√3100 𝐴

= 2.19 𝛺 Eq. (4.4)

Regarding the grid-connected case, the configuration remains the same as the modulations in

Chapter 2.

The quantities under analysis are the CMV, the ZSCC and inverter output currents.

As mentioned, the CMV is related to the pole voltages; since they vary between ±350 V, half of

𝑉𝐷𝐶_𝐵𝑢𝑠, CMV for classical SVM assume 0 V, ±116.67 V and ±233.3 V, according to Eq. (4.1).

This demonstrates the inability of simple SVM to produce a low common mode voltage and

thus a reason to investigate on a new modulation. The following waveform represents the CMV

both in case of load- and grid-connected inverters, resulting the same from the simulations.

Figure 4.13 Classical SVM CMV.


79

Unlike previous case, for ZCM SVM, two different results appear. In principle, they manifest a

notable reduction in the CMV as Figure 4.15 shows, reaching values between ±0.25 V.

Figure 4.14 ZCM SVM CMV.

Figure 4.15 ZCM SVM CMV zoom.

The only evident difference is the absence of peaks when the inverters are connected to grid;

this is probably because grid imposes the voltage to the AC side of the inverter producing more

balanced waveforms, balance that can be found then in the common mode voltage, as a result

of a combination of them.

Therefore, also an improvement of ZSCC is obtained. Zero CMV reduces current flowing in the

paths created by the ZCM switches topologies in the inverter; lower currents mean lower

leakage current. Figure 4.16 and Figure 4.17 demonstrate that, in both cases of load- or grid-

connection, the modulation behaves efficiently.

Figure 4.16 ZSCC for classical SVM.

Figure 4.17 ZSCC for ZCM SVM.


80

The case with a variation of frequency between the two inverters is investigated, and an

improvement with respect to Figure 3.44 is obtained. The study is only for grid-connected

inverters since for load-connected ones it resulted in an unbalance in phase currents due to

the absence of a regulation action.

Figure 4.18 ZCM SVM ZSCC; grid-connected with different inverter frequencies.

At last, AC currents are investigated.

Figure 4.19 ZCM SVM load and grid currents.

As clear from Figure 4.19, the modulation allows a good result in terms of current waveforms.

The first think to notice is that phase B, in red, in the case of grid-connection, presents some

distortion both on positive and negative peaks: this is due to the particular modulation done

for leg b and for sure due to the input signals of the S-function. In fact, while, for load-

connected case, those signals are ideal dq voltages, in the other case, they come from the PI

controllers and contain ripples.


81

In addition, this modulation introduces a DC component in the currents.

Figure 4.20 Currents with DC component.

Figure 4.21 Currents without DC component.

Figure 4.20 shows peaks of each phase, with a more relevant unbalance in the grid-connection

case; Figure 4.21 represents the same quantities after their own mean values have been

subtracted thus to give out waveforms without the DC component; phase B, in red, still

presents a higher peak due to modulation, as previously said, and not to DC component.

Anyway, even if this modulation presented a higher DC component in the phase currents, the

sum of the three DC signals is identically 0.

Another drawback of this modulation is the increased value of THD content of grid-injected

currents. It results much higher respect to previous modulations, especially on phase B.

Grid

Phase a b c

THD % 3.17 % 5 % 3.03 %

Table 24 ZCM SVM grid currents THD.

5.1 Test bench

83

LABORATORY TESTS

Test bench

Two inverters are parallelized with AC common point and a three-winding transformer

to decouple the system from the grid. As DC buses, instead of PV panels, two isolated sources

are used. The parasitic capacitance, obtained as the sum of the two capacitances of each

inverter, is 5 μF. The connection to the ground is realized on the DC bus and not on the input

of the DC/AC converter, thus to bypass the DC/DC boost at inverter input terminals. Inverter

parameters considered are the same as for the simulations. The only difference is the switching

frequency equivalent to 8 kHz.

Figure 5.1 Scheme for laboratory tests.

5 Laboratory tests

84

LCL filter

Filter parameters are the same of Table 2. In addition, common mode chokes, 8 kHz filter,

Cx and Cy AC capacitors for EMI filtering are removed. This allows to focus only on the

parasitic capacitance action.

Measurements

Following figures show inverter output phase current, (yellow) and current flowing in the

parasitic capacitances (green), also known as ZSCC. Parallel configuration produces

significant high peak-to-peak value of 20 A. In this case, current slowly oscillates according to

the shift between the two switching frequencies, with a period of almost 10 s.

Figure 5.2 ZSCC and inverter current.

In the following a zoom is shown; ZSCC has the same frequency of the inverters, 8 kHz.

Figure 5.3 ZSCC and inverter current zoom.

5.4 PWM synchronization

85

PWM synchronization

To evaluate if the technique is efficient, a semi-automatic synchronization procedure has

been implemented. On one of the inverters, it is possible to slow down the switching frequency

arbitrarily, shifting the triangular carrier signal that generates the PWM. In this way, one, with

the help of the oscilloscope, is able to synchronize the switching frequencies accordingly.

Figure 5.4 ZSCC and inverter current with modification.

Zooming Figure 5.4, it can be noticed that the 8 kHz oscillation is still present, but it is

considerably reduced to a peak-to-peak value of 2 A (note that the scale, for the green signal,

has been reduced to 2 A/division).

Figure 5.5 ZSCC and inverter current with modification zoom.

6.1 Conclusions

87

CONCLUSIONS

Conclusions

In this chapter, a summing-up of the overall work is drawn. Its aim is to present all the

used techniques in order to make a comparison between advantages and disadvantages of each

one and, if necessary, make a trade-off among the results of the adopted methods. As first, the

thesis aimed to leave out the already presented solutions brought by literature, trying to act on

the inverter modulation itself. This would make the whole system more reliable and efficient,

keeping out those elements that introduce losses, problems of maintenance and similar

obstacles.

The adopted techniques are:

• Sinusoidal PWM. This modulation is referred as the simplest one: it compares a three-

phase modulating signal and a triangular carrier one. Since the modulating signal is

kept unvaried, due to how it is generated, the choice was to modify the carrier one.

It is done making its period varying according to the homopolar-axis current error, to

which the ZSCC, to mitigate, is proportional.

• Space Vector Modulation. This type of modulation gets more complicated from a

computational point of view; the modulating signals are now times, generated from a

C-code based on many calculations. Again, the first choice was to keep unaltered these

signals and to vary the carrier signal in the same way SPWM did.

Previous modifications, even if they reach the objective of the work, present a drawback. The

modification of the switching period doesn’t result easy to realize and attention must be paid

to the error that modifies it since it could compromise the modulation at all.

From this reason, new modulations regarding SVM are introduced. They act on the generation

of the modulating signal without altering the carrier one. This ensures reasonable results of

ZSCC but introduces other problems.

6 Conclusions

88

First modulation is still related to precedent studies since the homopolar-axis error is the

quantity under investigation; in this case, for 2Level inverter, it is used to change the reference

times of each phase before the comparison with the triangular carrier signal happens. This

produces a reduction in the ZSCC since the zero-vector time is controlled accordingly; anyway,

the modulation introduces an increase of inverter output currents THD and consequentially

of grid currents one.

The second technique, ZCM SVM, related to 3Level inverter, has been implemented with a

different goal: generation of zero common mode voltage. Additionally, results demonstrate

that this contributes to a reduction of the ZSCC. However, it is to recall that this modulation

reduces the bus voltage utilization forcing to pay attention when the system is built up.

A comparison among all the results comes to be useful to have an overview on the adopted

modulations and choose which responds better to the initial request. In the following, peak

values are considered. SPWM presents a ZSCC lower than 1 A when inverters have the same

frequency unlike SVM, whose ZSCC is equal to few tens of Ampere; changing the switching

frequency of one of the inverters makes ZSCC increase to more or less 10 A for SPWM and

30÷40 A for SVM. So, modifications are applied and 2Level inverter SPWM ZSCC stays around

3 A while 3Level one goes below 1 A; the same improvement happens for SVM, even if its ZSCC

are around 5÷8 A. A study with different 𝑉𝐷𝐶_𝐵𝑢𝑠 was done and it demonstrated that the

techniques are still valid despite ZSCC, even if lowered, assumes higher values with respect to

case with same 𝑉𝐷𝐶_𝐵𝑢𝑠. About the two other modulations, the one for 2Level case presents

values of ZSCC around 8 A and 5 A for same and different frequencies respectively; the last one

presented very notable result in case of same frequency: ZSCC reaches peaks around 20 mA

while even 10 A are reached when frequencies differ. Anyway, this represents an improvement

with respect to classical 3Level SVM with different inverters frequencies.

Thus, to conclude, SPWM seems the modulation to be modified since its values of ZSCC are

considerably lower respect those of SVM; anyway, the latter modulation is much more spread

in modern technologies. The modified algorithm for 2Level SVM doesn’t bring to an efficient

solution and in addition grid currents THD content is quite high. ZCM, on the contrary, gives

a relative low ZSCC even if its grid currents THD is the highest among all the presented

modulations.

6.2 Future work

89

Future work

In the work, many models have been presented as based on ideal situations, as sampling

frequency, default Simulink blocks, ideal quantities. In practice it is surely different, thus, in

the future, it would be useful to implement the same model in a laboratory to see if

experimental results match the simulations. First it is to consider that sampling frequency,

limited to tens of kHz in nowadays technology, will modify all the measurements and a

reorganization of current controllers, LCL filters and probably other schemes should be

considered. In addition, the case of different dc buses can be of interest and should be

investigated deeply.

90

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i

APPENDIX A

Clarke and Park transformations

Used in three-phase systems, they result particularly convenient whenever current and voltage

transients have to be analysed.

Clarke transformation is a linear “fixed-axis” transformation at constant coefficients. The

transformation matrix results:

�̿�𝑜 = √2

3

[ 1 −

1

2−

1

2

0√3

2−

√3

21

√2

1

√2

1

√2 ]

This matrix, applied to three-phase instantaneous quantities 𝑣𝑎(𝑡), 𝑣𝑏(𝑡), 𝑣𝑐(𝑡), gives origin to

three Clarke components: α, β and 0, or homopolar.

[

𝑣𝛼(𝑡)𝑣𝛽(𝑡)

𝑣0(𝑡)

] = �̿�𝑜 [

𝑣𝑎(𝑡)𝑣𝑏(𝑡)𝑣𝑐(𝑡)

]

�̿�𝑜 is an orthogonal matrix, ensuring that the inverse matrix is equal to the transposed one.

Clarke vector, composed by 𝑣𝛼(𝑡) and 𝑣𝛽(𝑡), can be defined; it is also known as spatial vector:

�̅�(𝑡) = 𝑣𝛼(𝑡) + 𝑗𝑣𝛽(𝑡)

ii

Anyway, Clarke transformation is a particular case of Park one, obtained on rotating axis.

Park transformation matrix, always orthogonal, is as follow.

�̿�(𝜃) = √2

3

[ cos(𝜃) cos(𝜃 −

2𝜋

3) cos (𝜃 +

2𝜋

3)

−sen(𝜃) −sen(𝜃 −2𝜋

3) − sen(𝜃 +

2𝜋

3)

1

√2

1

√2

1

√2 ]

As Clarke transformation, this matrix, applied to three-phase instantaneous quantities, gives

origin to three elements: d, q and 0, or homopolar.

[

𝑣𝑑(𝑡)𝑣𝑞(𝑡)

𝑣0(𝑡)

] = �̿�(𝜃) [


]

The angular parameter 𝜃 is a time function. This element, along with its time derivative, can

be intended respectively as the position and the angular speed of Park axes (dq) with respect

to a fixed reference defined by the position 𝜃 = 0. Even in this case, Park complex vector is

defined:

�̅�(𝑡) = 𝑣𝑑(𝑡) + 𝑗𝑣𝑑(𝑡)

Figure A-1 �̅�(𝑡) either on Clarke and Park axes.

Hence, this second transformation rotates the dq components by the angle 𝜃, while the

homopolar component remains unchanged.

iii

Considering a Park vector referred to fixed-axis (𝜃 = 0), the same vector referred to rotating

axis results to be:

�̅�(𝑡) = �̅�𝑜(𝑡)𝑒−𝑗𝜃(𝑡)

Moreover, considering a generic three-phase sinusoidal voltage waveform �̅�𝑜(𝑡) = �̅�𝑒𝑗𝜔𝑡, its

Park vector results:

�̅�(𝑡) = �̅�𝑒𝑗(𝜔𝑡−𝜃)

Assuming that 𝜃 = 𝜔𝑡 (axis rotating at the grid frequency):

�̅�(𝑡) = �̅�

�̿�(𝜃(𝑡)) is not indifferent from the derivative operation. Making the time derivative of tree-

phase quantities, the results are:

𝑑

𝑑𝑡[


] = �̿�(𝜃) 𝑡 [


𝑣0(𝑡)

] +𝑑�̿�(𝜃) 𝑡

𝑑𝑡(

𝑑

𝑑𝑡[


𝑣0(𝑡)

] + �̿�(𝜃)𝑑�̿�(𝜃) 𝑡

𝑑𝑡[


𝑣0(𝑡)

])

�̿�(𝜃)𝑑

𝑑𝑡[

𝑣𝑎(𝑡)

𝑣𝑏(𝑡)

𝑣𝑐(𝑡)] =

𝑑

𝑑𝑡[


𝑣0(𝑡)

] + 𝐽�̿�𝑃 [


𝑣0(𝑡)

]

𝑤ℎ𝑒𝑟𝑒 𝐽 ̿ = �̿�(𝜃)𝑑�̿�(𝜃)𝑡

𝑑𝑡= [

0 −1 01 0 00 0 0

] 𝑎𝑛𝑑 𝜔𝑃 =𝑑𝜃

𝑑𝑡

These equations give birth to additional terms proportional to 𝜔𝑃 , called motional terms.

v

APPENDIX B

2Level Space Vector Modulation

This section explains, as detailed as possible, how SVM is implemented for a 2Level

three-phase inverter.

Figure B-1 2Level three-phase inverter.

A three-phase inverter can assume only 8 states, as a combination of its switches: these are

characterized by 3 bits, one per leg, that report how the IGBTs are connected. State “1” of a bit

means that the IGBT, connected to the positive pole of the DC bus, is closed (conducting) while

the lower IGBT connected to the negative pole is opened; “0” means the upper one is opened

and the lower is closed.

vi

Thus, a representation of the 8 states can be realized:

Figure B-2 2Level SVM hexagon.

It is a hexagon, of 6 sectors, containing 6 active states on the vertices and 2 0-states in the

centre. (000) and (111) represent the case in which all lower or all upper switches are on: this

implies 0-phase and 0-Park voltage. To recall, Park voltages (Space Vector) can be expressed

as follow:

�̅� = 𝑣𝛼 + 𝑗𝑣𝛽 =√2

√3∙ (𝑣𝐴𝑂 + �̅�𝑣𝐵𝑂 + �̅�2𝑣𝐶𝑂)

with:

• �̅� = 𝑒𝑗2

3𝜋

• 𝑣𝐴𝑂 + 𝑣𝐵𝑂 + 𝑣𝐶𝑂 = 0

And from the equation it results:

𝑣𝛼 =√3

√2𝑣𝐴𝑂

𝑣𝛽 =1

√2∙ (𝑣𝐵𝑂 − 𝑣𝐶𝑂) =

1

√2∙ (2𝑣𝐵𝑂 + 𝑣𝐴𝑂)

In addition, the pole voltage is considered: it is the voltage from the middle point of each leg

referred to the negative pole of the DC bus. It equals 𝑉𝐷𝐶 when upper switch in on and 0 when

the lower switch is on.

vii

Finally, the phase voltages can be derived from the following equations:

𝑣𝐴𝑂 =2 ∙ 𝑣𝐴𝑁 − 𝑣𝐵𝑁 − 𝑣𝐶𝑁

3

𝑣𝐵𝑂 =2 ∙ 𝑣𝐵𝑁 − 𝑣𝐴𝑁 − 𝑣𝐶𝑁

3

𝑣𝐶𝑂 =2 ∙ 𝑣𝐶𝑁 − 𝑣𝐴𝑁 − 𝑣𝐵𝑁

3

The following table resumes the states and which voltages they produce.

State Pole Voltage Phase Voltage Park Voltage

ABC vAN vBN vCN vAO vBO vCO vα vβ

(000) 0 0 0 0 0 0 0 0

(100) 𝑉𝐷𝐶 0 0 2𝑉𝐷𝐶/3 −𝑉𝐷𝐶/3 −𝑉𝐷𝐶/3 𝑉𝐷𝐶√2/√3 0

(110) 𝑉𝐷𝐶 𝑉𝐷𝐶 0 𝑉𝐷𝐶/3 𝑉𝐷𝐶/3 −2𝑉𝐷𝐶/3 𝑉𝐷𝐶/√6 𝑉𝐷𝐶/√2

(010) 0 𝑉𝐷𝐶 0 −𝑉𝐷𝐶/3 2𝑉𝐷𝐶/3 −𝑉𝐷𝐶/3 −𝑉𝐷𝐶/√6 𝑉𝐷𝐶/√2

(011) 0 𝑉𝐷𝐶 𝑉𝐷𝐶 −2𝑉𝐷𝐶/3 𝑉𝐷𝐶/3 𝑉𝐷𝐶/3 −𝑉𝐷𝐶√2/√3 0

(001) 0 0 𝑉𝐷𝐶 −𝑉𝐷𝐶/3 −𝑉𝐷𝐶/3 2𝑉𝐷𝐶/3 −𝑉𝐷𝐶/√6 −𝑉𝐷𝐶/√2

(101) 𝑉𝐷𝐶 0 𝑉𝐷𝐶 𝑉𝐷𝐶/3 −2𝑉𝐷𝐶/3 𝑉𝐷𝐶/3 𝑉𝐷𝐶/√6 −𝑉𝐷𝐶/√2

(111) 𝑉𝐷𝐶 𝑉𝐷𝐶 𝑉𝐷𝐶 0 0 0 0 0

In order to minimize the commutation of the switches, it is convenient to have a sequence so

that the transition from a state to another happens with a commutation of only one phase of

the inverter.

It can now proceed in the technique explanation. Focusing on Sector 1, the reference voltage

is constant in a switching period and it is represented by a constant space vector. Anyway, it is

possible to calculate the average value over a switching period. It is enough to apply the two

vectors for a time proportional to their projections and to apply the 0-vector for the remaining

time.

viii

Figure B-3 Sector 1 of 2Level inverter SVM.

Let’s call state (100) as 1 and (110) as 2. The projections of 𝑉𝑟𝑒𝑓 are:

𝑣𝛼1 =√2

√3𝑉𝑑𝑐 ; 𝑣𝛽1 = 0 ; 𝑣𝛼2 =

1

√6𝑉𝑑𝑐 ; 𝑣𝛽2 =

1

√2𝑉𝑑𝑐

Now, in the switching period 𝑇𝑠, it is possible to calculate also the average value:

𝑉𝛼 =1

𝑇𝑠∙ (√

2

3𝑡1 +

1

√6𝑡2) ∙ 𝑉𝑑𝑐

𝑉𝛽 =1

𝑇𝑠∙

1

√2𝑡2 ∙ 𝑉𝑑𝑐

From previous equations it is possible to obtain the application times 𝑡1 and 𝑡2:

𝑡1 =1

√2∙ (√3𝑉𝛼 − 𝑉𝛽) ∙

𝑇𝑠

𝑉𝑑𝑐

𝑡2 = √2 ∙ 𝑉𝛽 ∙𝑇𝑠

𝑉𝑑𝑐

and substituting:

𝐻1 = √3

2∙𝑉𝛼

𝑉𝑑𝑐∙ 𝑇𝑠

𝐻2 =1

√2∙𝑉𝛽

𝑉𝑑𝑐∙ 𝑇𝑠

ix

it results:

𝑡1 = 𝐻1 − 𝐻2

𝑡2 = 2 ∙ 𝐻2

𝑡0 = 𝑇𝑠 − 𝑡1 − 𝑡2

Since 0-vector can be obtained both with state (000) and (111), called also 0 and 7, usually it

is used to make them have the same duration.

Since it could not be obvious which 0-state must be applied first, it is used to repeat the

sequence of the states mirrored, in the total switching period. Then, it is easy to obtain the

output signals going to the switches, just comparing the three signals obtained by the SVM

with a triangular waveform of frequency 𝑓𝑠.

Figure B-4 Centred 2Level inverter SVM.

x

Figure B-5 Signal comparison for switching signals generation.

Known each sector applied vectors and the duration time of the states, it is possible to derive

𝑡𝑎, 𝑡𝑏 and 𝑡𝑐 that are the reference times compared with the triangular carrier signal.

This procedure can be repeated for each sector in the same manner and the final results are

reported in the following table. Concerning parameters 𝐻1and 𝐻2, they allow a simple and

direct identification of the sector in which the reference vector is.

xi

Sector Active states Conditions Application

times

Reference

times

1 1-2 H2>0

H1>H2

t4=h1-h2 t6=2h2

t0=Ts-t4-t6

ta=t0/2 tb=t0/2+t4

tc=t0/2+t4+t6

2 2-3 H2H1

H2 -H1

t2=-h1+h2 t6=h1+h2 t0=Ts-t2-t6

ta=t0/2+t2 tb=t0/2

tc=t0/2+t2+t6

3 3-4 H2>0

H2<-H1

t2=2h2 t3=-h1-h2

t0=Ts-t2-t3

ta=t0/2+t2+t3 tb=t0/2

tc=t0/2+t2

4 4-5 H20

H2>H1

t3=-h1+h2 t1=-2h2

t0=Ts-t3-t1

ta=t0/2+t1+t3 tb=t0/2+t1

tc=t0/2

5 5-6 H2H1 H2-H1

t5=h1-h2 t1=-h1-h2

t0=Ts-t5-t1

ta=t0/2+t1 tb=t0/2+t1+t5

tc=t0/2

6 6-1 H20

H2>-H1

t5=-2h2 t4=h1+h2 t0=Ts-t5-t4

ta=t0/2 tb=t0/2+t4+t5

tc=t0/2+t4

Once conditions, application and reference times have been calculated, there is to find a way

to implement this modulation in a model. It results quite easy since MATLAB Simulink makes

available a block called S-function: it receives as input the variables of the space vector such as

𝑉𝛼, 𝑉𝛽, 𝑓𝑠 and 𝑉𝐷𝐶 and gives as output the signals that have to be compared with the triangular

carrier signal. S-function contains a C-code whose logic is exactly based on the previous table.

Here it is reported the C-code implemented for 2Level inverter SVM.

/*2Level SPACE VECTOR*/ // Variable definition // fs_ = fs [0]; // 10000 Hz Tc = (1/fs_)/2; // 50us c_H1= (sqrt(3)* Tc)/(sqrt(2)* VDC); c_H2= c_H1/sqrt(3); VDC = VDC_Bus [0]; // PWM inizialization // Vα= Vα [0]; Vβ= Vβ [0]; H1 = (Vα *c_H1); H2 = (Vβ *c_H2);

xii

// Sector, intervals and reference times calculation // if (H2 > 0) { if (H1 > H2) {// Sector 1 // Tt4 = H1 - H2; Tt6 = 2*H2; Tt0 = Tc - Tt4 - Tt6; Tta = Tt0/2; Ttb = Tt0/2 + Tt4; Ttc = Tt0/2 + Tt4 + Tt6; } else if (- H1 > H2) {// Sector 3 // } else {// Sector 2 // } } else { if (H2 > - H1) {// Sector 6 // } else if (H2 > H1) {// Sector 4 // } else {// Sector 5 // } } Out [0] = Tta; Out [1] = Ttb; Out [2] = Ttc;

Figure B-6 2Level inverter S-function.

xiii

APPENDIX C

3Level Space Vector Modulation

The following explains how SVM is obtained for a 3Level three-phase inverter.

Classical theory, from “High-Power Converters and AC Drives” by Bin Wu and [21], implies

many trigonometric calculations that can rise to computational problems when they are

implemented on a DSP. Thus, an alternative solution is found: it has been developed by MCM

Energy Lab in Politecnico di Milano and it considers only 𝑉𝛼 and 𝑉𝛽 to obtain sectors and

application times. A 3Level inverter presents 3 legs, one per phase, and 3 states per leg,

indicated with 1,0 and -1 that are S_1 and S_2 on, S_2 and S_3 on, S_3 and S_4 on

respectively.

Figure C-1 3Level inverter.

xiv

Therefore, 27 states exist, and they can be reported on a hexagon. For what concerns the

amplitude of the vectors on the hexagon, they are obtained by Park transformation; classical

theory adopts the one with a multiplication factor of 2

3 while Politecnico di Milano uses the one

with √2

3. Then, the vectors are derived as follow:

Vector Zero Small Medium Large

Magnitude 0 ∙ 𝑉𝑑𝑐 √1

6∙ 𝑉𝑑𝑐 √

1

2∙ 𝑉𝑑𝑐 √

2

3∙ 𝑉𝑑𝑐

Figure C-2 3Level inverter hexagon.

Figure C-2 shows how the hexagon is divided: the inner one is the equivalent of a 2Level

inverter, while the outer is proper of the 3Level one.

Moreover, Figure C-2 shows some straight lines obtained by simply comparing the αβ-

components through some coefficients, explained in the following.

xv

Figure C-3 3Level inverter Sector 1.

Above it is reported Sector 1 of the hexagon; it contains 4 smaller sectors defined by states. As

it is clear, vectors 0,1 and 2 can be identified by more states since more configurations of the

inverter can give those vectors.

It is now possible to calculate, analytically, the time for each state depending on where the

voltage reference vector is. Region 12, in Figure C-3, is analysed. Its voltage vectors are:

�̅�1 = 1

√6∙ 𝑉𝑑𝑐 ; �̅�2 =

1

√6∙ 𝑉𝑑𝑐 ∙ 𝑒

𝑗𝜋3 ; �̅�7 =

1

√2∙ 𝑉𝑑𝑐 ∙ 𝑒

𝑗𝜋6 ;

�̅�𝑟𝑒𝑓 = 𝑉𝑟𝑒𝑓 ∙ 𝑒𝑗𝜃

In addition, in each sector, the reference vector multiplied for the switching period equals the

sum of each vector multiplied by its application time:

�̅�𝑟𝑒𝑓 ∙ 𝑇𝑠 = �̅�1 ∙ 𝑇1 + �̅�2 ∙ 𝑇2 + �̅�7 ∙ 𝑇7

xvi

And substituting, it becomes:

𝑉𝑟𝑒𝑓 ∙ (cos 𝜃 + 𝑗 sin 𝜃) ∙ 𝑇𝑠 =

=1

√6∙ 𝑉𝑑𝑐 ∙ 𝑇1 +

1

√6∙ 𝑉𝑑𝑐 ∙ (cos

𝜋

3+ 𝑗 sin

𝜋

3) ∙ 𝑇2 +

1

√2∙ 𝑉𝑑𝑐 ∙ (cos

𝜋

6+ 𝑗 sin

𝜋

6) ∙ 𝑇7

It is now to split the reference voltage vector in real and imaginary part:

�̅�𝑟𝑒𝑓 = 𝑉𝛼𝑟𝑒𝑓+ 𝑗𝑉𝛽𝑟𝑒𝑓

𝑉𝛼𝑟𝑒𝑓∙ 𝑇𝑠=

1

√6∙ 𝑉𝑑𝑐 ∙ 𝑇1 +

1

2√6∙ 𝑉𝑑𝑐 ∙ 𝑇2 +

√3

2√2∙ 𝑉𝑑𝑐 ∙ 𝑇7

𝑉𝛽𝑟𝑒𝑓∙ 𝑇𝑠=

1

2√2∙ 𝑉𝑑𝑐 ∙ 𝑇2 +

1

2√2∙ 𝑉𝑑𝑐 ∙ 𝑇7

Remembering that 𝑇𝑠 = 𝑇1 + 𝑇2 + 𝑇7, it is:

𝑇1 = 𝑇𝑠 −2√2 ∙ 𝑇𝑠 ∙ 𝑉𝛼𝑟𝑒𝑓

𝑉𝑑𝑐

𝑇2 = 𝑇𝑠 −√6 ∙ 𝑇𝑠 ∙ 𝑉𝛼𝑟𝑒𝑓

𝑉𝑑𝑐 +

√2 ∙ 𝑇𝑠 ∙ 𝑉𝛽𝑟𝑒𝑓

𝑉𝑑𝑐

𝑇7 =√6 ∙ 𝑇𝑠 ∙ 𝑉𝛼𝑟𝑒𝑓

𝑉𝑑𝑐 +

√2 ∙ 𝑇𝑠 ∙ 𝑉𝛽𝑟𝑒𝑓

𝑉𝑑𝑐 − 𝑇𝑠

To simplify previous equations, since they present common terms, it is possible to introduce

2 coefficients:

𝐻1 = √3 ∙ 𝑇𝑠 ∙ 𝑉𝛼𝑟𝑒𝑓

√2 ∙ 𝑉𝑑𝑐

𝐻2 = 𝑇𝑠 ∙ 𝑉𝛽𝑟𝑒𝑓

√2 ∙ 𝑉𝑑𝑐

This allows to rewrite the application times as:

𝑇1 = 𝑇𝑠 − 4𝐻2

𝑇2 = −2𝐻1 + 2𝐻2 + 𝑇𝑠

𝑇7 = −𝑇𝑠 + 2𝐻1 + 2𝐻2

xvii

Once the application times are determined, known the states per each sector, it is possible to

calculate reference times obtained by the comparison whit a triangular carrier signal.

Anyway, two cases exist:

1. Regions 13 and 14

To maintain the modulation symmetric and do not cause voltage unbalances on the

DC bus, the voltage vectors with two states, �̅�1 or �̅�2, stay for half of their application

time in one state and for the rest in the other state. A commutation sequence that

allows this configuration is the one called 7 segments applied in Region 14, as

example:

Figure C-4 3Level inverter subsector 14 times.

In Figure C-4, below, are reported the states present in region 14 and, on the left, the

respective time signals that will intercept the triangular carrier signal.

2. Regions 11 and 12

In this case, a further division in necessary: it is because these regions present more

configurations, so, depending on to which state the reference voltage vector is closer,

the commutation sequence changes. When 𝑉𝑟𝑒𝑓 is in 11a and 12a, 𝑉1 is considered as

main voltage vector and it is divided according to 7 segments procedure, otherwise, if

𝑉𝑟𝑒𝑓 is in 11b or 12b, 𝑉2 is considered.

xviii

Figure C-5 Divisions of Regions 11 and 12, in Sector 1.

The solution allows a more balanced DC bus voltage, avoiding the middle point to change too

much, since the commutation results linear.

In the following, the calculation of the application times and reference ones is carried out.

As for Region 12, all the others are computed, and their application times are derived.

Sector Region Active

states Conditions Application times

1

11 0 1 2 H2 > 0

H2 < H1 H2 < - H1 + 1/2

T0 = - 2H1 - 2H2 + Ts T1 = 2H1 - 2H2 T2 = 4H2

12 1 2 7 H2 < 1/4

H2 > H1 - 1/2 H2 > - H1 + 1/2

T1 = - 4H2 + Ts T2 = - 2H1 + 2H2 + Ts

T7 = 2H1 + 2H2 - Ts

13 1 7 13 H2 >0 H2 < H1 - 1/2

T1 = - 2H1 - 2H2 + 2Ts T7 = 4H2

T13 = 2H1 - 2H2 - Ts

14 2 7 14 H2 < H1 H2 > 1/4

T2 = - 2H1 - 2H2 + 2Ts T7 = 2H1 - 2H2 T14 = 4H2 - Ts

2

21 0 2 3 H2 > H1

H2 > - H1 H2 < 1/4

T0 = - 4H2 - Ts T2 = 2H1 + 2H2 T3 = 2H1 - 2H2

22 2 3 8 H2 > ¼

H2 < H1 + 1/2 H2 < - H1 + 1/2

T2 = 2H1 - 2H2 + Ts T3 = - 2H1 - 2H2 + Ts

T8 = 4H2 - Ts

23 2 8 14 H2 > H1 H2 > - H1 + 1/2

T2 = - 4H2 + 2Ts T8 = - 2H1 + 2H2

T14 = 2H1 + 2H2 - Ts

24 3 8 15 H2 > - H1 H2 > H1 + 1/2

T3 = - 4H2 + 2Ts T8 = 2H1 + 2H2

T15 = - 2H1 + 2H2 - Ts

xix

3

31 0 3 4 H2 < - H1

H2 > 0 H2 < H1 + 1/2

T0 = 2H1 - 2H2 + Ts T3 = 4H2

T4 = - 2H1 - 2H2

32 3 4 9 H2 < 1/4

H2 > - H1 – 1/2 H2 > H1 + 1/2

T3 = 2H1 + 2H2 + Ts T4 = - 4H2 + Ts

T9 = - 2H1 + 2H2 - Ts

33 3 9 15 H2 < - H1 H2 > 1/4

T3 = + 2H1 - 2H2 + 2Ts T9 = - 2H1 - 2H2 T15 = 4H2 - Ts

34 4 9 16 H2 > 0 H2 < - H1 – 1/2

T4 = + 2H1 + 2H2 + 2Ts T9 = 4H2

T16 = -2H1 - 2H2 - Ts

4

41 0 4 5 H2 < 0

H2 > - H1 – 1/2 H2 > H1

T0 = 2H1 + 2H2 + Ts T4 = - 2H1 + 2H2

T5 = - 4H2

42 4 5 10 H2 > -1/4

H2 < - H1 – 1/2 H2 < H1 + 1/2

T4 = 4H2 + Ts T5 = 2H1 - 2H2 + Ts

T10 = - 2H1 - 2H2 - Ts

43 4 10 16 H2 < 0 H2 > H1 + 1/2

T4 = 2H1 + 2H2 + 2Ts T10 = - 4H2

T16 = - 2H1 + 2H2 - Ts

44 5 10 17 H2 > H1 H2 < - 1/4

T5 = 2H1 + 2H2 + 2Ts T10 = - 2H1 + 2H2

T17 = - 4H2 -Ts

5

51 0 5 6 H2 > -1/4 H2 < H1

H2 > - H1

T0 = 4H2 + Ts T5 = - 2H1 - 2H2 T6 = 2H1 - 2H2

52 5 6 11 H2 < -1/4

H2 > H1 – 1/2 H2 > - H1 – 1/2

T5 = - 2H1 + 2H2 + Ts T6 = + 2H1 + 2H2 + Ts

T11 = - 4H2 -Ts

53 5 11 17 H2 < h1 H2 < - H1 – 1/2

T5 = 4H2 + 2Ts T11 = + 2H1 - 2H2

T17 = - 2H1 - 2H2 -Ts

54 6 11 18 H2 < - H1 H2 < H1 – 1/2

T6 = 4H2 + 2Ts T11 = - 2H1 - 2H2

T18= + 2H1 - 2H2 -Ts

6

61 0 1 6 H2 < 0

H2 > - H1 H2 > H1 – 1/2

T0 = -2H1 + 2H2 + Ts T1 = + 2H1 + 2H2

T6 = - 4H2

62 1 6 12 H2 > -1/4

H2 < - H1 + 1/2 H2 < H1 – 1/2

T1 = 4H2 + Ts T6 = - 2H1 - 2H2 + Ts T12 = 2H1 - 2H2 - Ts

63 6 12 18 H2 > - H1 H2 < -1/4

T6 = - 2H1 + 2H2 + 2Ts T12 = + 2H1 + 2H2

T18 = - 4H2 - Ts

64 1 12 13 H2 < 0 H2 > - H1 + 1/2

T1 = - 2H1 + 2H2 + 2Ts T12 = - 4H2

T13 = + 2H1 + 2H2 - Ts

xx

Then, in order to define the reference times going to the comparator, the triangular carrier

signal is introduced. The procedure is illustrated once for Region 11, divided in 11a and 11b,

and Region 13. In the following, it is considered only the left slope of the triangular wave, thus

half of the switching period 𝑇𝑐 = 𝑇𝑠/2. Anyway, the other half is just the same sequence

mirrored.

Region 11a

Tb1 = Tc1 = Tc

Ta1 = T1/4 + T2/2 + T0/2

Tc2 = T1/4 + T2/2

Tb2 = T1/4

Ta2 = 0

0 0 0 1 1 0 0 0

-1 0 0 0 0 0 0 -1

-1 -1 0 0 0 0 -1 -1

Region 11b

Tc1 = Tc

Tb1 = T2/4 + T0/2 + T1/2

Ta1 = T2/4 + T0/2

Tc2 = T2/4

Ta2 = Tb2 = 0

0 0 1 1 1 1 0 0

0 0 0 1 1 0 0 0

-1 0 0 0 0 0 0 -1

xxi

Region 13

Tb1 = Tc1 = Tc

Tc2 = T1/4 + T13/2 + T7/2

Tb2 = T1/4 + T13/2

Ta1 = T1/4

Ta2 = 0

0 1 1 1 1 1 1 0

-1 -1 0 0 0 0 -1 -1

-1 -1 -1 0 0 -1 -1 -1

The logic beyond the previous time values derivation can be explained. Once the states, below

the figures, are given, it is possible to see that the sequence is increasing linearly since each

step implies the commutation of only one switch. So, it can be seen how switching

configurations evolve: in Region 13, the first state, starting from the left, means that leg a has

switches S_2 and S_3 on while leg b and leg c have both switches S_3 and S_4 on. Then, on

leg a, S_1 closes and Ss_3 opens; this implies that there is a change in the comparation

between the time signals and the triangular wave. In fact, considering leg a: a1 regulates

switches S_1 and S_3, so when Ta1 is greater than the triangular wave, S_3 results closed and,

vice versa, S_1. In addition, it results that b1 and c1 are always greater than the triangular

wave since Sb_3 and Sc_3 are always on because they take part to “0” or “-1” state.

xxii

It follows a table containing the reference times for each sector.

Region States Reference times

11a

0 -1 -1 0 0 -1 0 0 0 1 0 0

Ta1 = T1/4 + T2/2 + T0/2 Ta2 = 0

Tb1 = Tc Tb2 = T1/4

Tc1 = Tc Tc2 = T1/4 + T2/2

11b

0 0 -1 0 0 0 1 0 0 1 1 0

Ta1 = T2/4 + T0/2 Ta2 = 0

Tb1 = T2/4 + T0/2 + T1/2 Tb2 = 0 Tc1 = Tc

Tc2 = T2/4


12a

0 -1 -1 0 0 -1 1 0 -1 1 0 0

Ta1 = T1/4 + T2/2 Ta2 = 0

Tb1 = Tc Tb2 =T1/4

Tc1 = Tc Tc2 = T1/4 + T2/2 +

T7/2

12b

0 0 -1 1 0 -1 1 0 0 1 1 0

Ta1 = T2/4 Ta2 = 0

Tb1 = T2/4 + T7/2 + T1/2

Tb2 = 0 Tc1 = Tc

Tc2 = T2/4 + T7/2


13

0 -1 -1 1 -1 -1 1 0 -1 1 0 0

Ta1 = T1/4 Ta2 = 0

Tb1 = Tc Tb2 = T1/4 +T13/2

Tc1 = Tc Tc2 = T1/4 + T13/2

+ T7/2


14

0 0 -1 1 0 -1 1 1 -1 1 1 0

Ta1 = T2/4 Ta2 = 0

Tb1 = Tc Tb2 = T2/4 + T7/2

Tc1 = Tc Tc2 = T2/4 + T7/2 +

T14/2


21a

0 0 -1 0 0 0 0 1 0 1 1 0

Ta1 = T2/4 + T0/2 + T3/2 Ta2 = 0

Tb1 = T2/4 + T0/2 Tb2 = 0 Tc1 = Tc

Tc2 = T2/4

21b

-1 0 -1 0 0 -1 0 0 0 0 1 0

Ta1 = Tc Ta2 = T3/4

Tb1 = T3/4 + T2/2 + T0/2 Tb2 = 0 Tc1 = Tc

Tc2 = T3/4 +T2/2


22a

0 0 -1 0 1 -1 0 1 0 1 1 0

Ta1 = T2/4 + T8/2 + T3/2

Ta2 = 0 Tb1 = T2/4

Tb2 = 0 Tc1 = Tc

Tc2 = T2/4 + T8/2

22b

-1 0 -1 0 0 -1 0 1 -1 0 1 0

Ta1 = Tc Ta2 = T3/4

Tb1 = T3/4 + T2/2 Tb2 = 0 Tc1 = Tc

Tc2 = T3/4 + T2/2 + T8/2


23

0 0 -1 0 1 -1 1 1 -1 1 1 0

Ta1 = T2/4 + T8/2 Ta2 = 0

Tb1 = T2/4 Tb2 = 0 Tc1 = Tc

Tc2 = T2/4 + T8/2 + T14/2


24

-1 0 -1 -1 1 -1 0 1 -1 0 1 0

Ta1 = Tc Ta2 = T3/4 + T15/2

Tb1 = T3/4 Tb2 = 0 Tc1 = Tc

Tc2 = T3/4 + T15/2 + T8/2

xxiii


31a

-1 0 -1 -1 0 0 0 0 0 0 1 0

Ta1 = Tc Ta2 = T3/4 + T4/2

Tb1 = T3/4 + T4/2+ T0/2

Tb2 = 0 Tc1 = Tc

Tc2 = T3/4

31b

-1 0 0 0 0 0 0 1 0 0 1 1

Ta1 = Tc Ta2 = T4/4

Tb1 = T4/4 + T0/2 Tb2 = 0

Tc1 = T4/4 + T0/2 + T3/2 Tc2 = 0


32a

-1 0 -1 -1 0 0 -1 1 0 0 1 0

Ta1 = Tc Ta2 = T3/4 + T4/2 +

T9/2 Tb1 = T3/4 + T4/2

Tb2 =0 Tc1 = Tc

Tc2 = T3/4

32b

-1 0 0 -1 1 0 0 1 0 0 1 1

Ta1 = Tc Ta2 = T4/4 + T9/2

Tb1 = T4/4 Tb2 = 0

Tc1 = T4/4 + T9/2 + T3/2

Tc2 = 0


33

-1 0 -1 -1 1 -1 -1 1 0 0 1 0

Ta1 = Tc Ta2 = T3/4 + T15/2

+T9/2 Tb1 = T3/4

Tb2 = 0 Tc1 = Tc

Tc2 = T3/4 + T15/2


34

-1 0 0 -1 1 0 -1 1 1 0 1 1

Ta1 = Tc Ta2 = T4/4 + T9/2

+T16/2 Tb1 = T4/4

Tb2 = 0 Tc1 = T4/4 + T9/2

Tc2 = 0


41a

-1 0 0 0 0 0 0 0 1 0 1 1

Ta1 = Tc Ta2 = T4/4

Tb1 = T4/4 + T0/2 + T5/2 Tb2 = 0

Tc1 = T4/4 + T0/2 Tc2 = 0

41b

-1 -1 0 -1 0 0 0 0 0 0 0 1

Ta1 = Tc Ta2 = T5/4 + T4/2

Tb1 = Tc Tb2 = T5/4

Tc1 = T5/4 + T4/2 + T0/2 Tc2 = 0


42a

-1 0 0 -1 0 1 0 0 1 0 1 1

Ta1 = Tc Ta2 = T4/4 + T10/2 Tb1 = T4/4 + T10/2

+ T5/2 Tb2 = 0

Tc1 = T4/4 Tc2 = 0

42b

-1 0 -1 0 0 -1 0 1 -1 0 1 0

Ta1 = Tc Ta2 = T5/4 + T4/2 +

T10/2 Tb1 = Tc

Tb2 = T5/4 Tc1 = T5/4 + T4/2

Tc2 = 0


43

-1 0 0 -1 0 1 -1 1 1 0 1 1

Ta1 = Tc Ta2 = T4/4 + T10/2

+ T16/2 Tb1 = T4/4 + T10/2

Tb2 = 0 Tc1 = T4/4

Tc2 = 0


44

-1 -1 0 -1 -1 1 -1 0 1 0 0 1

Ta1 = Tc Ta2 = T5/4 + T17/2

+ T10/2 Tb1 = Tc

Tb2 =T5/4 + T17/2 Tc1 = T5/4

Tc2 = 0

xxiv


51a

-1 -1 0 0 -1 0 0 0 0 0 0 1

Ta1 = Tc Ta2 = T5/4

Tb1 = Tc Tb2 = T5/4 + T6/2 Tc1 = T5/4 + T6/2

+ T0/2 Tc2 = 0

51b

0 -1 0 0 0 0 0 0 1 1 0 1

Ta1 = T6/4 + T0/2 + T5/2 Ta2 = 0

Tb1 = Tc Tb2 = T6/4

Tc1 = T6/4 + T0/2 Tc2 = 0


52a

-1 -1 0 0 -1 0 0 -1 1 0 0 1

Ta1 = Tc Ta2 = T5/4

Tb1 = Tc Tb2 =T5/4 + T6/2 +

T11/2 Tc1 = T5/4 + T6/2

Tc2 = 0

52b

0 -1 0 0 -1 1 0 0 1 1 0 1

Ta1 = T6/4 + T11/2+ T5/2

Ta2 = 0 Tb1 = Tc

Tb2 = T6/4 + T11/2 Tc1 = T6/4

Tc2 = 0


53

-1 -1 0 -1 -1 1 0 -1 1 0 0 1

Ta1 = Tc Ta2 = T5/4 + T17/2

Tb1 = Tc Tb2 = T5/4 +T17/2

+ T11/2 Tc1 = T5/4

Tc2 = 0


54

0 -1 0 0 -1 1 1 -1 1 1 0 1

Ta1 = T6/4 + T11/2 Ta2 = 0

Tb1 = Tc Tb2 =T6/4 + T11/2

+T18/2 Tc1 = T6/4

Tc2 = 0


61a

0 -1 0 0 0 0 1 0 0 1 0 1

Ta1 = T6/4 + T0/2 Ta2 = 0

Tb1 = Tc Tb2 = T6/4

Tc1 = T6/4 +T0/2 + T1/2 Tc2 = 0

61b

0 -1 -1 0 -1 0 0 0 0 1 0 0

Ta1 = T1/4 + T6/2 + T0/2 Ta2 = 0

Tb1 = Tc Tb2 = T1/4 +T6/2

Tc1 = Tc Tc2 = T1/4


62a

0 -1 0 1 -1 0 1 0 0 1 0 1

Ta1 = T6/4 Ta2 = 0

Tb1 = Tc Tb2 = T6/4 + T12/2 Tc1 = T6/4 + T12/2

+ T1/2 Tc2 = 0

62b

-1 0 -1 0 0 -1 0 1 -1 0 1 0

Ta1 = T1/4 + T6/2 Ta2 = 0

Tb1 = Tc Tb2 = T1/4 + T6/2 +

T/12/2 Tc1 = Tc

Tc2 = T1/4


63

0 -1 0 1 -1 0 1 -1 1 1 0 1

Ta1 = T6/4 Ta2 = 0

Tb1 = Tc Tb2 = T6/4 + T12/2

+ T18/2 Tc1 = T6/4 + T12/2

Tc2 = 0


64

0 -1 -1 1 -1 -1 1 -1 0 1 0 0

Ta1 = T1/4 Ta2 = 0

Tb1 = Tc Tb2 =T1/4 + T13/2

+T12/2 Tc1 = Tc

Tc2 = T1/4 + T13/2

xxv

Once states, application and reference times are defined, it is useful to write down a C-code to

make the computation easiest as possible. This code will be necessary to make Simulink model

run, since it is written in the S-function of the SVM.

/*3Level SPACE VECTOR*/ // Variable definition // fs_ = fs [0]; // 10000 Hz Tc = (1/fs_)/2; // 50us c_H1= (sqrt(3)*2*Tc)/(sqrt(2)* VDC); c_H2= c_H1/sqrt(3); VDC = VDC_Bus [0]; #define UN_QUARTO 2*Tc/4 #define UN_MEZZO 2*Tc/2 // PWM inizialization // Vα= Vα [0]; Vβ= Vβ [0]; H1 = (Vα *c_H1); H2 = (Vβ *c_H2); // Sector, intervals and reference times calculation // if (H2 >= 0) { if (H1 > H2) { // Sector 1 // if (H2 <= (-H1 + UN_MEZZO)) {// Region 11 // Tt1 = 2*H1 -2*H2; Tt2 = 4*H2; Tt0 = -2*H1 -2*H2 + Tc; if (Tt1 >= Tt2) {// Region 11a // T_a1 = Tt1/4+ Tt2/2 + Tt0/2; T_a2 = 0; T_b1 = Tc; T_b2 = Tt1/4; T_c1 = Tc; T_c2 = Tt1/4 + Tt2/2; } else {// Region 11b // T_a1 = Tt2/4 + Tt0/2; T_a2 = 0; T_b1 = Tt2/4 + Tt0 /2+ Tt1/2; T_b2 = 0; T_c1 = Tc; T_c2 = Tt2/4; } }

xxvi

else if (H2 >=(UN_QUARTO)) {// Region 14 // Tt2 = -2*H1 - 2*H2 +2*Tc; Tt7 = 2*H1 -2*H2; Tt14= 4*H2 -Tc; T_a1 = Tt2/4; T_a2 = 0; T_b1 = Tt2/4 + Tt7/2; T_b2 = 0; T_c1 = Tc; T_c2 = Tt2/4+Tt7/2+Tt14/2; } else if (H2 < (H1 - UN_MEZZO)) {// Region 13 // Tt1 = -2*H1 -2*H2 + 2*Tc; Tt7 = 4*H2; Tt13= 2*H1 -2*H2 -Tc; T_a1 = Tt1/4; T_a2 = 0; T_b1 = Tc; T_b2 = Tt1/4 + Tt13/2; T_c1 = Tc; T_c2 = Tt1/4 + Tt13/2 +Tt7/2; } else {// Region 12 // Tt1 = -4*H2 + Tc; Tt2 = -2*H1 + 2*H2 + Tc; Tt7 = 2*H1 +2*H2 - Tc; if (Tt1 >= Tt2) {// Region 12a // T_a1 = Tt1/4 + Tt2/2; T_a2 = 0; T_b1 = Tc; T_b2 = Tt1/4; T_c1 = Tc; T_c2 = Tt1/4 +Tt2/2 +Tt7/2; } else {// Region 12b / T_a1 = Tt2/4; T_a2 = 0; T_b1 = Tt2/4 + Tt7/2 + Tt1/2; T_b2 = 0; T_c1 = Tc; T_c2 = Tt2/4 + Tt7/2; } } } else if (-H1 >= H2) {// Sector 3 //

xxvii

if (H2 <= (H1 + UN_MEZZO)) {// Region 31 // if (Tt3 >= Tt4) {// Region 31a // } else {// Region 31b // } } else if (H2 >= UN_QUARTO) {// Region 33 // } else if (H2 <= (-H1 -UN_MEZZO)) {// Region 34 // } else {// Region 32 // if (Tt3 >= Tt4) {// Region 32a // } else {// Region 32b // } } } else {// Sector 2 // if (H2 > UN_QUARTO) { if (H2 >= (-H1 + UN_MEZZO)) {// Region 23 // } else if (H2 > (H1 + UN_MEZZO)) {// Region 24 // } else {// Region 22 // if (Tt2 >= Tt3) {// Region 22a // } else {// Region 22b // } } } else {// Region 21 // if (Tt2 >= Tt3) {// Region 21a // } else {// Region 21b // } }

xxviii

} } else { if (H2 >= -H1) {// Sector 6 // if (H2 >= (H1 -UN_MEZZO)) {// Region 61 // if (Tt6 >= Tt1) {// Region 61a // } else {// Region 61b // } } else if (H2 <= - UN_QUARTO) {// Region 63 // } else if (H2 >= (-H1 +UN_MEZZO)) {// Region 64 // } else {// Region 62 // if (Tt6 >= Tt1) {// Region 62a // } else {// Region 62b // } } } else if (H1 < H2) {// Sector 4 // if (H2 <= -UN_QUARTO) {// Region 44 // } else if (H2 > (H1 +UN_MEZZO)) {// Region 43 // } else if (H2 >= (-H1 -UN_MEZZO)) {// Region 41 // if (Tt4 >= Tt5) {// Region 41a // } else {// Region 41b // } } else {// Region 42 // if (Tt4 >= Tt5) {// Region 42a // } else

xxix

{// Region 42b // } } } else {// Sector 5// if (H2 >= -UN_QUARTO) {// Region 51 // if (Tt5 >= Tt6) {// Region 51a // } else {// Region 51b // } } else if (H2 < (-H1 -UN_MEZZO)) {// Region 53 // } else if (H2 <= (H1 -UN_MEZZO)) {// Region 54 // } else {// Region 52 // if (Tt5 >= Tt6) {// Region 52a // } else {// Region 52b // } } } } Out [0] = T_a1; Out [1] = T_a2; Out [2] = T_b1; Out [3] = T_b2; Out [4] = T_c1; Out [5] = T_c2;

Figure C-6 3Level inverter S-function.

Documents

OPERATION OF TRANSFORMERLESS INVERTERS, PARALLEL … · IV Figure 2.19 3Level Triangular carrier signals modification block. 27 Figure 2.20 3Level inverter SPWM comparator. 28 Figure