Operating Systems - University of Limerickgarryowen.csisdmz.ul.ie/~cs4023/resources/lect20.pdf · Main Memory (II) Operating Systems P. Healy CS1-08 Computer Science Bldg. tel: 202727

Main Memory (II)

Operating Systems

P. Healy

CS1-08Computer Science Bldg.

tel: [email protected]

Autumn 2019–2020

P. Healy (University of Limerick) CS4023 Autumn 2019–2020 1 / 24

Main Memory (II)

Outline

1 Main Memory (II)Paging / Paging HardwareShared PagesSegmentation


Main Memory (II)Paging / Paging HardwareShared PagesSegmentation

Outline




Paging

Physical address space of a process can benoncontiguous; process is allocated physical memorywhenever the latter is availableDivide physical memory into fixed-sized blocks calledframes (size is power of 2, between 512 bytes and 8,192bytes; 4,096 on linux)Divide logical memory into blocks of same size calledpagesKeep track of all free framesTo run a program of size x pages, need to find x freeframes and load the program into themSet up a page table to translate logical to physicaladdresses



Address Translation Scheme

Address generated by CPU is divided into 2 pieces:Page number (p) – used as an index into a page tablewhich contains base address of each page in physicalmemoryPage offset (d) – combined with base address to define thephysical memory address that is sent to the memory unit

page number page offsetp d

(m − n) bits n bits

For given logical address space 2m (m bits) and page size2n

nowadays, m = 64 and on linux n = 12: 52 bits for page no.



Paging Hardware



Paging Model of Logical and Physical Memory



Paging Example – really tiny example

16-byte logical address space (m = 4)4-byte pages (n = 2)(32-byte physical memory)



Free Frames



Implementation of Page Table

Page table is kept in main memoryPage-table base register (PTBR) points to the page tablePage-table length register (PTLR) indicates size of thepage tableIn this scheme every data/instruction access requires twomemory accesses: one for the page table and one for thedata/instructionThe two memory access problem can be solved by the useof a special fast-lookup hardware cache called associativememory or translation look-aside buffers (TLBs)Some TLBs store address-space identifiers (ASIDs) ineach TLB entry – uniquely identifies each process toprovide address-space protection for that process



Associative Memory

Associative memoryAnswers “do I know about item x?”Does it in (almost always) one clock cycle!Analogy: find me the index in an array where the value(say) 1.34 is stored; do this in one clock cycleParallel search!

Address translation (p,d)If p is in associative register, return corresponding frame no.Otherwise get frame number from page table in memory



Paging Hardware With TLB



Memory Protection

Memory protection implemented by associating protectionbit with each frameValid-invalid bit attached to each entry in the page table:

“valid” indicates that the associated page is in the process’logical address space, and is thus a legal page“invalid” indicates that the page is not in the process’ logicaladdress space



Valid (v) or Invalid (i) Bit In A Page Table

Page size 2KBSystem with logical address space 8 × 2K = 16K: 14-bitaddress space, 0 – 16383Program only uses addresses 0 – 10468internal fragmentation: 10469 – 16383213 = 8192 < 10468 < 16383 = 214 − 1 (see table)


http://www.vaughns-1-pagers.com/computer/powers-of-2.htm


Outline




Shared Pages

Shared codeOne copy of read-only (reentrant) code shared amongprocesses (i.e., text editors, compilers, window systems)Shared code must appear in same location in the logicaladdress space of all processes

Private code and dataEach process keeps a separate copy of the code and dataThe pages for the private code and data can appearanywhere in the logical address space



Shared Pages Example



Outline




Segmentation

Memory-management scheme that supports user view ofmemoryA program is a collection of segments

A segment is a logical unit such as:main programprocedurefunctionmethodobjectlocal variables, global variablescommon block (FORTRAN prog. language)stacksymbol tablearrays



User’s View of a Program

segments differentlysizedeach segment is putsomewhere in memorynot necessarilyconsecutively orderedmemory no longerdivided in to equalframes



Segmentation Architecture

Logical address consists of a two-tuple:<segment-number, offset>

Segment table – maps two-dimensional physicaladdresses; each table entry has:

base – contains the starting physical address where thesegment resides in memorylimit – specifies the length of the segment

Segment-table base register (STBR) points to thesegment table’s location in memorySegment-table length register (STLR) indicates numberof segments used by a program:

segment number s is legal if s < STLR



Segmentation Hardware



Example of Segmentation



Example: Intel Pentium

Supports both segmentation and segmentation with pagingCPU generates logical address

Given to segmentation unitWhich produces linear addresses

Linear address given to paging unitWhich generates physical address in main memoryPaging units form equivalent of MMU


Documents

Operating Systems - University of Limerickgarryowen.csisdmz.ul.ie/~cs4023/resources/lect20.pdf · Main Memory (II) Operating Systems P. Healy CS1-08 Computer Science Bldg. tel: 202727