OPA2211-EP 1.1-nV/√HzNoise, Low-Power, Precision Operational

Voltage N

ois

e D

ensity (

nV

/)

√H

z

0.1

100

1

Frequency (Hz)

100k101

10

100 1k 10k

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

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OPA2211-EPSBOS761 –NOVEMBER 2015

OPA2211-EP 1.1-nV/√Hz Noise, Low-Power, Precision Operational Amplifier1 Features 3 Description

The OPA2211-EP series of precision operational1• Low Voltage Noise: 1.1 nV/√Hz at 1 kHz

amplifiers achieves very-low 1.1-nV/√Hz noise density• Input Voltage Noise: 80 nVPP (0.1 to 10 Hz) with a supply current of only 3.6 mA. This series also• THD+N: –136 dB (G = 1, ƒ = 1 kHz) offers rail-to-rail output swing, which maximizes

dynamic range.• Offset Voltage: 180 μV (Max)• Offset Voltage Drift: 0.35 μV/°C (Typ) The extremely low voltage and low current noise,

high speed, and wide output swing of the OPA2211-• Low Supply Current: 3.6 mA/Ch (Typ)EP series make these devices an excellent choice as• Unity-Gain Stable a loop filter amplifier in PLL applications.

• Gain Bandwidth Product:In precision data acquisition applications, the80 MHz (G = 100)OPA2211-EP series of operational amplifiers45 MHz (G = 1) provides 700-ns settling time to 16-bit accuracy

• Slew Rate: 27 V/μs throughout 10-V output swings. This AC performance,• 16-Bit Settling: 700 ns combined with only 125 μV of offset and 0.35 μV/°C

of drift over temperature, makes the OPA2211-EP• Wide Supply Range:ideal for driving high-precision 16-bit analog-to-digital±2.25 V to ±18 V, +4.5 V to +36 Vconverters (ADCs) or buffering the output of high-

• Rail-to-Rail Output resolution digital-to-analog converters (DACs).• Output Current: 30 mA The OPA2211-EP is specified over a wide dual-power• Supports Defense, Aerospace, and Medical supply range of ±2.25 V to ±18 V, or for single-supply

Applications operation from 4.5 to 36 V.– Controlled Baseline The OPA2211-EP is available in a small DFN-8 (3-– One Assembly and Test Site mm × 3-mm) package. These operational amplifiers

are specified from TJ = –55°C to 125°C.– One Fabrication Site– Available in Military (–55°C to 125°C) Device Information(1)

Temperature Range (1)PART NUMBER PACKAGE BODY SIZE (NOM)

– Extended Product Life Cycle OPA2211-EP WSON (8) 3.00 mm × 3.00 mm– Extended Product-Change Notification

(1) For all available packages, see the orderable addendum at– Product Traceability the end of the data sheet.

Voltage Noise Density vs Frequency2 Applications• PLL Loop Filter• Low-Noise, Low-Power Signal Processing• 16-Bit ADC Drivers• DAC Output Amplifiers• Active Filters• Low-Noise Instrumentation Amplifiers• Ultrasound Amplifiers• Professional Audio Preamplifiers• Low-Noise Frequency Synthesizers• Infrared Detector Amplifiers• Hydrophone Amplifiers• Geophone Amplifiers• Medical(1) Additional temperature ranges available - contact factory

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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OPA2211-EPSBOS761 –NOVEMBER 2015 www.ti.com

Table of Contents7.4 Device Functional Modes........................................ 161 Features .................................................................. 1

8 Application and Implementation ........................ 172 Applications ........................................................... 18.1 Application Information............................................ 173 Description ............................................................. 18.2 Typical Application ................................................. 194 Revision History..................................................... 2

9 Power Supply Recommendations ...................... 225 Pin Configuration and Functions ......................... 39.1 Operating Voltage ................................................... 226 Specifications......................................................... 4

10 Layout................................................................... 226.1 Absolute Maximum Ratings ..................................... 410.1 Layout Guidelines ................................................. 226.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 236.3 Recommended Operating Conditions....................... 410.3 Thermal Considerations ........................................ 236.4 Thermal Information .................................................. 4

11 Device and Documentation Support ................. 246.5 Electrical Characteristics: VS = ±2.25 to ±18 V......... 511.1 Community Resources.......................................... 246.6 Typical Characteristics .............................................. 711.2 Trademarks ........................................................... 247 Detailed Description ............................................ 1411.3 Electrostatic Discharge Caution............................ 247.1 Overview ................................................................. 1411.4 Glossary ................................................................ 247.2 Functional Block Diagram ....................................... 14

12 Mechanical, Packaging, and Orderable7.3 Feature Description................................................. 14Information ........................................................... 24

4 Revision History

DATE REVISION NOTESNovember 2015 * Initial release.

2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: OPA2211-EP


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1

2

3

4

8

7

6

5

V+

OUT B

IN B

+IN B

OUT A

IN A

+IN A

V

Pad(1)

A

B

OPA2211-EPwww.ti.com SBOS761 –NOVEMBER 2015

5 Pin Configuration and Functions

DRG Package8-Pin WSON

Top View

(1) Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the thermal pad improves heatdissipation and provides specified performance

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

+IN A 3 I Noninverting input for channel A–IN A 2 I Inverting input for channel A+IN B 5 I Noninverting input for channel B–IN B 6 I Inverting input for channel BOUT A 1 O Output terminal for channel AOUT B 7 O Output terminal for channel BV+ 8 — Positive supply voltageV– 4 — Negative supply voltage

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3



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6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITSupply voltage VS = (V+) – (V–) 40 VInput voltage (V–) – 0.5 (V+) + 0.5 VInput current (any pin except power-supply pins) –10 10 mAOutput short-circuit (2) ContinuousJunction temperature, TJ 150 °CStorage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.

6.2 ESD RatingsVALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000ElectrostaticV(ESD) Vdischarge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITSupply voltage (V+ – V–) 4.5 (±2.25) 36 (±18) VOperating temperature, TJ –55 125 °C

6.4 Thermal InformationOPA2211-EP

THERMAL METRIC (1) DRG (WSON) UNIT8 PINS

RθJA Junction-to-ambient thermal resistance 47.3 °C/WRθJC(top) Junction-to-case (top) thermal resistance 51.8 °C/WRθJB Junction-to-board thermal resistance 21.8 °C/WψJT Junction-to-top characterization parameter 0.7 °C/WψJB Junction-to-board characterization parameter 21.9 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 4.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.




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6.5 Electrical Characteristics: VS = ±2.25 to ±18 Vat TJ = 25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITOFFSET VOLTAGEInput offset voltage VOS VS = ±15 V ±50 ±175 μV

Over temperature TJ = –55°C to 125°C ±350 µVDrift dVOS/dT TJ = –55°C to 125°C 0.35 μV/°Cvs power supply PSRR VS = ±2.25 V to ±18 V 0.1 1 μV/V

Over temperature 3 μV/VINPUT BIAS CURRENTInput bias current IB VCM = 0 V, TJ = –55°C to 125°C ±50 ±350 nAOffset current IOS VCM = 0 V, TJ = –55°C to 125°C ±20 ±200 nANOISEInput voltage noise en ƒ = 0.1 Hz to 10 Hz 80 nVPP

ƒ = 10 Hz 2 nV/√HzInput voltage noise density ƒ = 100 Hz 1.4 nV/√Hz

ƒ = 1 kHz 1.1 nV/√Hzƒ = 10 Hz 3.2 pA/√Hz

Input current noise density In ƒ = 1 kHz 1.7 pA/√HzINPUT VOLTAGE RANGE

VS ≥ ±5 V (V–) + 1.8 (V+) – 1.4 VCommon-mode voltage range VCM VS < ±5 V (V–) + 2 (V+) – 1.4 V

VS ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V, 114 120 dBTJ = –55°C to 125°CCommon-mode rejection ratio CMRR

VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V, 106 120 dBTJ = –55°C to 125°CINPUT IMPEDANCEDifferential 20k || 8 Ω || pFCommon-mode 109 || 2 Ω || pFOPEN-LOOP GAIN

(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2V, 114 130 dBRL = 10 kΩ, TJ = –55°C to 125°COpen-loop voltage gain AOL (V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V, 110 114 dBRL = 600 Ω

(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6V,Over temperature AOL 100 dBIO ≤ 15 mA, TJ = –55°C to 125°CFREQUENCY RESPONSE

G = 100 80 MHzGain-bandwidth product GBW

G = 1 45 MHzSlew rate SR 27 V/μs

VS = ±15 V, G = –1, 10-V step, CL = 100Settling time, 0.01% tS 400 nspFVS = ±15 V, G = –1, 10-V step, CL = 1000.0015% (16-bit) 700 nspF

Overload recovery time G = –10 500 nsG = +1, ƒ = 1kHz, 0.000015VO = 3VRMS, RL = 600 Ω %Total harmonic distortion + noise THD+N

–136 dB




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Electrical Characteristics: VS = ±2.25 to ±18 V (continued)at TJ = 25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITOUTPUT

RL = 10 kΩ, AOL ≥ 114 dB, TJ = –55°C to (V–) + 0.2 (V+) – 0.2 V125°CVoltage output VOUTRL = 600 Ω, AOL ≥ 110 dB (V–) + 0.6 (V+) – 0.6 VIO < 15 mA, AOL ≥ 100 dB, TJ = –55°C to (V–) + 0.6 (V+) – 0.6 V125°C

Short-circuit current ISC +30/–45 mACapacitive load drive CLOAD See Typical Characteristics pFOpen-loop output impedance ZO ƒ = 1MHz 5 ΩPOWER SUPPLYSpecified voltage VS ±2.25 ±18 VQuiescent current (per channel) IQ IOUT = 0 A 3.6 4.5 mA

Over temperature TJ = –55°C to 125°C 6 mATEMPERATURE RANGEOperating range TJ –55 125 °C




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PS

RR

(d

B)

1 10

160

140

100

80

60

40

0

Frequency (Hz)

100M10k100 1k 100k

20

120

1M 10M

-PSRR

+PSRR

CM

RR

(dB

)

10k

140

100

80

60

40

0

Frequency (Hz)

100M1M100k

20

120

10M

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

10

Frequency (Hz)

100k100 1k 10k

V = ±15VS

V = 3.5VIN RMS

G = 1R = 600L W

R = 2kL W

R = 5kL W

Ch

an

ne

l S

ep

ara

tio

n (

dB

)

20

nV

/div

Time (1s/div)

Curr

ent N

ois

e D

ensity (

pA

/)

ÖH

z

0.1

100

10

1

Frequency (Hz)

100k101 100 1k 10k

Vo

lta

ge

No

ise

De

nsity (

nV

/)

ÖH

z

0.1

100

1

Frequency (Hz)

100k101

10

100 1k 10k


6.6 Typical CharacteristicsAt TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.

Figure 1. Input Voltage Noise Density vs Frequency Figure 2. Input Current Noise Density vs Frequency

Figure 4. 0.1-Hz to 10-Hz NoiseFigure 3. Channel Separation vs Frequency

Figure 5. Power-Supply Rejection Ratio vs Frequency Figure 6. Common-Mode Rejection Ratio vs Frequency(Referred to Input)




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Iand I

Bia

s C

urr

ent (n

A)

BO

S

-50

200

150

100

50

0

50

100

150

200

-

-

-

-

Ambient Temperature ( C)°

150-25 0 25

IOS

+IB

50 10075 125

-IB

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

Offset Voltage Drift (mV/°C)

Popula

tion

-1

25

.0

-1

12

.5

-1

00

.0

-7

5.0

-6

2.5

-5

0.0

-3

7.5

-2

5.0

-1

2.5 0

12

.5

25

.0

37

.5

50

.0

62

.5

75

.0

87

.5

10

0.0

11

2.5

12

5.0

Offset Voltage ( V)m

Po

pu

latio

n

-8

7.5

Open-L

oop G

ain

(V

/V)

m

-75

5

-5

Temperature ( C)°

200

2

-50 -25 0

3

4

25 7550

1

100 125 150 175

0

-1

-2

-3

-4

300mV Swing From Rails

200mV Swing From Rails

R = 10kWL

Z(

)W

O

10

10k

0.1

Frequency (Hz)

100M

1

100 1k 10k

10

100

1k

100k 10M1M

Gain

(dB

)

100 1k

140

120

100

80

60

40

-20

Frequency (Hz)

100M1M10k 100k 10M

20

0

Phase (

)°

180

135

90

45

0

Gain

Phase


Typical Characteristics (continued)At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.

Figure 7. Open-Loop Output Impedance vs Frequency Figure 8. Gain and Phase vs Frequency

Figure 10. Offset Voltage Production DistributionFigure 9. Normalized Open-Loop Gain vs Temperature

Figure 11. Offset Voltage Drift Production Distribution Figure 12. IB and IOS Current vs Temperature




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I(n

A)

B

2.25

150

-150

V ( V)±S

184 6

100

8 10

50

12 14 16

-IB

+IB

Unit 1 Unit 2

Unit 3

3 Typical Units Shown

0

-50

-100

I(n

A)

B

1

150

-150

V (V)CM

355 10

100

15 20 25 30

0

-100

50

-50

Common-Mode Range

-IB

+IB

Unit 1 Unit 2

Unit 3

V = 36V

3 Typical Units ShownS

I(n

A)

OS

2.25

100

-100

V ( V)±S

18

20

4 6

40

60

80

8 10 12 14 16

0

-20

-40

-60

-80


I(n

A)

OS

1

100

-100

V (V)CM

35

75

5 10 15 20 25 30

0

-75

50

25

-25

-50

Common-Mode Range

V = 36V

3 Typical Units ShownS

VS

hift (

V)

mO

S

0

12

-12

Time (s)

60

4

10 20 30

6

8


2

0

-2

-4

-6

-8

-10

40 50

2000

1500

1000

500

0

-500

-1000

-1500

-2000(V )+1.0- (V )+1.5- (V )+2.0- (V+) 1.5- (V+) 1.0- (V+) 0.5-

V (V)CM

V(

V)

mO

S



Figure 13. Offset Voltage vs Common-Mode Voltage Figure 14. VOS Warmup

Figure 15. Input Offset Current vs Supply Voltage Figure 16. Input Offset Current vs Common-Mode Voltage

Figure 17. Input Bias Current vs Supply Voltage Figure 18. Input Bias Current vs Common-Mode Voltage




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20m

V/d

iv

Time (0.1µs/div)

G = -1C = 10pFL

+18V

-18V

RF

604W

RI

604W

CF

5.6pF

CL

OPA211

20m

V/d

iv

Time (0.1µs/div)

G = -1C = 100pFL

+18V

-18V

RF

604W

RI

604W

CF

5.6pF

CL

OPA211

IS

hift

(mA

)Q

0

0.05

-0.30

Time (s)

600

-0.15

60 120 180

-0.10

-0.05

0

240 360300

-0.20

-0.25

420 480 540

Average of 10 Typical Units

I(m

A)

SC

-75

60

-60

Temperature ( C)°

200

20

-50 -25 0

30

40

50

25 7550

10

0

-10

100 125

-20

-30

-40

-50

150 175

Sourcing

Sinking

I(m

A)

Q

-75

6

0

Temperature ( C)°

200

2

-50 -25 0

3

4

5

25 7550

1

100 125 150 175

I(m

A)

Q

0

4.0

0

V (V)S

36

2.0

4 8 12

2.5

3.0

3.5

16 2420

1.5

1.0

0.5

28 32



Figure 20. Quiescent Current vs Supply VoltageFigure 19. Quiescent Current vs Temperature

Figure 22. Short-Circuit Current vs TemperatureFigure 21. Normalized Quiescent Current vs Time

Figure 24. Small-Signal Step Response (100 mV)Figure 23. Small-Signal Step Response (100 mV)




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0 100 200 300 400 500 1000600 700 800 900

Time (ns)

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

DF

rom

Fin

al V

alu

e (

mV

)

0.010

0.008

0.006

0.004

0.002

0

-0.002

-0.004

-0.006

-0.008

-0.010

DF

rom

Fin

al V

alu

e (%

)

16-Bit Settling

( 1/2 LSB = 0.00075%)± ±

2V

/div

Time (0.5 s/div)m

G = +1

C = 100pF

R = 600L

L W

R = 100WF

R = 0WF

Note: See the

section, .

Applications Information

Input Protection

Ove

rsh

oo

t (%

)

0 200

60

50

40

30

20

10

0

Capacitive Load (pF)

1400800400 600 1000 1200

G = +1

G = 1-

G = 10

2V

/div

Time (0.5 s/div)m

G = 1

C = 100pF

R = 600

-

W

L

L

20

mV

/div

Time (0.1 s/div)m

G = +1

R = 600

C = 10pFL W

L

+18V

-18V CLRL

OPA211

20

mV

/div

Time (0.1 s/div)m

G = +1

R = 600

C = 100pFL W

L

+18V

-18V CLRL

OPA211



Figure 25. Small-Signal Step Response (100 mV) Figure 26. Small-Signal Step Response (100 mV)

Figure 27. Small-Signal Overshoot vs Capacitive Load Figure 28. Large-Signal Step Response(100-mV Output Step)

Figure 30. Large-Signal Positive Settling TimeFigure 29. Large-Signal Step Response(10 VPP, CL = 100 pF)




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0 10 20 30 40 50 7060

I (mA)OUT

20

15

10

5

0

-5

-10

-15

-20

V(V

)O

UT

+125 C°

0 C°

+85 C°

+125 C°

+85 C°

+150 C°- °55 C 0 C°

5V

/div

Time (0.5 s/div)m

0V

VIN

VOUT

G = 10-

1kW

10kW

VIN

VOUTOPA211

0 100 200 300 400 500 1000600 700 800 900

Time (ns)

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

DF

rom

Fin

al V

alu

e (

mV

)

0.010

0.008

0.006

0.004

0.002

0

-0.002

-0.004

-0.006

-0.008

-0.010

DF

rom

Fin

al V

alu

e (%

)

16-Bit Settling

( 1/2 LSB = 0.00075%)± ±

5V

/div

Time (0.5 s/div)m

0V

VIN

VOUT

G = 10-

1kW

10kW

VIN

VOUTOPA211

0 100 200 300 400 500 1000600 700 800 900

Time (ns)

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

DF

rom

Fin

al V

alu

e (

mV

)

0.010

0.008

0.006

0.004

0.002

0

-0.002

-0.004

-0.006

-0.008

-0.010

DF

rom

Fin

al V

alu

e (%

)

16-Bit Settling

( 1/2 LSB = 0.00075%)± ±

0 100 200 300 400 500 1000600 700 800 900

Time (ns)

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

Dro

m F

inal V

Falu

e (

mV

)

0.010

0.008

0.006

0.004

0.002

0

-0.002

-0.004

-0.006

-0.008

-0.010

DF

rom

Fin

al V

alu

e (%

)

16-Bit Settling

( 1/2 LSB = 0.00075%)± ±



Figure 32. Large-Signal Negative Settling Time (10 VPP, CL =Figure 31. Large-Signal Positive Settling Time (10 VPP, CL =100 pF)10 pF)

Figure 33. Large-Signal Negative Settling Time (10 VPP, CL = Figure 34. Negative Overload Recovery10 pF)

Figure 35. Positive Overload Recovery Figure 36. Output Voltage vs Output Current




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5V

/div

0.5ms/div

Output

+18V

-18V37VPP

( 18.5V)±

OutputOPA211



Figure 37. No Phase Reversal




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IN-

Pre-Output Driver OUT

IN+

V-

V+


7 Detailed Description

7.1 OverviewThe OPA2211-EP is a unity-gain stable, precision operational amplifier with very low noise. Applications withnoisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases,0.1-μF capacitors are adequate. Functional Block Diagram shows a simplified schematic of the OPA2211-EP.This die uses a SiGe bipolar process and contains 180 transistors.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Input ProtectionThe input terminals of the OPA2211-EPFigure 38 are protected from excessive differential voltage with back-to-back diodes, as shown in . In most circuit applications, the input protection circuitry has no consequence.However, in low-gain or G = 1 circuits, fast ramping input signals can forward bias these diodes because theoutput of the amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 29 inthe Typical Characteristics. If the input signal is fast enough to create this forward bias condition, the input signalcurrent must be limited to 10 mA or less. If the input signal current is not inherently limited, an input seriesresistor can be used to limit the signal input current. This input series resistor degrades the low-noiseperformance of the OPA2211-EP, and is discussed in Noise Performance. Figure 38 shows an exampleimplementing a current-limiting feedback resistor.




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100k 1M

Source Resistance, R ( )ΩS

100 1k 10k

10k

1k

100

10

1

Votlage N

ois

e S

pectr

al D

ensity,

EO

RS

EO

E = eO n S+ (i R ) + 4kTRn S

2 2 2

Resistor Noise

OPA227

OPA211

OPA2211-EP Output

RF

Input

-

+RI


Feature Description (continued)

Figure 38. Pulsed Operation

7.3.2 Noise PerformanceFigure 39 shows total circuit noise for varying source impedances with the operational amplifier in a unity-gainconfiguration (no feedback resistor network, and therefore no additional noise contributions). Two differentoperational amplifiers are shown with total circuit noise calculated. The OPA2211-EP has very low voltage noise,making it ideal for low source impedances (<2 kΩ). A similar precision operational amplifier, the OPA227, hassomewhat higher voltage noise but lower current noise. It provides excellent noise performance at moderatesource impedance (10 kΩ to 100 kΩ). Above 100 kΩ, a FET-input operational amplifier such as the OPA132(very-low current noise) may provide improved performance. The equation in Figure 39 is shown for thecalculation of the total circuit noise. Note that en = voltage noise, In = current noise, RS = source impedance, k =Boltzmann’s constant = 1.38 × 10–23 J/K, and T is temperature in K.

Figure 39. Noise Performance of the OPA2211-EP and OPA227 in Unity-Gain Buffer Configuration

7.3.3 Basic Noise CalculationsDesign of low-noise operational amplifier circuits requires careful consideration of a variety of possible noisecontributors: noise from the signal source, noise generated in the operational amplifier, and noise from thefeedback network resistors. The total noise of the circuit is the root-sum-square combination of all noisecomponents.

The resistive portion of the source impedance produces thermal noise proportional to the square root of theresistance. This function is plotted in Figure 39. The source impedance is usually fixed; consequently, select theoperational amplifier and the feedback resistors to minimize the respective contributions to the total noise.




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Feature Description (continued)Figure 39 depicts total noise for varying source impedances with the operational amplifier in a unity-gainconfiguration (no feedback resistor network, and therefore no additional noise contributions). The operationalamplifier itself contributes both a voltage noise component and a current noise component. The voltage noise iscommonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying component of the input bias current and reacts with the source resistance to create a voltage componentof noise. Therefore, the lowest noise operational amplifier for a given application depends on the sourceimpedance. For low source impedance, current noise is negligible and voltage noise generally dominates. Forhigh source impedance, current noise may dominate.

Figure 41 shows both inverting and noninverting operational amplifier circuit configurations with gain. In circuitconfigurations with gain, the feedback network resistors also contribute noise. The current noise of theoperational amplifier reacts with the feedback resistors to create additional noise components. The feedbackresistor values can generally be chosen to make these noise sources negligible. The equations for total noise areshown for both configurations.

7.3.4 Total Harmonic Distortion MeasurementsOPA2211-EP series operational amplifiers have excellent distortion characteristics. THD + Noise is below0.0002% (G = +1, VOUT = 3 VRMS) throughout the audio frequency range, 20 Hz to 20 kHz, with a 600-Ω load.

The distortion produced by OPA2211-EP series operational amplifiers is below the measurement limit of manycommercially available distortion analyzers. However, a special test circuit illustrated in Figure 42 can be used toextend the measurement capabilities.

Operational amplifier distortion can be considered an internal error source that can be referred to the input.Figure 42 shows a circuit that causes the operational amplifier distortion to be 101 times greater than thatnormally produced by the operational amplifier. The addition of R3 to the otherwise standard noninvertingamplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged,but the feedback available for error correction is reduced by a factor of 101, thus extending the resolution by 101.Note that the input signal and load applied to the operational amplifier are the same as with conventionalfeedback without R3. The value of R3 should be kept small to minimize its effect on the distortion measurements.

Validity of this technique can be verified by duplicating measurements at high gain and/or high frequency wherethe distortion is within the measurement capability of the test equipment. Measurements for this data sheet weremade with an Audio Precision System Two distortion/noise analyzer, which greatly simplifies such repetitivemeasurements. The measurement technique can, however, be performed with manual distortion measurementinstruments.

7.4 Device Functional ModesThe OPAx211 has a single functional mode and is operational when the power-supply voltage is greater than 4.5V (±2.25 V). The maximum power supply voltage for the OPAx211 is 36 V (±18 V).




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8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Electrical OverstressDesigners often ask questions about the capability of an operational amplifier to withstand electrical overstress.These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the outputpin. Each of these different pin functions have electrical stress limits determined by the voltage breakdowncharacteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them fromaccidental ESD events both before and during product assembly.

It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstressevent. Figure 40 illustrates the ESD circuits contained in the OPA2211-EP (indicated by the dashed line area).The ESD protection circuitry involves several current-steering diodes connected from the input and output pinsand routed back to the internal power-supply lines, where they meet at an absorption device internal to theoperational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.

An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed toprovide a current path around the operational amplifier core to prevent it from being damaged. The energyabsorbed by the protection circuitry is then dissipated as heat.

When an ESD voltage develops across two or more of the amplifier device pins, current flows through one ormore of the steering diodes. Depending on the path that the current takes, the absorption device may activate.The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of theOPA2211-EP but below the device breakdown voltage level. Once this threshold is exceeded, the absorptiondevice quickly activates and clamps the voltage across the supply rails to a safe level.

When the operational amplifier connects into a circuit such as that illustrated in Figure 40, the ESD protectioncomponents are intended to remain inactive and not become involved in the application circuit operation.However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on,and conduct current. Any such current flow occurs through steering diode paths and rarely involves theabsorption device.




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RF

Op-AmpCore

RI

RL

V(1)

IN

ID

-In

Out

+In

ESD Current-Steering Diodes

Edge-Triggered ESDAbsorption Circuit

+VS

+V

-V

-VS

OPA2211-EP


Application Information (continued)

(1) VIN = +VS + 500 mV

Figure 40. Equivalent Internal ESD Circuitry and its Relation to a Typical Circuit Application

Figure 40 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by500mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink thecurrent, one of the upper input steering diodes conducts and directs current to +VS. Excessively high currentlevels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend thatapplications limit the input current to 10mA.

If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, andthen take over as the source of positive supply voltage. The danger in this case is that the voltage can rise tolevels that exceed the operational amplifier absolute maximum ratings. In extreme but rare cases, the absorptiondevice triggers on while +VS and –VS are applied. If this event happens, a direct current path is establishedbetween the +VS and –VS supplies. The power dissipation of the absorption device is quickly exceeded, and theextreme internal heating destroys the operational amplifier.

Another common question involves what happens to the amplifier if an input signal is applied to the input whilethe power supplies +VS and/or –VS are at 0 V. Again, it depends on the supply characteristic while at 0V, or at alevel below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifiersupply current may be supplied by the input source via the current steering diodes. This state is not a normalbias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then thecurrent through the steering diodes can become quite high. The current level depends on the ability of the inputsource to deliver current, and any resistance in the input path.




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R2

OPA2211-EP

R1

Signal Gain = 1+

Distortion Gain = 1+

R3 VOUT

GeneratorOutput

AnalyzerInput

Audio Precision

System Two(1)

with PC Controller

Load

SIG.

GAIN

DIST.

GAIN R1 R2 R3

¥

100W

1kW

1kW

10W

11W

1

11

101

101R2

R1

R2

R II R1 3

R1

R2

EO

R1

R2

EORS

VS

RS

VS

Noise in Noninverting Gain Configuration

Noise in Inverting Gain Configuration

Noise at the output:

E =O

2

Where e = ÖS S4kTR ´ = thermal noise of RS

2

1 +R2

R1

e + en 1 2 n 2 S S+ e + (i R ) + e + (i

nR )

2 2 2 2 2 2

1 +R2

R1

R2

R1

e = Ö1 14kTR ´ = thermal noise of R1

2

1 +R2

R1

e = Ö2 2 24kTR = thermal noise of R

Noise at the output:

E =O

2

Where e = 4kTRÖS S ´ = thermal noise of RS

2

1 +R2

R + R1 S

e + en 1 2 n 2 S+ e + (i R ) + e2 2 2 2 2

R2

R + R1 S

R2

R + R1 S

e = 4kTRÖ1 1 ´ = thermal noise of R1

e = 4kTRÖ2 2 2= thermal noise of R

For the OPA211 series op amps at 1kHz, e = 1.1nV/ Hz and i = 1.7pA/ Hz.Ö Ön n


8.2 Typical Application

Figure 41. Noise Calculation in Gain Configurations

(1) For measurement bandwidth, see Figure 43, Figure 44, and Figure 45.

Figure 42. Distortion Test Circuit




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Tota

l H

arm

onic

Dis

tort

ion +

Nois

e (

%) T

ota

l Harm

onic

Dis

tortio

n +

Nois

e (d

B)

10

Frequency (Hz)

20k100 1k 10k

0.001

0.0001

0.00001

-100

-120

-140

V = 15VS

V = 3VOUT RMS

Measurement BW = 80kHz

G = 1

G = 11

G = 1R = 600L W

R = 600L W

R = 5kL W

Tota

l H

arm

onic

Dis

tort

ion +

Nois

e (

%)

0.01

0.1

0.000001

Output Voltage Amplitude (V )RMS

100

0.00001

0.1 1 10

0.0001

0.001

0.01

V = 15V

R = 600W

1kHz Signal

S

L

±

-60

-160

-140

-120

-100

-80

Tota

l Harm

onic

Dis

tortio

n +

Nois

e (d

B)

G = 1

G = 11

G = -1Measurement BW = 80kHz

2

1

RSignal Gain 1

R


Typical Application (continued)8.2.1 Design RequirementsThe design requirements for Signal Gain = 11 are:

where• Supply voltage: 30 V (±15 V)• R1 = 100 Ω• R2 = 1 kΩ• R3 = 11 Ω (1)

8.2.2 Detailed Design Procedure

8.2.2.1 Total Harmonic Distortion MeasurementsOPA2211-EP series operational amplifiers have excellent distortion characteristics. THD + Noise is below0.0002% (G = +1, VOUT = 3VRMS) throughout the audio frequency range, 20 Hz to 20 kHz, with a 600-Ω load.The distortion produced by OPA2211-EP series operational amplifiers is below the measurement limit of manycommercially available distortion analyzers. However, a special test circuit illustrated in Figure 47 can be used toextend the measurement capabilities.

Operational amplifier distortion can be considered an internal error source that can be referred to the input.Figure 47 shows a circuit that causes the operational amplifier distortion to be 101 times greater than thatnormally produced by the operational amplifier. The addition of R3 to the otherwise standard noninvertingamplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged,but the feedback available for error correction is reduced by a factor of 101, thus extending the resolution by 101.Note that the input signal and load applied to the operational amplifier are the same as with conventionalfeedback without R3. The value of R3 should be kept small to minimize its effect on the distortion measurements.

Validity of this technique can be verified by duplicating measurements at high gain and/or high frequency wherethe distortion is within the measurement capability of the test equipment. Measurements for this data sheet weremade with an Audio Precision System Two distortion/noise analyzer, which greatly simplifies such repetitivemeasurements. The measurement technique can, however, be performed with manual distortion measurementinstruments.

8.2.3 Application Curves

Figure 44. THD+N Ratio vs Output Voltage AmplitudeFigure 43. THD+N Ratio vs Frequency




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Tota

lH

arm

onic

Dis

tort

ion

+N

ois

e(%

)

10

Frequency (Hz)

100k100 1k 10k

Tota

lH

arm

onic

Dis

tortio

n +

Nois

e (d

B)

0.001

0.0001

0.00001

-100

-120

-140

Measurement BW > 500kHz

G = 1

G = 11

G = 1

R = 600L W

R = 600L W

R = 5kL W

V = ±15VS

V = 3.5VIN RMS


Typical Application (continued)

Figure 45. THD+N Ratio vs Frequency




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9 Power Supply Recommendations

9.1 Operating VoltageOPA2211-EP series operational amplifiers operate from ±2.25-V to ±18-V supplies while maintaining excellentperformance. The OPA2211-EP series can operate with as little as +4.5 V between the supplies and with up to+36 V between the supplies. However, some applications do not require equal positive and negative outputvoltage swing. With the OPA2211-EP series, power-supply voltages do not need to be equal. For example, thepositive supply could be set to +25 V with the negative supply at –5 V or vice-versa.

The common-mode voltage must be maintained within the specified range. In addition, key parameters areassured over the specified temperature range, TA = –55°C to 125°C. Parameters that vary significantly withoperating voltage or temperature are shown in Typical Characteristics.

10 Layout

10.1 Layout GuidelinesFor best operational performance of the device, use good PCB layout practices, including:• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.

Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local tothe analog circuitry.– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effectivemethods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digitaland analog grounds paying attention to the flow of the ground current. For more detailed information refer toCircuit Board Layout Techniques, SLOA089.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces aspossible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better asopposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. As shown in Figure 46, keeping RF andRG close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakage currents from nearby traces that are at different potentials.

• Cleaning the PCB following board assembly is recommended for best performance.• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly toremove moisture introduced into the device packaging during the cleaning process. A low temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.




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Place components close to device and to each other to reduce parasitic errors

GND

GND

VIN

VOUT

VS+

GND VS±

Run the input traces as far away from the supply lines as possible

V+

OUT B

±IN B

+IN B

OUT A

±IN A

+IN A

V±

Use low-ESR, ceramic bypass capacitor

Ground (GND) plane on another layer(or GND for single supply) Only needed for dual-supply operation

RF

RG

RIN

+

±

VOUTRG

RINVIN

(Schematic Representation)

RF


10.2 Layout Example

Figure 46. Operational Amplifier Board Layout for Noninverting Configuration

10.3 Thermal ConsiderationsThe primary issue with all semiconductor devices is junction temperature (TJ). The most obvious consideration isassuring that TJ never exceeds the absolute maximum rating specified for the device. However, addressingdevice thermal dissipation has benefits beyond protecting the device from damage. Even modest increases injunction temperature can decrease operational amplifier performance, and temperature-related errors canaccumulate. Understanding the power generated by the device within the specific application and assessing thethermal effects on the error tolerance lead to a better understanding of system performance and thermaldissipation needs.




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11 Device and Documentation Support

11.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.2 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

OPA2211MDRGTEP ACTIVE SON DRG 8 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OCQM

V62/15606-01XE ACTIVE SON DRG 8 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OCQM

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2211-EP :

NOTE: Qualified Version Definitions:

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA2211MDRGTEP SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA2211MDRGTEP SON DRG 8 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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