Online Closed-Loop Autotuning Digital Controller for Switching Power Converters

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013 1747

Online Closed-Loop Autotuning Digital Controllerfor Switching Power Converters

Jaber A. Abu Qahouq, Senior Member, IEEE, and VaraPrasad Arikatla, Student Member, IEEE

Abstract—A switching power-converter closed-loop online au-totuning controller is presented in this paper. The presentedcontroller is based on tuning the closed-loop-compensator pa-rameters by simply observing the compensated-error-signaltime-domain characteristics. Moreover, the presented online au-totuning controller does not require the knowledge of the power-stage frequency response, does not depend on any conventionalrule-of-thumb control-design criteria such as gain and phase mar-gins, can be used without interrupting the normal operation of thepower converter, and is relatively simple when compared to othermethods particularly those that require measuring the frequencyresponse of the power stage or closed-loop converter system. Theonline autotuning controller is presented in this paper based ona dc–dc buck switching converter with a fully digital closed-loopcontroller, as an example and not for limitation.

Index Terms—Autotuning, compensator, controller, dc–dc,digital, error, power converter, stability, tuning.

I. INTRODUCTION

THE design and tuning of the closed-loop feedback controlof power converters for stable operation with high dy-

namic performance over variable and wide operating conditionsare critical in many applications [1]–[6]. In the design process,the power-stage transfer function and design parameters areused to design the closed-loop compensator [6]–[11]. Theinaccuracy in the knowledge of the power-stage componentvalues and their parasitic values in addition to the approxima-tion used in the transfer functions affects the design accuracyand performance of the designed compensator. The additionalsources of inaccuracy include the delay of the switches’ drivers,the digital logic component delays, and the analog-to-digitalconverter (ADC) delays when a digital controller is used.

The control loop design is usually based on conventionalmethods with the rule-of-thumb design guidelines such asgain and phase margins with Bode plots and/or root-locuspole–zero locating [9]–[12]. The drawbacks of using thesemethods include one or more of the following: 1) they requirethe knowledge of the power-stage transfer function (frequency

Manuscript received July 4, 2011; revised October 31, 2011 and January 1,2012; accepted February 25, 2012. Date of publication March 8, 2012; dateof current version January 30, 2013. This work was supported by the NationalScience Foundation of the United States under Grant 0927104.

Any opinions, findings, and conclusions or recommendations expressed inthis material are those of the author(s) and do not necessarily reflect the viewsof the National Science Foundation.

The authors are with The University of Alabama, Tuscaloosa, AL35487 USA (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2012.2190373

response); 2) their results are sensitive to design approxi-mations and power-stage components’ parasitic values; and3) the theoretical design is usually not sufficient, and additionaladjustment or tuning is usually required for the implementedhardware. All these make the design of a high-performanceclosed-loop compensator a noneasy task and require a tediousmanual tuning in the theoretical design and in the experimentalhardware.

The advantages of digital controllers in power-converter ap-plications have made them stronger competitors and alternativeto their analog counterpart in several applications [12]–[23].These advantages include the digital controllers’ ability andeasiness to implement sophisticated algorithms and laws toimprove the dynamic and efficiency performances of powerconverters, their easiness to be reconfigured and scaled com-pared to their analog counterpart, and their ability to potentiallyreduce or eliminate the controller-component variations andsensitivity that affect the controller performance [12]–[20].On the other hand, the limited resolution, the size, cost, andpower consumption incurred from the required high-speedhigh-resolution ADCs and digital pulsewidth modulators areamong the challenges in designing and utilizing digital con-trollers in power-converter applications.

In order to alleviate the challenges and difficulties in theclosed-loop-compensator design discussed earlier, researchershave utilized digital controllers’ ability to autotune and/orcalibrate the compensator [20]–[30]. In [7]–[9], [11], [26],and [31] autotuning controller schemes, the closed loop isperturbed using a test signal, and the response to that signalis obtained to find the frequency characteristics of the loop.The phase margin and gain margin are obtained, and thenecessary adjustment of compensator parameters is made toattain the desired phase margin and gain margin. In [24] and[29], an autotuning controller scheme based on model referenceimpulse response is presented. This autotuning controller com-pares the measured system response with a reference systemresponse and adjusts a compensator parameter accordingly tominimize the error function. In [25], an autotuning controllerbased on the relay feedback method is presented. It tunesthe proportional–integral–derivative (PID) parameters of thecompensator based on a desired phase margin and controlloop bandwidth. In [28], a self-tuning analog current-modecontroller is presented. The presented method is based on theinsertion of nonlinear blocks in the control loop and mea-surement of the closed-loop properties such as gain margin,phase margin, and crossover frequency by perturbing the outputvoltage. The controller is then tuned according to the desired setof specifications.

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1748 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

Fig. 1. Block diagram of a power-converter system with closed-loop control.

The power-converter closed-loop autotuning schemes dis-cussed in the literature, such as the examples discussed earlier,usually have one or more of the following characteristics:1) they are relatively complicated and require adding significanthardware; 2) they require breaking the control loop, interruptingthe power-converter-system operation and/or injecting signal(disturbance) that affects the output-voltage regulation; and3) their operation is based on conventional design methods andthe associated rule-of-thumb design criteria.

This paper presents an online closed-loop compensator au-totuning digital power controller that is relatively simple, doesnot require the knowledge and/or measurement of the power-stage or closed-loop frequency response, and does not dependon conventional design methods and the associated rule-of-thumb design criteria. The presented concept and controller isfor autotuning the compensator of the closed-loop pulsewidthmodulation (PWM) controller at a given set of parameters andswitching frequency value.

The next section discusses the bases for the proposed conceptof the autotuning digital controller (ATerror controller), whichis called compensated-error observe and modulate method(CEO&M method). Section III presents the ATerror-controllerdigital implementation algorithm and architecture. The proof-of-concept experimental prototype results are presented inSection IV, and the conclusion is given in Section V.

II. BASES OF THE PROPOSED ONLINE

AUTOTUNING CONTROLLER

The proposed online autotuning controller is based onobserving the compensated-error-signal time-domain charac-teristics, which is readily available in any compensated closed-loop feedback controller. This method is referred to as CEO&Mmethod.

Fig. 1 shows a block diagram of a power-converter sys-tem with voltage-mode closed-loop feedback control. Transfer-function notation for each part of the system is indicated on thefigure. The difference between the reference voltage and theoutput voltage (the uncompensated error) is applied to a com-pensator, such as PID compensator, to result in a compensatederror signal (Ve−comp). Ve−comp has a dc component and anac component and is used to generate the controller duty cycleusing a pulsewidth modulator.

The CEO&M will first be introduced using the simulationresults of a design example. The design example is a dc–dcbuck-converter closed-loop system with a three-pole two-zerocompensator (one pole is at zero), 12-V input voltage, 1.5-Voutput voltage, 0.1-μH output inductor, 350-μF output capac-

Fig. 2. Bode plots for (a) different gain (K) values and (b) different pole (P1)locations.

itor, and 1-MHz switching frequency (fsw). Fig. 2 shows thesystem Bode plots [for Gp(s) × Gc(s) × GM (s)] for differentgain (K) values and different pole (P1) locations (one polelocation is varied).

The power-converter system is simulated using Matlab/Simulink software package. The simulation results are shown inFigs. 3 and 4 that correspond to Fig. 2(a) and (b), respectively.Figs. 2(a) and 3 show that as the compensator gain K increases,which corresponds to an increase in bandwidth and systemspeed, the peak-to-peak value of the compensated error signal(Ve−pp) increases and the dynamic performance is improved(smaller output-voltage dynamic deviation and shorter settlingtime). This occurs up to a point where the system becomesunstable and the frequency of Ve−comp (fV e−comp) becomeslower than the switching frequency. Similarly, Figs. 2(b) and 4show the same behavior as the pole location P1 is moved in adirection that results in increasing the system bandwidth andimproving the system dynamic performance.

Therefore, the following conclusion can be drawn from theprevious discussion: A closed-loop controller’s compensator

ABU QAHOUQ AND ARIKATLA: ONLINE CLOSED-LOOP AUTOTUNING DIGITAL CONTROLLER FOR SWITCHING POWER CONVERTERS 1749

Fig. 3. Simulation results of a dc–dc buck converter to demonstrate the basisof the proposed CEO&M control concept based on several K values (Note thatVe−conv. = Ve−comp): (a) During steady state and (b) during step-up loadtransient.

can be tuned or optimized by perturbing one or moreof the compensator-parameter values such as gain, poles,and/or zeros in a direction that will increase Ve−pp as longas fV e−comp = fsw (given a switching frequency value duringthe tuning process) or until a maximum possible Ve−ppvalue isobtained whilefV e−comp = fsw is still maintained.

The theoretical verification to the fact that Ve−pp is largerfor closed loop with higher bandwidth is relatively simple. Forsimplicity, assume that the compensator is a simple low-passfilter with a gain (K) and a cutoff frequency ωc as follows:

Gc(s) =K

1 +(

sωc

) ⇒ Ve−comp(s) ∝ Gc(s)

⇒ Ve−comp(s) ∝ K

1 +(

sωc

) . (1)

Equation (1) indicates that the magnitude ofVe−comp(s) (|Ve−comp(s)|) increases as K (the gain) increasesand as ωc (the pole) increases, which indicates a faster system.A similar behavior is expected with a higher order low-passfilter type (several poles in addition to several zeros).

As shown in Fig. 5, as the bandwidth is increased (by theincrease of gain), Ve−pp becomes larger up to a point wherethe closed-loop system becomes unstable and the frequencyof Ve−comp (fV e−comp) becomes lower and not equal to thedigital-ramp switching frequency. This will cause the PWM

Fig. 4. Simulation results of a dc–dc buck converter to demonstrate the basisof the CEO&M control concept (Note that Ve−conv. = Ve−comp) based onseveral pole locations (one pole is moved): (a) During steady state, (b) duringstep-up load transient, and (c) during step-down load transient.

Fig. 5. Illustration of the compensated-error-signal behavior under differentbandwidth values.

output to have a frequency that is lower than the switching fre-quency (or the ramp signal frequency). This point will likely tooccur as the bandwidth becomes closer to half of the switchingfrequency [31]–[35].


Fig. 6. Illustration of the compensated-error-signal behavior under differentbandwidth values with digital compensator.

It is to be noted here that even though the previous discussionand example is based on compensator transfer functions inanalog domain, it should be obvious that the same argumentis valid when a digital compensator implementation is used. Anexample digital equivalent to Fig. 5 is shown in Fig. 6. Fig. 6shows a digital ramp and digitally compensated error signalassuming multisampling operation per switching cycle (multi-ple ADC samples used for multiple calculations per switchingcycle) [36]. In conventional digital controller, the duty-cyclecommand can be calculated either once (single sample) eachswitching cycle or multiple times (multisampling rate) [36] inorder to generate a compensated error signal.

Fig. 7 shows a dc–dc buck converter with digital closed-loopcompensator and a proposed autotuning controller (ATerror)block diagram. Based on the previous discussion, by observingVe−pp and fV e−comp, the closed-loop-compensator parameterscan be tuned to achieve a closed-loop converter system withbetter dynamic performance by tuning one or more of thecompensator parameters to a more near-to-optimum value fora given power-converter design. This is discussed further in thenext section.

III. ONLINE ATERROR CONTROLLER ALGORITHM

AND ARCHITECTURE

As shown in Fig. 7, the main input to the ATerror controlleris Ve−comp. The only other input is the switching frequency(fsw) which is the digital pulsewidth modulation (DPWM)frequency in order to synchronize the operation of the ATerrorcontroller when its Ve−pp and fV e−comp are measured. Thesetwo inputs are readily available in the controller, and therefore,no additional voltage or current sensors are needed.

Fig. 8 shows a general implementation flowchart of theATerror controller. The controller finds Ve−pp value severaltimes over “H” switching cycles in order to confirm steady-state operation and the accuracy of Ve−pp. Since autotuningis performed during a steady-state operation, it is necessary toconfirm the steady-state operation of the power stage.

Fig. 7. DC–DC buck converter with digital closed-loop compensator andATerror controller.

If the Ve−pp value is stable over the “H” switching cycles(note that one Ve−pp value is recorded in the digital con-troller every switching cycle), the controller will adjust theclosed-loop-compensator parameter(s) (such as gain, pole, orzero) in a direction that will increase or decrease the Ve−pp

value (which results in the increase or decrease in the closed-loop bandwidth) after confirming the fV e−comp = fsw con-dition. Note that fV e−comp = fsw condition can be verified,for example, every switching cycle by measuring the timebetween two compensated-error-signal peaks in two or moreconsecutive switching cycles (this will be detailed in the nextsection). The fV e−comp = fsw condition is considered satis-fied if the consecutive peak values of Ve−pp are equal orwithin a specified error range (to account for digital resolutionerrors). The increase/decrease decision of the compensatorparameter being tuned is based on the comparison betweenthe new value of Ve−pp [Ve−pp(r)] and the previous value ofVe−pp [Ve−pp(r − 1)]. If Ve−pp(r) > Ve−pp(r − 1) is satisfied,the ATerror controller will adjust the closed-loop-compensatorparameter(s) in a direction that will increase the Ve−pp (andhence, the closed-loop bandwidth). Taking the compensatorgain (K) as an example here, K value is increased. The ATerrorcontroller will then wait “Y” switching cycles to ensure newsteady-state operation before repeating the process again. IfVe−pp(r) < Ve−pp(r − 1) is not satisfied, the ATerror con-troller will repeat the process starting from recording Ve−pp

again.If the value of Ve−pp is not the same or not stable over the

“H” switching cycles, the controller will check if this condi-tion is because fV e−comp �= fsw. If it is the case, the ATerrorcontroller will vary the appropriate parameter (in this example,reduce K) in a direction that will reduce Ve−pp (and hence, theclosed-loop bandwidth) until the condition fV e−comp = fsw issatisfied and then stops its operation for “Z” switching cyclesassuming that a more near-to-optimum value for the parameter(K value, in this example) has been reached before startingthe new autotuning process again (the new autotuning and cal-ibration cycles). The new autotuning process can be performedperiodically or when a change is detected that requires a newautotuning operation.


Fig. 8. General main implementation flowchart of the ATerror controller.

It should be noted that there may be several possible ATerrorcontroller algorithms/implementations based on the CEO&Mconcept and one of them is described in the next section.Moreover, more specific implementation details for the partsof Fig. 8 controller flowchart are shown in Figs. 12 and 13.

IV. PROOF-OF-CONCEPT EXPERIMENTAL

PROTOTYPE RESULTS

This section is divided into two parts. In the first part, anexperimental verification for the CEO&M concept is presented,and in the second part, the experimental results of the ATerrorcontroller (which is based on the CEO&M concept) are pre-sented and discussed.

A proof-of-concept experimental prototype is built in thelaboratory in order to verify the proposed concept and con-troller. Fig. 9 shows the block diagram of the experimentalsetup. The prototype is a single-phase buck converter with anominal input voltage of 9 V, a nominal output voltage of1.5 V, an output inductor of 440 nH, an output capacitanceof 2.8 mF, a switching frequency of 342 kHz, and a full-loadcurrent of 8 A.

Fully digital control hardware is used to implement theclosed-loop voltage-mode feedback compensator and theATerror controller. The output-voltage ADC has 8-b reso-lution and takes 2.8 million samples/s. However, only fourADC samples are utilized to obtain (calculate) four values

Fig. 9. Block diagram of experimental prototype setup.

of Ve−comp, and the duty ratio update is sent to the DPWMonce each switching cycle. The DPWM used is with 10-bresolution. The digital controller is implemented using Alterafield-programmable gate array (FPGA) “Altera Cyclone IIEP2C35F672C6.” A digital-to-analog converter (DAC) is usedto convert the digital value of Ve−comp to an analog output thatcan be viewed on the oscilloscope for testing purposes (thisDAC is not required for the controller operation). As shown


Fig. 10. Digital compensator used in the proof-of-concept experimentalprototype.

in Fig. 9, input/output pins are used to transmit the informationback and forth between the hardware setup parts (power stage,ADC, FPGA, and DAC).

The ATerror controller operation and performance improveas the number of samples in the compensator-error calculationsis increased. This is because with a higher number of samples,the compensated-error-signal peak-to-peak value and frequencycan be determined more accurately (becomes closer to an ana-log compensated error signal). A single sample is not sufficientfor the ATerror controller operation since peak-to-peak valueand frequency cannot be determined.

The digital compensator architecture used is as shown inFig. 10, where Kp = 1.39, Ki = 0.0195, Kd = 0.008, and KT

is the gain which is varied for optimization by the ATerrorcontroller.

A. Experimental Verification of the AutotuningController Bases

The gain of the compensator (KT ) is varied in order toinvestigate the effect on Ve−comp. Fig. 11 shows the experi-mental results of the output voltage and Ve−comp with an inputvoltage of 9 V under three different example values of KT asindicated in Fig. 11 title. Obviously, the three different gainvalues correspond to three different bandwidth values. Thelower gain value results in a lower bandwidth, the mediumgain value results in a medium bandwidth, and the higher gainvalue results in a higher bandwidth that causes the system tostart becoming unstable as shown in the figure. It could beobserved from Fig. 11 results that as the gain is increased(and hence, bandwidth is increased), Ve−pp is increased and thedynamic output-voltage deviation and settling time are reduced,up to a KT value that makes the system unstable. It can alsobe observed from Fig. 11(e) that in this unstable case, thefrequency of the compensated error signal is not equal to theswitching frequency (fV e−comp �= fsw).

These results agree with the theoretical assumptions of theCEO&M concept presented earlier. The authors have alsoverified the same behavior using other several commerciallyavailable power-converter prototypes with analog controllers.These results show that the CEO&M concept is valid and canbe utilized for the autotuning of the compensator’s parameters.

B. Experimental Operation and Results of the OnlineAutotuning Controller

The ATerror controller is used to autotune the gain KT ofthe compensator as an example parameter. A general imple-

Fig. 11. Experimental results of a dc–dc buck converter to demonstrate thebasis of the proposed CEO&M control concept when varying gains. (a) and(b) Lower gain (KT = 0.344). (c) and (d) Medium gain (KT = 1.593).(e) and (f) Higher (unstable) gain (KT = 2.531). (a), (c), and (e) DuringSteady-State Operation. (b), (d), and (f) Under 8–0–8 A Load Current Transient.

mentation flowchart of the ATerror controller is discussed inthe previous section (Fig. 8). More ATerror-controller opera-tion details are given in this section. At the beginning of theautotuning cycle, the ATerror controller adjusts the gain ofthe compensator and identifies the direction of gain change(increase or decrease) that results in the increase in Ve−pp whilemaintaining fV e−comp = fsw, as shown in Fig. 12 flowchart.

The ATerror controller first decrements (increments) the gainof the compensator (as shown in Mode A1 of Fig. 14, fordecrementing the gain KT ) and compares the Ve−pp underthe current gain value [Ve−pp(r)] with the Ve−pp under theprevious gain value [Ve−pp(r − 1)]. If there is an increase inVe−pp [Ve−pp(r) > Ve−pp(r − 1)], the controller identifies thisdecrement (increment) direction of gain as the correct directionto adjust the gain to increase Ve−pp. Otherwise, the increment(decrement) direction of gain is identified by the controller asthe correct direction to adjust the gain to increase Ve−pp. Thisprocess of the decrement (increment) of gain occurs for “S”steps. After the end of “S” steps, the gain is once again incre-mented (decremented) until it reaches the initial gain (whichtakes S − 1 steps), when the process of gain change started (asshown in Mode A2 of Fig. 14, for incrementing the gain KT ).

The duration of the direction detection process is determinedby “S.” The ATerror controller initializes the detection process


Fig. 12. Flowchart for the detection of the direction of gain change (increase/decrease).

Fig. 13. Flowchart for the detection of frequency change and the setting of gain.

by setting “Detection=1” and initializing “DC Counter=1”as shown in Fig. 12. The variable “Sign” is set to be equalto “zero,” the gain KT is decremented, and the correspondingchange in Ve−pp is observed. If Ve−pp is increased [Ve−pp(r) >Ve−pp(r − 1)], then the variable “Direction” is set to “zero”through the variable “Sign.” Otherwise, “Direction” is setto “one” by taking the complement of “Sign.” At the endof the operation cycle of setting the “Direction” value,“DC Counter” is incremented. This process repeats untilthe “DC Counter” value is greater than “S” (as shown inMode A1 of Fig. 14). When “DC Counter” is greater than“S,” the gain KT is incremented, and the change in Ve−pp isobserved (as shown in Fig. 12 and illustrated in Mode A2 ofFig. 14). Based on the change in Ve−pp, the “Direction” isset through the variable “Sign” as described earlier. When the

“DC Counter” value is equal to twice the “S,” the gain changedirection is set in “Direction” (zero or one), and the value of“Detection” is set to “zero” to indicate that the gain-direction-detection process is completed. The value of “Direction” is setto “one” if an increase in the gain (or any other variable to betuned such as a zero or a pole) increases Ve−pp. Otherwise, it isset to “zero.”

Once the correct/required direction of gain change to in-crease Ve−pp is identified, the ATerror controller adjusts thegain in that direction and observes Ve−comp for any instabilityas shown in Fig. 8 flowchart, or in other words, it watches forthe condition when fV e−comp �= fsw. The controller flowchartfor the detection of the condition fV e−comp �= fsw is shown inFig. 13. In this experiment, instead of measuring fV e−comp inorder to compare it with fsw, the condition fV e−comp �= fsw


Fig. 14. Illustration of the controller operation under autotuning to determinethe variable (the gain here) required-direction change and the detection offrequency change condition.

is detected/identified by observing the difference between theconsecutive Ve−pp values over several switching cycles, forsimplicity. If this difference is above a preferment value, thecontroller determines that fV e−comp �= fsw. In other words,fV e−comp �= fsw is identified (indicating an unstable outputvoltage) if the deviation between two consecutive values ofVe−pp (|Ve−pp(r) − Ve−pp(r − 1)|) is greater than an upperlimit value (HL). The gain is first adjusted in the directionidentified earlier until the deviation between the two consecu-tive cycles is greater than HL (|Ve−pp(r) − Ve−pp(r − 1)| >HL). Mode B in Fig. 14 shows the increase of gain until|Ve−pp(r) − Ve−pp(r − 1)| > HL is satisfied. Once this condi-tion is detected, the controller starts adjusting the gain value inthe opposite direction that decreases Ve−pp (as shown in ModeC of Fig. 14) until the difference (|Ve−pp(r) − Ve−pp(r − 1)|)is less than a lower limit (LL), which is considered a stablecondition. The number of steps the ATerror controller takesto reach the optimum value after the detection of |Ve−pp(r) −Ve−pp(r − 1)| > HL condition depends on the difference be-tween HL and LL (HL − LL) and the gain step size. At thisstable condition, the controller sets the gain value and waitsfor a predetermined amount of time (Z switching cycles), or achange in Ve−pp is detected, before another autotuning processis initiated.

As shown in Fig. 13, at the beginning of the frequency-change-detection process, the variable “Flag” is set to be equalto “one,” which indicates that fV e−comp = fsw. Depending onthe value of “Direction,” the gain KT is incremented or decre-mented. When “Direction = 0 (Direction = 1),” the gainKT is incremented (decremented) until the deviation betweenthe values of Ve−pp (|Ve−pp(r) − Ve−pp(r − 1)|) is larger thanHL (as shown in Mode B of Fig. 14). When the deviationin Ve−pp exceeds HL, “Flag” is set to “zero” indicating thefrequency change condition (fV e−comp �= fsw). The gain isthen decremented (incremented) until it reaches the value wherethe deviation between Ve−pp values is less than LL (as shownin Mode C of Fig. 14).

Since the ADC has a finite number of bits (N) which resultsin a resolution of Res = ΔV/2N , which means ∼8 mV for8-b ADC with ΔV = 2 V (ADC voltage range) in this paperexperimental prototype, the error signal can vary by 8 mVduring normal operation with fixed compensator gain and noautotuning operation. Therefore, the LL value needs to beselected such that it is larger than 8 mV so that the ATerror

controller is able to correctly identify that the change in theerror-signal peak-to-peak value is due to the gain change andnot because of the finite ADC resolution. Therefore, LL shouldbe selected with at least 1-b-less resolution than the ADC whichresults in 16 mV for LL value.

Once the compensated-error-signal peak-to-peak value isequal to or larger than LL, the ATerror controller determinesthat the frequency of the compensated error signal might havechanged due to reaching a gain value that results in unstablesystem. However, another limit, which is HL limit, is used toconfirm that the unstable condition is because of the gain valueand not because of any quantization error in the calculationsof the compensated error signal, which is equal to Res/2 =4 mV. Therefore, HL = LL + Res/2 = 20 mV is selected.HL limit can also serve as an additional confirmation step forthe instability condition occurrence. The designer can chooseHL with a higher value, but the drawback is that this will causethe ATerror controller to take the power-converter system to acondition with larger oscillations before it brings it back to theoptimum stable condition.

The perturbation step size of the gain affects the ATerroroperation as follows: It is desired to have a small step size(limited by the hardware capability) so that the optimum gainvalue is detected more accurately; however, a smaller step sizewill result in a longer autotuning cycle. Therefore, the designershould select a gain perturbation step size while considering thetradeoff between accuracy and speed and the digital hardwarerequirements. In the experimental prototype of this paper, theexample step size used to obtain the results is 1/32.

The gain starting point can be selected when initially design-ing the compensator using conventional design techniques. Inthis initial design, the gain value is usually selected to be aconservative value such that the system is stable under a widerange of operation parameters. In the experimental work of thispaper, the starting gain value is selected to be far from theoptimum gain value in order to demonstrate that the ATerrorcontroller is able to converge to the optimum gain value whenstarting from a far starting gain value. However, in general, thestarting gain value can be any value, and the ATerror controllerwill autotune the gain during the first autotuning cycle when thepower-converter system is initially powered up. After this,the ATerror controller will start the autotuning process fromthe gain value of the previous operating condition in order todetect the new gain value under the new operating condition(for example, when the input voltage changes, see Fig. 17). Theproposed concept is able to tune the closed loop for a givenset of design parameters such as input voltage, output voltage,switching frequency, power inductor value, capacitor value, andcomponent parasitic values. If any of these parameters changes,the proposed controller will go through another autotuningcycle and adjust the compensator accordingly. However, theparameter-value change rate should not be faster than the auto-tuning operation in order for the autotuning controller to be ableto complete the tuning operation. If a parameter changes duringthe autotuning process, the autotuning controller will continueits autotuning process based on the new parameter value.

Fig. 15 shows the experimental waveforms of the proto-type during autotuning operation at an input voltage of 9 V.


Fig. 15. Experimental waveforms of the prototype with the ATerror controllerfor an input voltage of 9 V. (a) Variation of gain until new optimized gain valueis achieved. (b) Periodic tuning operation of the ATerror controller.

Fig. 15(a) shows an autotuning cycle starting from an initialgain value until the ATerror controller converges to new gainvalue, for demonstration purposes. As can be observed fromFig. 15(a), the ATerror controller initially identifies the correctdirection of the gain change, followed by adjusting the gain andthe detection and confirmation of the frequency condition (asdescribed earlier) before setting the new optimized gain value.Fig. 15(b) shows the periodic reautotuning operation of thecontroller (the optimized gain value stays the same since it isfor the same converter design and operating conditions).

Fig. 16 shows the transient-response comparison before auto-tuning and after autotuning of the power-converter closed-loopsystem. Fig. 16(a) shows the power-converter output-voltageresponse due to a step-down load transient of 8–0 A beforeautotuning with a gain value that is equal to the initial gain valueused to obtain Fig. 15(a) before the start of the autotuning cycle.Fig. 16(b) shows the power-converter output-voltage responsedue to a step-down load transient of 8–0 A after autotuning witha gain value that is equal to the optimum gain value after theautotuning cycle obtained in Fig. 15(a) and (b).

While the ATerror controller periodically autotunes the com-pensator, it is also able to detect the steady-state variationsin the compensated error signal (if, for example, the inputvoltage changed) and initiate an autotuning cycle. Fig. 17 showsthe autotuning experimental results when the input voltagechanges between different values during the power-converteroperation. It can be observed that the optimum compensatorgain is decreased when the input voltage is increased, which isexpected.

Fig. 16. Dynamic response of the power converter during a load transient of8–0 A (a) before autotuning and (b) after autotuning.

Fig. 17. Experimental waveforms of the autotuning process under (line) input-voltage variations (a) 9–10 V, (b) 9–11 V, and (c) 11–9 V.

ATerror controller can autotune the gain starting from a stableor unstable closed-loop power-converter system. If the power-converter closed-loop system is initially unstable, the ATerrorcontroller will determine that the compensated-error-signal fre-quency is not equal to the power-stage switching frequency andwill decrease the gain value. Fig. 17(a) and (b) shows how the


Fig. 18. Experimental waveforms for the autotuning process with a smalleroutput-capacitor value of 340 μF (with 9-V input voltage).

Fig. 19. Dynamic response of the power converter during a load transient of8–0 A with 340-μF output capacitance: (a) Before autotuning and (b) afterautotuning.

Fig. 20. Experimental waveforms for the autotuning process with a smalleroutput-capacitor value of 1160 μF (with 9-V input voltage).

ATerror controller performed the autotuning from an unstablecondition (with higher gain value) and converged to a stablecondition (with lower gain value).

In order to test the operation of the ATerror controllerfor different power-stage output-capacitor values, the output-capacitor value is reduced from 2.8 mF to 340 μF. Figs. 18and 19 show the experimental results with the 340 μF whichdemonstrate the ability of the ATerror controller to perform au-totuning with different output-capacitor values. Figs. 20 and 21show the results when the output-capacitor value is 1160 μF.

As can be observed from the experimental results and theoperation description of the autotuning controller, once thecompensated-error-signal Ve−pp value starts to change fromone switching cycle to another, the autotuning controller re-

Fig. 21. Dynamic response of the power converter during a load transient of8–0 A with 1160-μF output capacitance: (a) Before autotuning and (b) afterautotuning.

duces the value of KT . At the condition when the value ofVe−pp starts to change from one switching cycle to another, avery small and minor instability could be observed, if any, at theoutput voltage, and such small instability is acceptable and iskept within the desired regulation limits of the power converter.The amount of how much instability KT can cause in the outputis controlled by adjusting HL and LL values.

After the initial closed-loop compensator autotuning process,the time the autotuning process takes mainly depends on thechange in one of the design parameters of the power converterin addition to the perturbation step size of the parameter beingtuned. This is true for the proposed concept as well as forthe other autotuning concepts presented in the literature. Inthis paper experiment, it can be observed from Fig. 17 thatwhen the input voltages changed from 9 to 10 V, for example,the autotuning process took about six autotuning cycles. Theinitial autotuning process took a longer time when the valueof the parameter being autotuned is initialized to be far fromthe optimum value when the power converter is powered up,which was done for demonstration purposes (to demonstratethat the proposed controller is able to converge starting froma far starting point). Changes in the component values or theirparasitic values as a result of aging or temperature variationoccur very slowly over time, and therefore, it is expected thatthe autotuning process will not need more than few cycles eachtime such changes are large enough to require a compensator-parameter adjustment (this autotuning process happens slowlyover time). Large variation in one of the power-converter pa-rameters, such as output capacitance or a desired change inthe switching frequency, which usually occurs by a changein the design as desired by the designer, might take manycycles, 30 cycles, for example, in this paper experiment, butonce the compensator is autotuned, the compensator parameterwill always be close to any new optimum value that is neededwhen a slow or small variation occurs naturally. It should benoted that the values of HL and LL might add few additionaltuning cycles to the process; however, these additional cycleswill occur when the compensator parameter is already aroundthe optimum value.

V. CONCLUSION

This paper has presented a method to tune the power-converter closed-loop-compensator parameters for improveddynamic performance. The CEO&M concept observes the


time-domain characteristics of the compensated error signal(Ve−comp), namely, the peak-to-peak value (Ve−pp) and fre-quency (fV e−comp) to tune the compensator. The presentedmethod does not require the knowledge of the power-stagefrequency response, does not depend on any conventionalrule-of-thumb control-design criteria such as gain and phasemargins, and is dependent only on the time-domain parametersof the compensated error signal.

The presented CEO&M concept is utilized to implementan online closed-loop compensator ATerror controller. Thepresented CEO&M concept can be used in a wide varietyof applications that requires switching power converters withPWM control and closed-loop compensator such as space appli-cations, electric vehicles, computing platforms, communicationplatforms, and for on-chip integrated power converters. Thepresented ATerror controller based on the CEO&M conceptis particularly advantageous in cases or applications wherethe power-converter design parameters or component values orparasitics might change over time, for example, as a result ofaging, temperature, or surrounding design parameters in thesame system. One scenario example is that if the equivalentoutput capacitance of the power converter is changed as a resultof replacing a component in the system that utilizes the powerconverter, the presented ATerror controller is able to autotunethe closed-loop compensator. Another scenario example is thatif a power-converter module is designed for given initial designparameters, once it is placed in a system (such as comput-ing platform or vehicle), the presented ATerror controller isable to autotune the closed-loop compensator based on thesurrounding component values in the system to yield stableand better dynamic performance. A third scenario example isthat if a power converter with a given design is available andthe designer desires to reduce the output inductor to improvethe dynamic performance or increase the output inductanceto improve efficiency, the presented ATerror controller is ableto autotune the closed-loop compensator for the designer. TheCEO&M concept can also be utilized as guidance to manuallydesign a closed-loop compensator for a power converter byobserving the characteristic changes of the compensated errorsignal while adjusting the compensator parameters in an exper-imental prototype or a simulation model.

The digital implementation algorithm, architecture, and aproof-of-concept experimental prototype results are presentedfor the ATerror controller. While in this paper experiment, thecompensator gain is autotuned, the method could also be usedto autotune other parameters of the compensator such as poleand zero locations, which is a future work.

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Jaber A. Abu Qahouq (SM’07) received the B.Sc.degree (with first-class honors) in electronics engi-neering from Princess Sumaya University for Tech-nology, Royal Scientific Society (RSS), Amman,Jordan, in 1998 and the M.S. and Ph.D. degrees inelectrical engineering from the University of Cen-tral Florida (UCF), Orlando, in 2000 and 2003,respectively.

From 1998 to 1999, he was with RSS, ElectronicServices and Training Center, Amman. From 1999to 2003, he was a Research Assistant/Associate with

Florida Power Electronics Center, UCF. From January 2002 to December 2003,he was an Adjunct Faculty with UCF, where he was a Visiting Assistant Pro-fessor and Instructor with the School of Electrical Engineering and ComputerScience from January 2004 to August 2005. From August 2005 to January2008, he was with Intel Corporation. He is currently an Assistant Professorwith the Department of Electrical and Computer Engineering, The Universityof Alabama, Tuscaloosa. He led and worked on several projects funded byNational Science Foundation, United States Department of Agriculture, ArmyResearch Laboratory, National Aeronautics and Space Administration, AstecPower/Emerson, Intel, the UCF, and The University of Alabama. His researchinterests include high-frequency high-density low-voltage high-current fast-transient dc–dc converters, soft-switching power conversion, digital controlin power electronics, adaptive power control, platform power delivery distri-bution architectures and related power-management schemes, power-factor-correction ac–dc converters, dc–ac inverters, renewable energy systems, powerdevices, nanotechnology-based electronic devices, and unmanned aerial vehi-cles, among others.

Dr. Abu Qahouq is actively serving as a Reviewer to several journal and con-ference publications including IEEE transactions and conferences. He chairedseveral conference sessions over the years. He served as a technical programcommittee member of the IEEE PESC 2007 conference, as a review com-mittee member of the IEEE ISCAS 2008 conference, as a technical programcommittee member of the IEEE ICECS 2009, 2010, and 2011 conferences,as a technical program committee member of the IEEE ECCE 2010, 2011, and2012 conferences, and as a member of Intel’s mobile-platform patent committee(when he was with Intel Corporation), among others. He was the recipient ofthe Division Recognition Award from the Systems Technology Lab, CorporateTechnology Group, Intel Corporation, in 2006, the IET Premium Award forBest Paper in 2009, the IEEE Outstanding Graduate Student Award in 2002,and the King of Jordan Royal Watch in 1998, among others. He has publishedmany refereed journal and conference papers and is the holder of several patents(13 U.S. patents granted and many others pending as of February 2012). He isa member of Eta Kappa Nu and of Phi Kappa Phi.

VaraPrasad Arikatla (S’10) was born in Ongole,India. He received the B.Tech. degree in electronicsand communications engineering from AcharyaNagarjuna University, Guntur, India, in 2008 andPh.D. degree in electrical and computer engineer-ing from The University of Alabama, Tuscaloosa,in 2011.

He was with the University of Alabama, un-til 2012. He is now with Summit Microelectron-ics, Sunnyvale, CA. His research interests includemodeling and the control of power converters, high-

frequency power conversion, high-frequency magnetics, and energy harvesting.Dr. Arikatla served as a Reviewer for IEEE TRANSACTIONS ON POWER

ELECTRONICS, the IEEE Energy Conversion Congress and Exposition confer-ence (2010 and 2011), the IEEE International Conference on Electronics, Cir-cuits, and Systems (2010 and 2011), and the IEEE Applied Power ElectronicsConference (2011 and 2012).

Documents

Online Closed-Loop Autotuning Digital Controller for Switching Power Converters