7/28/2019 Old_SDADC

1/6

Sigma-Delta ADC and D AC for D igital Wireless Comm unication(Invited Paper)Zhongming Shi

NOK IA Mobile Phones Inc.9605 Scranton Road, San Diego, CA 92121, USA

MON4-2

A B S T M C TThis paper provides a brief overview ofSigma-Delta (CA) ADC and DACtechniques. An emphasis is given on theirapplications in wireless comm unication. Itfirst introduces the theory and designmethodology of low-power and high-resolution CA ADC's and DA C's for audioapplications. A discussion is then lead tohigh speed EA ADC's and DAC's for RFbaseband channel application in wirelesscommunication. Finally a discussion isgiven on IF bandpass CA ADC's andDAC's.

INTRODUCTIONContinuous development of wirelesscommunication pushes analog/digital(AD) and digital/analog (D/A)

conversion techniques to higher andhigher limits: higher resolution for stereoaudio, wider signal bandwidth for w irelesstransceiver, and less power consumptionis always desired. New digital systems ofwireless communication have beenproposed to p rovide higher data rate, highquality audio, video and interactivemultimedia. The imp lementations of suchsystems rely heavily on advanced AD andDA converters that lead and alter thecourse of system design andimplementation.CA A D D A conversion techniques [1,2]are very attractive to wirelesscommunication systems. That is, in part,due to the fact that they employ a 1-bit

internal D/A converter that does notrequire precision component matching.This technique allows ADC's and DAC'sto operate at low supply voltage and toconsume a minimum power. Furthermore,due to their noise shaping, CA ADC's andDAC's are immune to noise generated inportable devices where many clocks arerunning in a very compact size. Today,most cellular phones consist of CA ADCand DAC inside the voice CODEC.THEORY

At the cores of CAADC's and DAC'sare the CA modulators. TheZA modulators used in the ADC's areanalog implementation, where the one inDAC is digitally constructed. Based onthe fact that both share the same theoryand a similar architecture, and since mostof the analog CAmodulators areimplemented by a switch capacitortechnique, we can focus our discussion ontheir common discrete model. Fig.1showsa block diagram of a 2nd-orderCA modulator that is m ost com monly usedbecau se it is simple and stable.

Figure 1 A block diagram of a 2nd-orderCA modulatorThe 2nd-order EA modulator consists oftwo cascade integrator stages, with a

570-7803-5604-7/99/$10.000 1999 IEEE 1999IEEE Radio Frequency Integrated Circu its Symposium

7/28/2019 Old_SDADC

2/6

feedback loop to each stage. The firststage integrates the difference of the inputsignal and the feedback, and its output isthen scaled by a gain stage with a value A .The final stage is a 1-bit high speedcomparator (COMP). The 1 bit digitaloutput is converted back into an analog ormulti-bit digital format, depending onAD C or DA C implementation. Thefeedback signal is subtracted from theinput signal and the residual is integratedagain and again at a high clock rate. Thenegative loop back keeps the difference ata very. small level, and therefore theaverage of the 1-bit digital output isfinally equivalent to the input. The signaland noise transfer functions of the linearmodel of the modulator, respectivelydefined as H, and H,, are:

(1)1H , (Z) = ( 2 - z - ' )(2)2(1 - z- y( 2 - 3 2 I )H n ( Z ) =

Where A = 0.5. The selection of A willaffect the loop stability and noise shap ing.The frequency responses of signal andnoise are shown in Fig.2 and Fig.3. Themodulator behaves as a lowpass filter forsignal and a highpass filter for noise. Thequantization noise, originally white andgenerated by the comparator, the onlynon-linear component, is reshaped in thespectrum and most of the noise energy ismoved into the high frequency band, orthe high frequency portion of the clock.The signal to noise ratio (SNR) of the2nd-order modulator is determined usingthe clocking rate as follows [1,3]:

(3)7rSNR = ~

Where OSR is the oversampling ratiodefined by the ratio of the modulatorclock rate over twice the band width of thesignal.

Figure 2 Signal frequency response of the2nd-order ZA modulator with differentgain settingI I

0.05 0.1 0.15 0.2 0.25Frequency I Clock Rate

Figure 3 Noise frequency response of the2nd-order ZA modulator with differentgain settingIt is clear that to increase resolution an ddynamic range of the modulator, one hasto raise the clock rate. Higher clockingrates require a higher bandwidth for the

operational am plifiers (OPA) used in theintegrator and high-speed comparator.Both components, due to the widebandwidth, are power hungry. In thedigital implementation, the high-speed

58

7/28/2019 Old_SDADC

3/6

clocking rates are not difficult to achievewith today's sub-micron CMOStechnology. However, for portablewireless devices un-necessary high-speedclocking is always avoided. There aremany ways to raise the resolution whilekeeping the clock rate low. One is toincrease the order of the modulator. Butthe higher the order, the less stable themodulator becomes, and more complexhigher-order digital filtering is required[4]. To solve high order stabilityproblems, several topologies can be used,such as cascade [5,6] and multi-stagenoise-shaping (MASH) [7]. These havebeen implemented in wide range ofsuccessful products.

The other approach to increase resolutionat low clocking rate is to use a multi-bitquantizer. The technique however isinherently non-linear [8]. Dynamicelement matching or butterflyrandomizing [9] is suggested to overcomethe non-linearity problem introduced intothe system. There is always a trade offbetween the clocking rate and the order ofthe modulator or multi-bit quantizer used.Double sampling technique can alsoimprove the modulator resolution [10,111.To date, the most commonly usedmodulators in wireless portable devicesare 2nd-order and use a single bitquantizer.In practice l/f noise of MOS devicesand kT/C noise, thermal noise of switchcapacitors especially the ones forsampling, also contribute to the total noisein the signal band and therefore limit thedynamic range of the modulator. It isworth mentioning that sm all idle tones canbe observed at the modulator output if avery small dc signal is applied to theinput. Dithering techniques are employedto spread out the energy of the tones to outof the range of the signal band [12].

Audio Band EA ADC and DACThe first application of CA ADC's andDAC's in wireless comm unication devicesis for use in audio CODEC's. Today's

cellular phones require up to 14-bitresolution within a 3.4 kHz voice band.The new generation systems will require16-bit stereo over a 20 kHz bandwidth. Itis still a great challenge to design a low-power, compact size, high-resolution [13-171 CODE C for wireless portable d evices.Where integration level is high, theCODEC may not be a stand-alone device,instead it may be integrated into a large ICdevice where many other noisy blocks arerunning [18]. A great attention has to begiven to grounding and isolation of thecritical blocks to ensure noise reductionand crosstalk minimization. To achieve alarge dynamic range, techniques such asfully differential, common mode feedbackand common centroid layout need to beemployed.Figure 4 and 5 show the measuredpower spectrum of a voice CODECdesigned for CDMNAMPS cellularphones (Code Division Multiple Access /Advanced Mobile Phone System) [181.Both TX- and RX-channels consist of2nd-order CA modulators and post low-pass filters. The =-channel of theCODEC also consists of a low power and.size compact 2nd-order 1 bit demodulator[14,151.

RF Baseband CA ADC and DACTo explore the application of CAmodulators into a wider area of wirelessportable device s, people are looking at RFbaseband channel applications. Several

CA modulators were successfully designedfor GSM (Global System for Mobilecommunication)(8 b i td l3 5 kHz) [19,20].

59

7/28/2019 Old_SDADC

4/6

.a)T I...............,...............i

p

Figure 4 A measured power spectrum ofTX output of a 13-bit voice CODEC witha full-scale analog input

'1............................................. ~~ .............. spectrum of a 2nd-order CA modulatorwhere fclk = 20 MHz, and -12 dB inputsignals of CDMA (615 kHz), GSM (135............................ .~

-10 .............. ...............,............................. ..1 1

4 1e 8De

............................

'O 1CCC m 3m m,

FwuenLy (MIFigure 5 A measured power spectrum ofRX output of a 13-bit voice CODEC witha full-scale digital input.

1 kHz) and AMPS (15 kHz), respectively........................................................... :..IF Bandpass CA ADC and DAC.............. :...............

To further explore the application of EAmodulators, people are interested indigital IF by using bandpass (BP) ZAmodulators, the wireless transceiver isallowed to have cheap and reliable digitalsignal process, such as signal filtering,modulation, demodulation, coding,decoding and channel selection.Comparing to the baseband CAmodulators where the integrators are in aform of I/(I-Z'), now for BPCAmodulators, the integrators are replacedby the resonators in a form of l/(l-Z4)with four poles at nf,/4, where n =0, 1, 2,3. The signal and noise transfer functionsof the linear model of a 4th-orderbandpass ZA modulator defined as H, andH,,, are:

e 'I : I

(4)

I

Fig. 6 shows a simulated output power( 5 )spectrum of a 2nd-order CA modulator forthree different systems, AM PS (Advanced 2( 1 - z - 4 ) =2 - 2 - 4H . ( Z ) =Mobile Phone System, 12 bitdl5 kHz),

GSM and CDMA (Code Division Transfer functions of signal and noiseMultiple Access, 4 bitd61-5 kHz)~ share two pairs of complex-conjugaterespectively. poles. The signal transfer function is all-I I pole and the noise transfer function has

a,m-422-60

four pairs of complex-conjugate zeros thatare located exactly at the quarter of theclock frequency fclk. Fig.7 showssimulated signal and noise frequencyresponses of the 4th-order BPCAmodulator. This modulator behaves as abandpass filter for signal and a bandrejection filter for noise at f =f&/4.I I3.5 4 4.5 5 5.5 6 6.5 7Frequency (log(Hz)) 60

7/28/2019 Old_SDADC

5/6

Several BPCA-modulators are designedfor AM PS [21] and GSM [22-251. Fig.8shows a simulated output power spectrumof a 4th-order BPCA modulator with asignal input of a single side +615 kHzindicating a CD MA application.When implementing a BPCA modulatorin the ADC of an RF receiver, a verylimited freedom in selecting the IFfrequency is given by the system. Thehigher the IF, the smaller the IF SAWfilters required, but higher speed OPA'sare then needed which consume morepower. Furthermore, low jitter clockgenerators and high-resolution samp le andholder circuits are not easy to achieve athigh frequencies [26]. Although sub-sampling/mixing techniques and topologycan be considered as options [27].

0 n.

implementation for audio band, high-speed for RF baseband and high-frequency IF bandpass where the linearmodel, band location, pole/zerotransformation, signal and noise transferfunctions, stability are addressed.

50

:: , , , I , , , 1-40

0.10 0.2 02 2 0 24 0.26 0.20 0.3 0.32Frequency /C lock Rate

Figure 8 A simulated output powerspectrum of a 4th-order BPCA modulatorwhere f, =fclk/4 and -12 dB input where fs=f, +615 kHz

-10% 1. 1. - f.,. I 4 . l o% I.Norm.l,z.d F,.q".nsyFigure 7 Signal and noise Erequencyresponses of the 4th-orderBPCA modulator

SUMMARYA tutorial overview of CA ADC's andDAC's covers the basic concepts of

CA modulators, quantization noise, l/ f andkT/C noise, non-linearity of multi-bitquantization, dithering the idle tones,high-order stability, cascade and MASHtopologies. Double sampling technique,practical design aspects and wide bandchallenges are presented. The discussionscover low-power and high-resolution

ACKNOWLEDGMENTSThe author would like to thank Dr. FazalAli and K. Hsu for many helpful technicaldiscussions.REFERENCES

[11 S . R. Norsworthy, et al, "Delta-SigmaData Converters", IEEE Press, 1997.J. C. Candy, "Oversampling Delta-Sigma Data Converters", IEEE Press,1992.B. P. Agrawal and K. Shenoi, "DesignMethodology for CAM", IEEE Trans.Commun, Vol. COM-31, p360-370,1983.R. E. Crochiere and L. R. Rabiner,"Interpolation and Decimation ofDigital Signals - A Tutorial Review",Proc. of the IEEE, Vol. 69, p417-448,1981.T. L. Brook, et al, "A CascadedSigma-Delta Pipeline A/D Converterwith 1.25 MHz S ignal Bandwidth and89 dB SNR", IEEE JSSC, Vol. 32,~1896- 1906 , 199761

7/28/2019 Old_SDADC

6/6

[6] A. R. Feldman, et al, "A 13-bitY1.4-MS/s Sigma-Delta Modulator for RFBaseband Channel Applications",1998.[7] K. Uchimura, et al, "Oversampling A-to-D an d D -to-A Co n-rerters withMultistage Noise ShapingModulators", IEEE Trans. ASSP,

[SI R. Walden, et al, "Architectures ForHigh-Order Multibit Sigma-DeltaModulators", Proc. of IEEE ISCS,[9] A. Yasuda, et al, "A Third-Order AXModulator Using Second-OrderNoise-Shaping Dynamic ElementMatching", IEEE JSSC, Vol. 33,[lo] T. V. Burmas, et al, "A S econd-OrderDouble-Sampled Delta-SigmaModulator Using Additive-ErrorSwitching", IEEE JSSC, Vol. 31,[113 D. Senderowicz, et al, "Low-VoltageDouble-Sampled Converters", IEEE[12] M. Motamed, et al, ""Tones,

Saturation, and SNR in Double LoopEA Modulators", Proc. of IEEE

[13] V. Peluso, et al, "A 900-mV Low-Power AX A D Converter with 77-dBDynam ic Range", IE EE JS SC , Vo1.33,[14] Z.M. Shi, et al, "A 2.4V, 700pW0.1 8mm 2 Second-order Demod ulator

for High-resolution CA DAC's", Proc.[15] Z.M. Shi, et al, US Patent 5,821,891and E urope Patent 973 10417.7-2206[16] I. Fujimori and T. Sugimoto, "A 1.5V, 4.1 mW Dual-Channel AudioDelta-Sigma D/A Converter", IEEE

IEEE JSSC, Vol. 33, ~1462-1469,

pl899-1905,1988.

~ 8 9 5 - 8 9 8 , 9 90 .

~187 9-188 6, 998.

~284 -293, 996.

JSSC, Vol . 32, ~1 907 -19 19 , 997.

ISCAS, Vol . 2, ~1 345 -13 48, 993.

~188 7-189 7, 998.

of IEEE CICC, ~297 -300,1 997.

JSSC, Vol. 33, ~18 63- 187 0, 998.

[17] A. L. Coban and P. E. Allen, "A 1.5V1 OmW Audio AX Modulator with98dB Dynamic Range", Digest of[18] Z.M. Shi, et al, "A 2.7V MixedSignal Processor for CDMA/AMPSCellular Phones'' Digest of IEEERFIC Symp, 1999.[19] Y. Matsuya and J. Yamada, "1 VPower Supply Low-PowerConsumption A/D ConversionTechnique with Swing-SuppressionNoise Shaping", IEEE JSSC, Vol. 29,[20] P. C. Maulik, et al, "AnAnalogKIigital Interface for CellularTelephony", IEEE JSSCC, Vol. 30,[21] "Bandpass EA IF System", AnalogDevices, AD6 140 Data Sheet.E221 F. W. Singor and W. M. Snelgrove,"Switched-Capacitor Bandpass Delta-Sigma A/D Mo dulation at 10.7 MHz",[23] A. K. Ong and B. A. Wooley, "ATwo-Path Bandpass EA Modulator forDigital IF Extraction at 20 MHz",IEEE JSSC, V01.32, ~1920-1934,1997.[24] S. A. Jantzi, et al, "QuadratureBandpass Modulation for DigitalRadio", IEEE JSSC, Vol. 32, p1935-1950,1997.[25] T. Paulus, et al, "A CMOS IFTransceiver with Reduced AnalogComplexity", IEEE JSSC, Vol. 33,[26] W. Gao and W. M. Snelgrove, "A950-MHz IF Second-Order IntegratedLC Bandpass Delta-SigmaModulator", IEEE JSSC, Vol. 33,[27] A. Hairapetian, "An 81 MHz IFReceiver in CMOS", IEEE ISSCC,

IEEE ISSCC, ~ 5 0 - 5, 1999.

~1524- 1530 , 1994 .

p20 1-209, 19 95.

IEEE JSSC, Vol. 30, ~18 4- 19 2, 995.

~2154-2159 , 998.

p723-732,1998.p56-57, 1996.

62