510 IEEE ELECTROX DEVICE LETTERS, VOL. EDL-6, NO. 10, OCTOBER 1985

ation of Double-Hump Substrate Current in hape Tiansistors

T. Y. HUANG, MEMBER, IEEE, AND J . Y. CHEN, SENIOR MEMBER, IEEE

Abstract-n-channel transistors with a funnel-shape (FS) channel region were fabricated with thin gate oxide (21 nm) and short-channel length (1 pm) to study the effects of channel shapes on hot-electron effects. Two interesting phenomena are observed. First, the double-hump substrate current phenomenon is found when operating with wider channel close to drain side (wide-drain mode), while the narrow-drain mode shows the usual single-peak substrate current characteristics. Second, an enhanced gate current injection is found in the wide-drain mode, which is surprising as substrate current is actually lower in this mode. The finding is interesting as it suggests that floating-gate FS- tranistors with short-channel length and thin gate oxide are more efficient in programming when operating in wide-drain mode. This contradicts the previous SIMOS EPROM device that utilizes funnel-shape channel region operating in narrow-drain mode. The discrepancy is ascribed to the occurrence of. double-hump effect in substrate current and associated enhanced gate current injection in FS-transistors when channel length and gate oxide are scaled down.

I. INTRODUCTION

UBSTRATE CURRENT characteristics have been used extensively as the convenient tool for monitoring

hot-electron effects in n-channel transistors [ 11. Although a single peak is normally observed in the substrate current (Isub) versus gate voltage (V,) characteristics, double-hump I s u b phenomena are reported recently ,in a few device structures, including perpendicularly accelerating channel injection MOS (PAC- MOS) device with dual-gate structure [ 2 ] , graded-gate-oxide (GGO) MOSFET [3] and also in short-channel lightly doped- drain (LDD) and minimum overlap devices under certain conditions (thin gate oxide thickness, low n- -doping) [4], [ 5 ] . The double-hump IsUb phenomenon, besides being a reliability concern, could on the other hand be properly utilized as a potential low-voltage EPROM device, and is therefore of technological interest.

SIMOS (stacked-gate injection MOS) EPROM, which utilizes a funnel-shape (FS) channel region operating in narrow- drain mode has been reported to show increased programming efficiency [6] . Recently one of the present authors also demonstrates that 70-11m FS-transistor operating in the other mode (i.e., wide-drain mode) indeed depicts less Isub [7]. In this letter we report for the first time the observation of double- hump Is,,b and enhanced gate current (I,) injection in FS- transistors with thin (21-nm) gate oxide, while operating in wide-drain mode.

Manuscript received June 7 , 1985; revised August 1, 1985. The authors are with Xerox Palo Alto Research Center, Integrated Circuit

Laboratory, 3333 Coyote Rd.? Palo Alto, CA 94304.

11. EXPERIMENTAL RESULTS

Funnel-shape transistors with various Wl (channel width at the narrow side), W, (channel width at the wide side) and channel length down to 1 pm were fabricated with standard NMOS technology with LOCOS isolation. A thinner gate oxide (21 nm) is used in this study, as compared with thicker (70-nm) oxide used in previous report [7]. The transistors depict normal subthreshold slope and low subthreshold leak- age in the picoampere range for drain voltage ( Vd) at 5 V. No noticeable differences in threshold voltage and subthreshold slope are observed for the FS-transistors by switching source and drain. However, significant differences in substrate current behavior are observed. Typical ISUb versus V, charac- teristics of the resultant thin gate-oxide FS-transistors with Wl = 6 pm, w2 = 20 pm and &,sk = 1 pm are shown in Fig. l(a). It can be seen that I sub behaves quite differently by interchanging source and drain. While the usual single-peak I S u b is observed for narrow-drain mode, the double-hump effect is obvious in the wide-drain mode. The gate voltage at which I s u b depicts the minimum dip increases with Vd, a similar trend has been reported for GGO device and low n-- dose LDD device [3], [4]. Note that I sub is higher in the narrow-drain mode at any Vd for all V, biases, which is similar to that reported for 70-nm FS transistors [7]. For comparison, typical I s u b characteristics for the normal rectangular transis- tors with W, = W, = 20 pm, and L m & = 1 pm on the same wafer are shown in Fig. l(b). The rectangular device depicts quite similar I s u b behavior by switching source and drain, and the Isub decreases monotonically at high V,. No double-hump ISUb effect could be observed up to V, = 15 V, which is about the maximum voltage that could be suitably applied to the 21- nm gate oxide without entering Fowler-Nordheim tunneling regime. The minor asymmetry observed on normal rectangu- lar transistors could be attributed to n+ implant tilt angle, which has been shown to result in asymmetry in the MOSFET’s source/drain to gate overlapping [8]. However, the significant asymmetry and the double-hump effect in FS transistors are clearly due to the asymmetry of the channel shape. The results have been reproduced from run to run, and the effect is found to be more enhanced in the transistors with LDD structure. We have measured many (> 100) devices and the results remain the same. However, we could not apply any heuristic argument at the moment to explain why the double- hump I S U b effect shows up in wide-drain mode of the FS

0741-3106/85/1000-0510$01.00 0 1985 IEEE

HUANG AND CHEN: SUBSTRATE CURRENT IN FUNNEL-SHAPE TRANSISTORS 5 1 1

ISUB ( A I

-1E-04

decade i d i V

-1E-04

decade / d i v

.oooo VG l .SOO/dtv ( V)

1s. 00

(b) Fig. 1. Typical substrate current versus gate voltage with drain voltage as

parameter for a conventional (a) FS transistor with W, = 6 pm, W, = 20 pm, and (b) rectangular transistor with W, = W2 = 20 pm both with Lmask = 1 pm (dashed lines: wide-drain mode, solid lines: narrow-drain mode).

transistors. We believe it is due to some three-dimensional effects, and could only be resolved by elaborate three- dimensional simulations.

The gate current characteristics for the above FS transistor are plotted in Fig. 2(a). Significant Ig injection is obtained for v d as low as 7 V, and V, below 15 V during wide-drain mode (dashed curves), while no obvious Ig (above the noise background) could be measured for the narrow-drsin mode under the same bias condition (solid curves). For comparison, the rectangular transistor does not show noticeable I, by switching source 'and drain, as shown in Fig. 2(b). The enhancement of Ig injection for FS transistors in wide-drain mode is a surprising and interesting finding as ]sub, or E,,, that determines Isub, is actually higher for narrow-drain mode. The exact mechanism is still unclear, although it could be due to different positions of E, in the two modes, with E, in the wide-drain mode more favorable for 1, injection (e.g., closer to the silicon-silicon dioxide interface); or it could be due to a wider drain area in wide-drain mode that will act as a more effective collector for I,. Again the quantative answer could only be resolved by detailed three-dimensional simulations. The enhancement ifi I, injection is always observed for wide- drain mode of FS transistors used in this study, and seems to be associated with double-hump Isub phenomenon. This effect is found to be more enhanced with increased W2/ W, ratio, as

IG ( A)

1E-08

decade. i d i v

IE-12 .oo .oo

.oo

Fig. 2. Gate current versus gate voltage with drain voltage as parameter for the same transistors used in previous figure (a) FS-transistor (b) rectangular transistor (dashed lines: wide-drain mode, solid lines: narrow- drain mode).

should be expected. The phenomenon is interesting as the SIMOS EPROM device [ 6 ] , which utilizes a floating-gate FS transistor operating in narrow-drain mode has been reported to show enhanced programming efficiency for EPROM opera- tion. Since the double-hump ISUb effect appears to be a sensitive function to gate oxide thickness and channel length, as reported from the low n--dose EDD transistors [4], it is not surprising that as the SIMOS device that employs a thicker gate oxide and longer channel length would not depict the double-hump I s u b effect, so the narrow-drain mode is more favorable for Ig injection than the wide-drain mode, due to the larger Issub in the narrow-drain mode. With the occurrence of the double-hump Isub effect in short-channel FS-transistors that incorporate thinner gate oxide, it is actually the wide-drain mode taht is more favorable for I, injection.

111. CONCLUSION Funnel-shape transistors with thin gate oxide (21 nm) and

short channel elgnth (1 pm) have been investigated for hot- electron behaviors. The double-hump substrate current phe- nomenon, together with an enhanced gate current injection, are discovered in the wide-drain mode. The wide-drain mode in FS-transistors with short channel length and thin gate oxide is thus identified as the more efficient mode for programming the EPROM device. Work is still underway to fully under-

5 1 2 IEEE ELECTRON DEVICE LETTERS, VOL. EDL-6, NO. 10, OCTOBER 1985

stand the theory of the enchanced gate-current injection that seems to accompany the double-hump substrate current phenomenon.

ACKNOWLEDGMENT The authors are grateful to their colleagues at Xerox

Integrated Circuit Laboratory for processing the devices. They would dso like to thank R. Bruce for support and encourage- ment.

REFERENCES

[ l ] Y. W. Sing and B. Sudlow, “Modeling and VLSI design constraints of substrate current,” in IEDM Tech. Dig,, 1980, pp. 132-735.

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[5] H. Katto, K. Okuyama, S. Meguro, R. Nagai? and S. Ikeda, “Hot carrier degradation modes and optimization of LDD MOSFET’s,’‘ in IEDM Tech. Dig., 1984, pp. 174-111.

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[73 T. Y. Huang, “Effects of channel-shape on MOSFET hot-electron resistance,” IEE Electron. ketr., vol. 21: pp. 211-212, 1985.

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