NXP User Experience: Complex SoC Implementation with CPF

A Practical Guide to Low-Power DesignUser Experience with CPF

NXP User Experience: Complex SoCImplementation with CPF

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NXP User Experience: Complex SoC Implementation with CPF

By Herve Menager, Architect, SoC Design Technology, NXP Semiconductors.Founded by Philips, NXP is a top-10 semiconductor company creating semi-conductors, system solutions, and software that deliver better sensory experiences in mobile phones, personal media players, TVs, set-top boxes, identification applications, cars, and a wide range of other electronic devices.

Figure 122. NXP facts and figures

Established: 2006 (formerly a division of Royal Philips Electronics)50+ years of experience in semiconductors

Headquarters: Eindhoven, The Netherlands

President &CEO:

Frans van Houten

BusinessUnits:

Mobile & PersonalHomeAutomotive & IdentificationMultimarket SemiconductorsNXP Software

Net sales: € 4.96 billion in 2006

Sales byRegion:

22% China 16% Netherlands 12% Singapore 10% USA 7% Taiwan7% South Korea 5% Germany 21% Other

Research &Development:

Investment of about € 950 million7,500 engineers25,000+ patents26 R&D centers located in 12 countriesParticipation in over 75 standardization bodies & consortiaStrong links with universities

Employees: Approximately 37,000 people in more than 20 countries:37% Europe 37% Asia 21% Greater China 5% Americas

ManufacturingFacilities:

15 manufacturing sites worldwide:7 wafer fabs: Caen Fishkill Hamburg HazelJilin Nijmegen Singapore

8 test and assembly sites:Bangkok Cabuyao Calamba GuangdongHong Kong Kaohsiung Seremban Suzhou

Customers: 50+ direct customers accounting for approximately 70% of sales.Customers include Apple, Bosch, Dell, Ericsson, Flextronics, Foxconn, Nokia, Philips,Samsung, Siemens, and Sony.30,000+ customers reached via NXP’s semiconductor distributor partners, including Arrow, Avnet, Future, SA, C and WPI.


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Worldwide leadership positions include the following, by business unit:

Mobile & Personal

NXP provides complete entry-level to high-end system solutions for mobile phones that enable handset manufacturers to rapidly deliver highly featured and reliable products to the market. NXP’s solutions cover a wide range of current and upcoming telecom standards — EDGE, 3G and 4G — and seamlessly share content through a wide range of connectivity interfaces, such as Bluetooth and (wireless) USB, and even allow mobile payments using Near Field Communications (NFC).

More than 250 million Nexperia cellular system solutions shipped #1 in mobile phone speakers #1 in FM radio ICs for portable applications#1 in USB for mobile and portable applications#2 3G RFLeading the market with several industry firsts in TD-SCDMA development

Home NXP’s Nexperia-based Home system solutions and audio/video components enable manufacturers to offer consumers more digital content via a better viewing and listening experience. The Home business unit innovates embedded multimedia features and nextgeneration, connected multimedia appliances for a connected living experience — making it easier than ever to enjoy and share multimedia content, anytime and in every room.

1 out of 2 TVs worldwide contains an NXP Chip4 in 10 PC TVs use NXP silicon tuners#1 in TV reception tuners#1 in RF front end modules for digital terrestrial set top boxes Created Nexperia PNX5100, the world’s first video postprocessor with Motion Accurate Picture Processing technology

Identification NXP’s contactless technologies are designed to track inventory, improve logistics and protect people’s information-driven lives. NXP technologies can be found in everything from Radio Frequency Identification (RFID) tags that authenticate medicines, to e-ticketing systems that cut commute times and e-passports that fight identity theft and increase border security. In particular, Near Field Communication (NFC), a technology NXP co-developed, gives instant yet completely secure access to entertainment, information and services.

#1 in NFC (Near Field Communication)#1 in RFID (Radio Frequency Identification) solutions: over 2 billion ICs shipped#1 in e-passports with 80% of the world’s e-passports using NXP ICs 80% of all electronic tickets in public transport use NXP ICs

Automotive NXP’s Nexperia-based processors for automotive offer the same incredible sights and sounds the consumer expects at home, with seamless connectivity to personal media players. NXP’s in-vehicle networking technologies like FlexRay make cars more responsive and safer to drive while the RFbased car access solutions are helping to put car thieves out of business.

#1 in car radio tuners#1 in Digital Signal Processors for car radios#1 in automotive networking#1 in system solutions for automotive immobilizers and keyless entry/go

(Continued)


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Low Power is Critical to NXPFor NXP designs across all business units, at the device and system level, total power is important—both operating (or active) power and leakage power.

Low Operating Power is Important

For cost-sensitive battery-operated devices with no standby mode, the convergence of computing, communication, and entertainment increases the complexity of SoCs and requires higher-level silicon integration. Yet in spite of these challenges, the market expects and demands longer battery life. Also, cost of goods is a critical concern, and exotic heat-dissipating packages are costly. (Ref. 21)Home consumers who want electronic products that enhance the user environment insist on reduced noise (which means no fans) and cool-running products (again, requiring lower power dissipation).To meet these requirements, NXP is addressing low operating power at all design levels: transistor, logic, RTL, interconnect, architectural, and system.

Low Leakage Power is Important

For handheld devices with stand-by requirements, technology and the market combine to create the “Perfect Storm.” Customers want smaller, cooler mobile devices at lower cost. This again leads to both a dramatic increase in functionality and complexity and higher demands on standby battery lifetimes.Achieving the high levels of silicon integration required for these devices means using advanced processes, but unfortunately, advanced processes have inherently higher leakage current. This creates a challenge that must be addressed by both process and design.

Figure 123. NXP business units

Multimarket Semiconductors

NXP has one of the largest portfolios of multimarket semiconductors in the industry, from basic building blocks like timers and amplifiers to sophisticated ICs that improve media processing, wireless connectivity and broadband communications. These are designed to save space, extend battery life, enable customized solutions tailored to customers’ needs, and make it easy to implement lastminute changes.

#1 in 32-bit ARM-basedmicrocontrollers#1 in I²C-logic and industrial UARTs1 out of 2 laptops uses NXP’sGreenChip power supply controller#2 in small signal discretes andstandard logic worldwide

NXP Software NXP Software is a fully independent andleading provider of innovative multimediasoftware solutions focused on enhancing theUser Experience, reducing cost and improvingtime to market for device makers.

Independent Software Vendor formobile multimedia software solutionsMore than 250 million devices useLifeVibes software


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Leakage power can be addressed through choice of process, library options, transistor thresholds, design techniques, and other solutions.

NXP and CPF

NXP early recognized the need for an industry initiative to improve low-power flows, and began work on the Common Power Format (CPF) in early 2006. NXP was a founding member of the 26-company Power Forward Initiative (PFI) to drive direction and standardization of CPF. NXP was also an early member of the 18-company Low-Power Coalition (LPC) under Si2, which approved CPF as an Si2 standard in early 2007. (Ref. 22)In the larger sense of power and energy consumption and its impact on our environment, NXP also believes in taking corporate social responsibility, and has taken concrete steps and set clear goals in environmental impact for SoCs and electronic products.

Low-Power Implementation Trends

Previously, at less aggressive complexity and process nodes, NXP SoC designs avoided undue risk and complexity by primarily using the simple, reliable available power management techniques, which were cleanly supported by existing individual tools. So, among other techniques, for dynamic power, designers:

Reduced power dissipation sources when not needed • Gated clocks• Minimized switching capacitances• Used synchronous circuits such as handshake protocols•

And for leakage power, the approach involved:Used multi-• Vt synthesis and optimization at the physical level

Still, these common power reduction techniques were not enough to meet our power goals.More recently, we introduced aggressive, state-of-the-art techniques to control active and leakage power.For dynamic power, to meet both chip performance requirements and operating power goals, NXP designers used:

Voltage islands (MSV)• Dynamic voltage and frequency scaling• Adaptive voltage and frequency scaling •

For leakage power, designers:Suppressed current when not needed through power shut-off modes•

At the design level, however, without CPF, these advanced techniques can increase risk due to manual intervention in the design, reduce engineering productivity, increase complexity, slow time to market, and create timing and area problems. (Ref. 23)


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They are not only intrusive on the functionality of the SoC but also impact the entire design flow—from synthesis through verification and physical implementation. Without CPF—with manual intervention in flows—NXP’s past SoC designs identified the following challenges and limitations in MSV SoCs: (Ref. 24)

No placeholders for power and ground nets• No way to describe power specifications and constraints: power information is • sometimes available as a paper specification, but often exists only in the SoC architect’s mind, as it is not usually explicit in functional descriptionsRecurrent specification of the same power intent for each tool in the • design flowNo flow to verify power modes and power sequences in functional simulation• Increase of STA signoff cases• Vast increase of SDF simulation cases• No reusability of IP with multiple power domains in SoCs• Tremendous increase of implementation throughput time due to • lack of automationComplex signal distribution• Complex power grids• Design-for-test (DFT) complexity•

Specifying intent for automated implementation and verification is very complex, and the total problem is more than the sum of its parts.

Why a Common Power Format?

CPF solved these problems by delivering a power intent specification, separate from the functional specification. In CPF shared with RTL, both design intent and low-power intent are captured in the design specification as a power intent and functional specification pair.CPF facilitates a golden reference design specification, with separate low-power intent information, such that early exploration of different power architectures can be done and power behavior may be changed.

Figure 124. Functional and power intent

CPFPowerIntent

Specification

RTLFunctional

SpecificationDESIGN

Specification


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Since CPF allows the same low-power intent to be shared across all design tools, and from the start of the design through implementation, it offers the following oppor- tunities to reduce power while preserving design and implementation productivity.

Scalable solutions• The ability to capture power network intent independently and throughout the • tool flowNew tool functionality with an integrated flow•

Low-power design at RTL �Verification early in the design flow �Implementation based on the common power intent that was verified earlier �Validation of the power intent modeled at early design stage and the actual �implementation of the power intentDFT �

Support for advanced techniques • Voltage islands (MSV) �Dynamic voltage and frequency scaling (DVFS) �Adaptive voltage and frequency scaling (AVFS) �Power shut-off (PSO) �Low-power IP required by advanced techniques: level shifters, isolation �clamps, on-chip switches, state retention cells

IP and design reuse and portability•

The following SoC design example illustrates how NXP implemented several of these power reduction techniques with a CPF-enabled flow, and summarizes the user experience and results NXP obtained.

CPF in Action on a Complex SoC Platform NXP developed a complex SoC that challenged the current architecture and implementation flow, as a CPF proof-point project, and has regularly reported to the Power Forward Initiative on the status and progress over the last year. The CPF standard published by Si2 (Ref. 23) was the industry’s first power format to have tool support, with power intent captured in CPF and functionality in RTL description. This allowed the simple migration of a non-power-aware RTL design to a power-aware RTL design.This complex MSV NXP SoC (see Figure 125) incorporates 11 voltage islands.

There are 3 voltage-scalable logic sections, 3 on-chip switchable domains, 5 off-chip • switchable domains, and separate switchable pad ring sectionsThe 3 major power consumers (RISC CPU, VLIW DSP and L2 System Cache) are • controlled using DVFSHigh-bandwidth expansion ports enable the platform to be extended, for • example, with graphics or cellular modem subsystems

The die size of the chip is 42mm2 and it was fabricated in a 65nm CMOS process. (Ref. 21)


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Power Network Intent Before CPF, and for designs without advanced power management, power and ground were traditionally defined and implemented in the layout phase, as they had no functional impact on the chip (other than being necessary!).Now, power gating to minimize leakage current is making power and ground nets partly functional, since the behavior of the device depends on their state (clamping value) and level (performance.) The number of voltage islands in SoC and IP designs has increased complexity considerably. But neither RTL nor the logical views for basic library elements (leaf cells) have implicit representation of these nets, and special handling and global connection in the back-end phase is tedious and error-prone.With CPF, power and ground nets can be specified as part of a design’s low-power description with a standardized placeholder. Power intent for the power and ground network is modeled above the physical level abstraction of the design.

Figure 125. Complex platform SoC (Ref. 21,25)


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At the top level, two power domains are created: Power domain VALW is the default power domain and is always on • Power domain VARM_CORE is a switchable power domain with an associated • shut-off condition. An expression specifies the condition under which the power domain will be switched off

RTL designers can use CPF to describe the power-up and power-down behavior, and need not understand the details of how the power domain will eventually be implemented. CPF semantics for power domains furnish the power behavior for each instance, so all instances belonging to the same power domain share the same power characteristics such as voltage, on and off, etc. Power domain semantics model the power and ground network and its connections to the instance power and ground pins.This facilitates power-aware verification and simulation of the power-up and power-down behavior of the design. Later in the flow, at physical implementation, designers can associate a power and ground net for each power domain, and only then are power nets actually created and associated to the correct power domains.

set_cpf_version 1.0set_design e2_corecreate_power_domain –name VALW –default –instances \{u_cl_per/u_cl_per_valw_*…}

create_power_domain –name VARM_CORE\-instances {u_cl_arm/u_cl_arm_varm_1…} \-shutoff_condition {/u_cl_per/…/arm_vocore_switch_ena}

This approach allowed NXP designers to separate the power intent from the implementation, simplifying the task of verification engineers in validating the power mode and state transitions.

CPF Added Value in Verification

The NXP SoC, with 11 power islands, is representative of an increasing number of designs implemented with power shut-off, including multiple voltage islands which are temporarily powered down to reduce leakage power without affecting the functionality of the rest of the design.

create_power_nets -nets ALW_VDDupdate_power_domain -name VALW_domain -internal_power_net ALW_VDD

The power domain partitioning of the SoC design is shown in this short extract of the top level CPF:


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Power shut-off dramatically increases the complexity of design verification, and must be addressed at the beginning of the design cycle. Key issues that must be addressed during verification include the following. For power shut-off: Should an entire block be shut off, or just portions of the block? For isolation: Has logic been added which, when a block is powered down, prevents the propagation of unknown signals to the rest of the design? Are the right values forced on the inputs driven by power-down logic for this block to operate properly? For state retention: Are the values of key registers stored prior to power being shut-off? During initialization: How is a block initialized to a known state after power is restored?

Checking MSV Elements

With CPF, it is now possible to identify missing level shifters and clamps, and verify power intent in the context of RTL simulation:

Operation of the power-down modes • Clamping to the proper value(s)• Preventing deadlock in control networks that have a number of power domain • crossingsPrevention of misplaced timeout mechanisms • Retention, save, and restore cycles• System recovery at power-on•

CPF and Simulation of Power Modes

Before CPF-enabled flows, NXP previously verified power-down modes either using proprietary PLI/API based scripts, or by simulating with additional special standard cell libraries which modeled power state functional dependencies. These methods required manual recurrent specification of the power intent and were not easily scalable. Software rules the verification environment of the NXP design. The approach to test was to develop self-checking test cases to drive a central power mode controller, which controls the individual power-up and power-down sequences across various power domains of the chip. The power test cases were implemented as self-checking software running on either of the embedded CPU cores.Cadence Incisive Unified Simulator read in the CPF and simulated without changes to RTL. The simulator monitored power shut-off conditions with the potential to corrupt a power domain when triggered (Figure 126).


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Level Shifters and Clamps

In the NXP SoC, some isolation cells were inserted in RTL as opposed to using the CPF-enabled tool support. However, the insertion of isolation cells in RTL isn’t possible for all paths. Since the infrastructure for production test is generated during, or following the logic synthesis process, any paths traversing power domains created for production test are not present in the RTL. So, any isolation cells in these paths must be inserted during, or after design-for-test (DFT) insertion. The design team used the CPF design description to insert these isolation cells during the physical implementation phase and verified the functional integrity in simulation post-layout.Signals driven from a powered-down block must be clamped, and floating inputs to downstream blocks which remain on must also be clamped to the proper logical values for the powered-on blocks to operate properly. Defining the proper isolation cell value requires detailed knowledge of the inactive state for each IP’s input driven by a powered-down block. In the past, these values were stored in spreadsheets or other placeholders, but can now be captured in CPF when known. There are also challenges in identifying incorrect functional behavior in communication spanning power islands. The control network in the NXP design enables communication between IP cells in a number of power domains, so this control network has a number of power domain crossings. If communication is attempted to an IP cell that is powered down and unable to respond, this creates the risk of a deadlock on the control network. To overcome this potential deadlock, the control network implements a timeout mechanism, which aborts the transaction if one of the parties doesn’t respond. CPF-enabled simulation was proved very useful in detecting that the implementation of the timeout mechanism had been incorrectly placed in a powered-down domain, thereby disabling the timeout function itself.

Figure 126. Interface verification for power switching

Power Domain OFF Power Domain ON

Missing clamp

Expected inactivevalues from Spec

Functional error

Clamping to the wrong value

X

X

0

1


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NXP’s experience was that the power-on/off awareness and enhanced capabilities of Incisive Unified Simulator, with the CPF description of the design and HDL constructs in both Verilog and VHDL, allowed the design team to verify a range of power modes and uncovered a number of issues that would have been difficult to detect in previous designs.

Hierarchical Support for IP and Design ReuseTo leverage IP and design reuse in an advanced, power-managed design, both tools and the format must support hierarchical usage of power intent descriptions. The CPF design flow consisting of both power intent specification and functional specification helps define a hierarchical precedence mechanism.

Figure 127. Top-level design incorporating IP

Top.tpf

IP.tpfIP block

U_TB

U_TA

II_A

II_B

portA

(vddA)

(g)

(f)

(gnd)(vddB)

VDDA

VDDB GND

portB

TAA

BTB

TOPPD_A(1.2v)

PD_A(1.2v)

TOPPD_B(1.8v)

PD_B(1.8v)

For bottom-up reuse, power design intent has been developed along with the functional implementation of an IP.For soft IP, it must be reusable for the integration of the IP without having to rewrite the intent specification of the entire SoC. In the case of hard IP, the power intent must be derived from the IP implementation, and this description must also be usable to give IP visibility from the chip level for integration. For top-down constraint of lower-level IP implementation, the chip-level power design intent is created. Lower-level blocks must have their power design constraints derived from this chip-level description. The chip-level context must also be visible during IP implementation, so that IP implementation is done with the knowledge of the power domains, including both external boundary level power domains and state conditions.All of this can be done with CPF while staying at the abstract level, without doing manual design or floorplanning, and without specifying the IP instance by instance.


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Scalable ImplementationIn the past, ad-hoc manual approaches to low-power design lacked a holistic view and increased design and implementation time. NXP had in some cases experienced 2x productivity drop for the back-end implementation phase with the manual approach. This productivity penalty was due to lack of tool functionality and the lack of scalability of implementation of voltage islands, for instance:

Interface logic, whether isolation gates for power switching or level shifters • for voltage scaling, introduces verification challenges. Checks must be run to verify proper isolation, proper connectivity to the right power domains, proper partitioning of the netlist, and proper behavior of the interfaceLevel shifters, which are standard cells operating with two voltage supplies, • create a constraint for the layout implementationAlways-on logic resulting from buffering of control logic for retention or global • nets in power down blocks requires proper connection of their suppliesVoltage islands and on-chip switches create a challenge for power distribution • and limit floorplan alternatives and flexibility. More effort is necessary for connecting power sources to the voltage domainsCommunication between voltage islands may create logical paths spanning • power domain boundaries, increasing the number of corners and modes, and the number of static timing analysis (STA) runs

To alleviate these problems, CPF-based tools that understand the same power design intent can automate many of the manual tasks. Two examples of improvements introduced by CPF follow:

Power Logic Insertion

CPF describes rules governing interfaces between different power domains by adding isolation rules and/or level shifter rules only once. The CPF specification below defines from/to rules for signal interaction between power domains at a high level of abstraction, instead of requiring designers to describe them in an instance-specific way.

create_isolation_rule –name SOC_VDD_domain_to_Others\-from SOC_VDD_domain \-to {ALW_VDD_domain WSB_VDD_domain TM_VDD_domainARM_CORE_VDD_domain ARM_RAM_VDD_domainARM_VFP_VDD_domain}\-isolation_output low\-isolation_condition{lu_e2_pinmux/e2_core_inst/u_cl_per/u_cl_per_valw_2/ip_pmc_1_vsoc_clamp_ena_n}\-exclude $chiplet_inputs

update_isolation_rules –names rule_SOC_VDD_domain_to_Others\-location to \-cells HS65_LH_LSDOHLX18\


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Since voltage islands, multiple voltage supplies, level shifters, isolation logic, and power switches are specified with respect to the power domain (not in RTL), changes are facilitated. Rather than being forced to modify RTL to insert isolation cells, NXP designers were able to use CPF as their golden power intent specification, permitting a generic and scalable methodology from synthesis through routing.

Secondary Power Pin Connection

The Wasabe key infrastructure IP controls the memory access network. This IP block example is in one power domain with supply voltage WSB_VDD_D only; but it interfaces with several other voltage domains. So, the IP has level shifters on the receiving end of other power domains, as shown in Figure 128. In this case, the designer needed to avoid uncontrolled buffering of nets from input pins to the level shifter, and properly connect and route the extra power pins on the level shifter to power distribution.

Since chip-level power domains, TM_VDD_D and SOC_VDD_D, are made visible during the bottom-up block implementation, automation is improved and special handling of these cells removed. CPF provides the notion of virtual power domains (Figure 128) to which pins of the IP block are associated, thus providing the information about their power domains in the instantiation. Thus, level shifters can be implemented seamlessly regardless of the number of domains.

Figure 128. Wasabe IP block power domain interface

TM–VDD–D

IP WSB block

Vdd

Vddin

Gnd

Control /avoid buffering

Properly connect LSsecondary power pins

SOC–VDD–D


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CPF Mitigates Complexity of Modes and Corners Power reduction for the SoC depends on combining modes for which the voltage can be static or vary. This greatly increases the number of system-level modes, and it is essential to be able to capture these modes and how the transitions between them are governed. More modes and more corners have a significant effect on complexity of verification. Static timing analysis (STA) complexity increases with more corners:

Explosion of STA runs• Blocks will have operating corners, constraints, and libraries that will be • combined to create many analysis and optimization views

# WSB domaincreate_power_domain -name WSB_VDD_domain -default \

-boundary_ports ${e2_cl_wsb__WSB_domain__Output}update_power_domain -name WSB_VDD_domain -internal_power_net WSB_VDD# External domains to WSB#Name: SMC SOC_VDDcreate_power_domain -name SOC_VDD_domain \

-shutoff_condition ip_pmc_1_vsoc_clamp_ena_n \-boundary_ports ${e2_cl_wsb__SOC_domain__Input}

# Name: TM TM_VDDcreate_power_domain -name TM_VDD_domain \

-shutoff_condition ip_pmc_1_vtmc_clamp_ena_n \-boundary_ports ${e2_cl_wsb__TM_domain__Input}

# Name: ALW_VDD_domaincreate_power_domain -name ALW_VDD_domain \

-boundary_ports ${e2_cl_wsb__ALW_domain__Input}# Library informationdefine_isolation_cell -cells {HS65_LH_LSDOHLX18 HS65_LH_LSDOHHX18} -enable E -valid_location to\-power vddout -power_switchable vddin -ground gnddefine_level_shifter_cell -cells {HS65_LH_LSDOHLX18 HS65_LH_LSDOHHX18} \-input_voltage_range 0.7:1.2:0.1 \# Power Nets specified and connectedcreate_power_nets -nets WSB_VDDcreate_global_connection -net VSS -domain WSB_VDD_domain -pins gndcreate_global_connection -net WSB_VDD -domain WSB_VDD_domain -pins vddcreate_global_connection -net WSB_VDD -domain WSB_VDD_domain -pins vddout# Power Net connections and routing (outside of CPF1.0)connect2ndPwr SOC_VDD –cells ${LS_Cell_List} –pin vddin –from SOC_VDD_domain –toWSB_VDD_domainconnect2ndPwr TM_VDD –cells ${LS_Cell_List} –pin vddin –from TM_VDD_domain –toWSB_VDD_domainconnect2ndPwr ALW_VDD –cells ${LS_Cell_List} –pin vddin –from ALW_VDD_domain –toWSB_VDD_domain

Sample CPF for the virtual power domains on Wasabe follows:


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Four different modes with associated nominal voltages for five domains are shown in Figure 129:

Figure 129. Power modes

create_nominal_condition -name 1.2V -voltage 1.2…create_power_mode -name all_on -domain_conditions {[email protected][email protected] [email protected] [email protected][email protected] [email protected]} -defaultcreate_power_mode -name dbg_off -domain_conditions {[email protected][email protected] [email protected] [email protected]_VDD_domain@off [email protected]}

Here is an example of the CPF for several modes of operation for the power domains:

With DVFS, any active block may imply a range of operating voltages and therefore a large number of corners. Performing timing optimization and signoff verification on these corners can be overwhelming and may require many iterations. Signals between voltage islands can also be challenging. For signoff, on a synchronous path, besides the presence of interface logic, the hold condition should theoretically be explored with the highest voltage on the driving domain and the lowest voltage on the receiving domain. Intermediate operating points will probably need to be verified as well. In the example SoC, NXP reduced the potential timing issues on path spanning across power domains by making them asynchronous. (Ref. 26)This set of challenges needs the placeholder and abstraction for proper management provided by CPF. Raising the level of abstraction makes multi-mode, multi-corner analysis and optimization easier and less error-prone. Associating analysis views to each power mode gave NXP the ability to manage the different constraints and library associated to each operating condition of each power domain for each mode.

WSB_VDD0.9v

SOC_VDD1.2v

TM_VDD1.2v

DBG1.2v

ALW1.2v

all_on on on on on ondbg_off on on on off ontm_off on on off on onsoc_off on off on on on


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With a CPF centralized approach to single placeholder specification, power modes and operating conditions are concurrently taken into account during synthesis, optimization, STA, and formal verification in a multi-mode, multi-corner analysis and optimization flow.The overhead associated with the complexity of designing with multiple supplies is greatly removed by the scalability of the CPF solution.

DFT ImpactInsertion of scan chains across voltage islands can complicate implementation, and commercial tools are struggling to become multi-supply, multi-voltage aware. Some issues that arise from advanced low-power design in DFT include the following:

Naturally, the test control block needs to be assigned a power domain• Scan chains may span across power domains, and require level shifters• CTAG may span voltage domain, boundaries. Isolation should be placed within • the voltage domain of the I/O pinScan-chain routing within the boundaries of the voltage islands is preferred• Over-random stitching of scan flip-flops across the voltage islands creates • problemsTestability of level shifters and switches remains a problem•

However, if all power sequencing circuits will be held to a power-on state during test operation, the scan chain may not have to be designed based on voltage islands, simplifying the approach to multi-voltage test.

create_operating_corner -name WC_1v1_corner -library_set WC_1v1_lib -voltage 1.1 -temperature125 -process 1.5….create_analysis_view -name all_on_WC -modeall_on -domain_corners{WSB_VDD_domain@WC_1v3_corner \SOC_VDD_domain@WC_1v1_corner \TM_VDD_domain@WC_1v1_corner \DBG_VDD_domain@WC_1v1_corner \ALW_VDD_domain@WC_1v1_corner}

Here is the CPF for the analysis views for each power mode:


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CPF-Based ResultsThe SoC described earlier was designed by NXP as a CPF proof-point project and successfully taped out in 2007. The notable results of this design project are as follows:

Successful fabrication, in a 65nm process, of an aggressive design with 11 voltage • islands, 3 voltage-scalable logic sections, 3 on-chip switchable domains, 5 off-chip switchable domains, separate switchable pad ring sections, and 3 modules controlled using DVFSA 50% savings in implementing advanced power reduction techniques. In the • past, before CPF, we had in some cases experienced 2x productivity drop in the implementation phase for such designsCPF power-aware simulation also discovered a critical issue: a time-out • mechanism was being powered down in one particular mode, which could have caused deadlock conditions on the communication bus. With CPF we detected that the implementation of this timeout mechanism had been incorrectly placed in a domain that was subject to power-down, thereby disabling itself

This design demonstrated a scalable implementation of voltage islands. Tools understanding the same power design intent, with the highest possible level of abstraction, compensated for the throughput time overhead introduced by designing with multiple supplies. Level shifters, retention logic, and on-chip switches were logically inserted, verified, physically implemented, and analyzed. Power modes and operating conditions were managed during synthesis, optimization, and STA, with multi-mode multi-corner analysis and optimization. CPF provided the placeholder mechanism for power intent specification, avoiding error prone re-entry of the same power intent for each EDA tool in the flow, and supported better IP integration. NXP believes this methodology leads to significant time-to-market improvement.Having proven the value of this standard, NXP will continue to drive for the additional functionality required for designing with the most advanced power management techniques, in all forums. NXP, with other LPC members, is currently exploring CPF features such as enhancements to hierarchical IP reuse, memory (and other custom IP) modeling, power network component modeling, associating clocks to power mode transitions, and support for power estimation. Another active LPC working group is currently developing a data model and API interface to support rapid incremental what-if scenarios. A top-level data model view is shown below:


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Herve Menager is with Corporate Innovation & Technology at NXP Semiconductors. As Design Technology Architect, he is responsible for the SoC design environment and contributes to complex SoCs with a focus on advanced design techniques, including low-power, for which he has several publications. He also participates in technical committees for various conferences as well as industry consortium such as Si2. Prior to Philips, he held a variety of positions in physical design ranging from engineering manager responsible for the development of floorplanning and routing technology at Compass Design Automation (VLSI Technology) to methodology engineering at Aristo Technology. Herve holds a MSEE and graduated from ENSEEIHT (Ecole Nationale superieure d’electronique, electrotechnique, informatique, hydraulique et des Telecommunications) National Polytechnic Institute of Toulouse.

Figure 130. Top-level CPF data model view (Ref. 22)

Documents

NXP User Experience: Complex SoC Implementation with CPF