7/27/2019 NR-CPLD & FPGA ARCHITECTURE AND
APPLICATIONS.pdf
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Code No: B7704JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY
HYDERABAD
M.Tech II Semester Examinations, March/April 2011
CPLD & FPGA ARCHITECTURE AND APPLICATIONS
(EMBEDDED SYSTEMS AND VLSI DESIGN)Time: 3hours Max. Marks:
60
Answer any five questions
All questions carry equal marks
- - -
1. a) State the various types of PLDs available and
differentiate between PAL & PLA.
b) Implement the following Boolean function using a suitable
PAL
F(a, b, c, d) = m(2,4,6,8,10,11,12,14,15). [6+6]
2. a) Differentiate between CPLD and FPGA.b) Explain what is
macro cell with an example. [6+6]
3. Explain what is meant by metastability and how it can be
avoided in finite state
machines. [12]
4. Draw a state diagram for a sequence checker, whose output
will be 1 whenever the
sequence 1011 is detected. Develop a one-hot design for the same
sequence checker.
[12]
5. Draw an ASM chart for a digital system which counts the
number of 1s in the number
loaded into register R1 and sets register R2 to that number. The
same system is also
having one flip-flop called E to verify the bits of register R1.
[12]
6. Show how the Xilinx XC3000 CLB can provide 1-bit adder cell
for a parallel adder.
[12]
7. Explain the implementation of a 3-bit decade counter using
CLBS of Xilinx FPGA
device. [12]
8. Explain about the following:a) Functional Simulation.
b) Time Simulation.
c) Device Configuration . [12]
*****
NR
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