Not Recommended for New Designs VTM Current Multiplier · VTM ® Current Multiplier Rev 1.0 vicorpower.com Page 4 of 25 05/2014 800 927.9474 Part Ordering Information Device Input

Not Recommended for New Designs

VTM® Current Multiplier Rev 1.0 vicorpower.comPage 1 of 25 05/2014 800 927.9474

S

NRTLC US

VTM® Current Multiplier

High Efficiency, Sine Amplitude Converter™ (SAC™)

MIL-COTSMV036A Series

Features

• Family of MIL-COTs current multiplierscovering output voltages from 1 to 50 Vdc

n Operating from MIL-COTs PRM® modules

• High efficiency reduces system power consumption

• High density provides isolated regulated systemand saves space

• VI Chip® package enables surface mount or through hole,low impedance interconnect to system board

• Contains built-in protection features against:

n Overvoltagen Overcurrentn Short Circuitn Overtemperature

• ZVS/ZCS resonant Sine Amplitude Converter topology

• Less than 50ºC temperature rise at full load in typical applications

Typical Applications

• Land/Air/Sea Unmanned Vehicles/Drones

• Scanning Equipment• Radar

• Mobile Weapons

• Hybrid Vehicles

Product Description

The VI Chip® current multiplier is a high efficiency Sine Amplitude Converter™ (SAC™) operating from a 26 to 50 Vdc primary bus to deliver an isolated output. The Sine Amplitude Converter offers a low AC impedancebeyond the bandwidth of most downstream regulators, whichmeans that capacitance normally at the load can be located at the input to the Sine Amplitude Converter. This allows for areduction in point of load capacitance of typically >100x whichresults in a saving of board area, materials and total system cost.

The VTM current multiplier is provided in a VI Chip packagecompatible with standard pick-and-place and surface mountassembly processes. The co-molded VI Chip package providesenhanced thermal management due to large thermal interface

area and superior thermal conductivity. With high conversionefficiency the VTM current multiplier increases overall systemefficiency and lowers operating costs compared to conventional approaches.

The VTM current multiplier enables the utilization ofFactorized Power Architecture providing efficiency and sizebenefits by lowering conversion and distribution losses andpromoting high density point of load conversion.

Product Ratings

VIN = 26.0 V to 50.0 V POUT = up to 150 W

VOUT = 1.0 V to 50.0 V(various models)

IOUT = up to 80 A

Product Status

Part NumberProductStatus

Replaced by

MV036F015M080A NRND MVTM36Bx015M080A00











NRND = Not Recommended for New Designs

MV036A SeriesNot Recommended for New Designs


Typical Application

Using the MIL-COTs PRM, the output of the VTM is regulated over the load current range with only a single interconnectbetween the PRM and VTM and without the need for isolation in the feedback path.

PRM AL

SC

OS

CD VC

VH

+IN

–IN

+OUT

–OUT

SGND 1

SGND

GND

F1

CIN

VIN

16 V to 50 V LF 1 C

F 1

VC

TM

PC

VOUT

+IN

–IN –OUT

+OUT

ISOLATION BOUNDRY

VTM

PRIMARY SECONDARY

VTM Start Up Pulse and Temperature Feedback

VF: 26 V to 50 V

PC

PR

IL

TM

SGND

RSC

CSC

ROS

10KRVC

RDF

RCD

0.01µF

SEC_GND



Pin Configuration and Description

-In

PC

VC

TM

+In

-Out

+Out

-Out

+Out

Bottom View

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

4 3 2 1

A

B

C

D

E

H

J

K

L

M

N

P

R

T

Signal Name Pin Designation +In A1-E1, A2-E2–In L1-T1, L2-T2TM H1, H2VC J1, J2PC K1, K2

+OutA3-D3, A4-D4,J3-M3, J4-M4

–OutE3-H3, E4-H4,N3-T3, N4-T4



Part Ordering Information

DeviceInput Voltage

RangePackage Type

Output Voltagex 10

TemperatureGrade

OutputCurrent

Revision Version

VTM 36B F 015 M 080 A 00

VTM = VTM 36B = 26.0 to 50.0 V F = Full VIC SMD 015 = 1.5 V M = -55 to 125°C 080 = 80 A A 00 = Standard

Standard Models

All products shipped in JEDEC standard high profile (0.400” thick) trays (JEDEC Publication 95, Design Guide 4.10).

Part Number Package Size VIN K VOUT Temperature Current

MV036F015M080A Full VIC SMD 26.0 V to 50.0 V 1/24 1.50 V (1.08 V to 2.08 V) -55 to 125°C 80 A










MV036F360M003A Full VIC SMD 26.0 V to 50.0 V 1 36.0 V (26.0 V to 50.0 V) -55 to 125°C 3 A



General Electrical Characteristics

Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of-55°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted.

Absolute Maximum RatingsThe absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.

Parameter Comments Min Max Unit

+IN to -IN -1.0 60 VDC

PC to -IN -0.3 20 VDC

TM to -IN -0.3 7 VDC

VC to -IN -0.3 20 VDC

IM to -IN Half Chip only 0 3.15 VDC

+IN / -IN to +OUT / -OUT (hipot) 2250 VDC

Attribute Symbol Conditions / Notes Min Typ Max Unit

Input voltage range VIN

No external VC applied 26 50VDC

VC applied 0 50

VIN slew rate dVIN/dt 1 V/µs

Output voltage ripple VOUT_PP COUT = 0 F, IOUT = Full Load, VIN = 48 V, 20 MHz BW 5 % VOUT

Protection

Overvoltage lockout VIN_OVLO+ Module latched shutdown 52.0 56.0 58.5 V

Overvoltage lockout

response time constanttOVLO Effective internal RC filter 8 µs

Output overcurent trip IOCP 120 % IOUT_AVG

Short circuit protection trip current ISCP 150 % IOUT_AVG

Output overcurrent

response time constanttOCP Effective internal RC filter (Integrative) 3.8 ms

Short cicuit protection response time tSCPFrom detection to cessation of switching

(Instantaneous)1 µs

Thermal shutdown setpoint TJ_OTP 125 130 135 °C

Reverse inrush current protection Reverse Inrush protection disabled for this product



Model Specific Electrical Characteristics



MV036F015M080A

No load power dissipation PNL VIN = 26 V to 50 V 7.5 W

Transfer ratio K K = VOUT / VIN, IOUT = 0 A 1/24 V/V

Ouput voltage VOUT VOUT = VIN • K - IOUT • ROUT V

Output current (average) IOUT_AVG 80 A

Output current (peak) IOUT_PK tPEAK < 10 ms, IOUT_AVG ≤ 80 A 120 A

Efficiency (ambient) hAMB

VIN = 36 V, IOUT = 80 A 90.0 91.3%

VIN = 26 V to 50 V, IOUT = 80 A 87.3

Output resistance (cold) ROUT_COLD TC = -40°C, IOUT = 80 A 0.40 0.76 1.0 mΩ

Output resistance (ambient) ROUT_AMB TC = 25°C, IOUT = 80 A 0.55 0.98 1.4 mΩ

Output resistance (hot) ROUT_HOT TC = 100°C, IOUT = 80 A 0.65 1.18 1.5 mΩ

Switching frequency fSW 1.50 1.60 1.70 MHz

Output ripple frequency fSW_RP 3.00 3.20 3.40 MHz

MTBF

MIL-HDBK-217 Plus Parts Count; 25°C Ground Benign,

Stationary, Indoors / Computer Profile5.0 MHrs

Telcordia Issue 2 - Method 1 Case 1;

Ground Benign, Controlled6.7 MHrs

VC internal resistor RVC-INT 2 kΩ

MV036F022M055A







VIN = 36 V, IOUT = 55 A 92.6 93.7%

VIN = 26 V to 50 V, IOUT = 55 A 88.8






MTBF





VC internal resistor RVC-INT 1.0 kΩ



Model Specific Electrical Characteristics (Cont.)



MV036F030M040A







VIN = 36 V, IOUT = 40 A 92.5 94.0%

VIN = 26 V to 50 V, IOUT = 40 A 90.2






MTBF






MV036F045M027A







VIN = 36 V, IOUT = 27 A 93.0 94.7%

VIN = 26 V to 55 V, IOUT = 27 A 89.3






MTBF











MV036F060M020A







VIN = 36 V, IOUT = 20 A 94.6 95.5%

VIN = 26 V to 50 V, IOUT = 20 A 92.0






MTBF






MV036F072M017A







VIN = 36 V, IOUT = 17 A 95.3 95.9%

VIN = 26 V to 55 V, IOUT = 17 A 92.0






MTBF











MV036F090M013A







VIN = 36 V, IOUT = 13 A 93.8 95.3%

VIN = 26 V to 50 V, IOUT = 13 A 93.5






MTBF






MV036F120M010A







VIN = 36 V, IOUT = 10 A 94.2 94.9%

VIN = 26 V to 50 V, IOUT = 10 A 90.0






MTBF











MV036F180M007A







VIN = 36 V, IOUT = 7 A 93.0 94.0%

VIN = 26 V to 50 V, IOUT = 7 A 92.0






MTBF






MV036F240M005A





Output current (peak) IOUT_PK tPEAK < 10 ms, IOUT_AVG ≤ 5 A 7.5 A


VIN = 36 V, IOUT = 5 A 93.5 96.0%

VIN = 26 V to 50 V, IOUT = 5 A 93.0



Output resistance (hot) ROUT_HOT TC = 100°C, IOUT = 5 A 85.0 102.0 135 mΩ



MTBF











MV036F360M003A


Transfer ratio K K = VOUT / VIN, IOUT = 0 A 1 V/V



Output current (peak) IOUT_PK tPEAK < 10 ms, IOUT_AVG ≤ 3 A 4.5 A


VIN = 36 V, IOUT = 3 A 95.3 96.0%

VIN = 26 V to 50 V, IOUT = 3 A 93.3






MTBF








Signal Characteristics


VTM Control: VC

• Used to wake up powertrain circuit.• A minimum of 12 V must be applied indefinitely for VIN ≤ 26 V to ensure normal operation.• VC slew rate must be within range for a successful start.• PRM® VC can be used as valid wake-up signal source.• VC voltage may be continuously applied; there will be minimal VC current drawn when VIN ≥ 26 V and VC ≤ 13.• Internal resistance used in adaptive loop compensation

SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

ANALOGINPUT

Steady

External VC voltage VVC_EXTRequired for startup, and operation

below 26 V. 12 16.5 V

VC current draw threshold VVC_TH Low VC current draw for Vin >26 V 13 V

VC current draw IVC

VC = 13 V, VIN = 0 V 150

mAVC = 13 V, VIN > 26 V 0

VC = 16.5 V, VIN > 26 V 0

Start UpVC slew rate dVC/dt Required for proper startup 0.02 0.25 V/µs

VC inrush current IINR_VC VC = 16.5 V, dVC/dt = 0.25 V/µs 750 mA

Transitional

VC output turn-on delay tONVIN pre-applied, PC floating, VC

enable; CPC = 0 µF, COUT = 4000 µF500 µs

VC to PC delay tVC_PCVC = 12 V to PC high, VIN = 0 V,

dVC/dt = 0.25 V/µs10 25 µs

Primary Control: PC

• The PC pin enables and disables the VTM. When held below 2 V, the VTM will be disabled.• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V during fault mode given Vin ≥ 26 V and VC ≥ 12 V.• After successful start-up and under no fault condition, PC can be used as a 5 V regulated voltage source with a 2 mA maximum current.• Module will shutdown when pulled low with an impedance less than 400 Ω.• In an array of VTMs, connect PC pin to synchronize startup.• PC pin cannot sink current and will not disable other modules during fault mode.


ANALOGINPUT

Steady

PC voltage VPC 4.7 5.0 5.3 V

PC source current IPC_OP 2 mA

PC resistance (internal) RPC_INT Internal pull down resistor 50 150 400 kΩ

Start Up

PC source current IPC_EN 50 100 300 µA

PC capacitance (internal) CPC_INT 50 pF

PC resistance (external) RPC_EXT 60 kΩ

DIGITALINPUT / OUTPUT

Enable PC voltage (enable) VPC_EN 2 2.5 3 V

DisablePC voltage (disable) VPC_DIS 2 V

PC pull down current IPC_PD 5.1 mA

TransitionalPC disable time tPC_DIS_T 4 µs

PC fault response time tFR_PC From fault to PC = 2 V 100 µs



Signal Characteristics (Cont.)


Temperature Monitor: TM

• The TM pin monitors the internal temperature of the VTM controller IC within an accuracy of ±5°C.• Can be used as a "Power Good" flag to verify that the VTM is operating.• The TM pin has a room temperature setpoint of 3 V (@27°C) and approximate gain of 10 mV/ °C.


ANALOGOUTPUT

Steady

TM voltage VTM_AMB TJ controller = 27°C 2.95 3.00 3.05 V

TM source current ITM 100 µA

TM gain ATM 10 mV/°C

DIGITALOUTPUT(FAULT FLAG)

Disable TM voltage VTM_DIS 0 V

Transitional

TM resistance (internal) RTM_INT Internal pull down resistor 25 40 50 kΩ

TM capacitance (external) CTM_EXT 50 pF

TM fault response time tFR_TM From fault to TM = 1.5 V 10 µs



Timing diagram

12

7

V IN

1. In

itiat

ed V

C pu

lse

2. C

ontr

olle

r sta

rt3.

VIN

ram

p up

4. V

IN =

VO

VLO

5. V

IN ra

mp

dow

n no

VC

puls

e6.

Ove

rcur

rent

7. S

tart

up

on s

hort

circ

uit

8. P

C dr

iven

low

V OU

T

PC

3 V

VC

NL

5 V

V OVL

O

TMV T

M-A

MB

c

Not

es:

– T

imin

g an

d vo

ltage

is n

ot to

sca

le

–

Err

or p

ulse

wid

th is

load

dep

ende

nt

a: V

C sl

ew ra

te (d

VC/d

t)

b: M

inim

um V

C pu

lse

rate

c: T

OVL

O

d: T

OCP

e: O

utpu

t tur

n on

del

ay (T

ON

)f:

PC

disa

ble

time

(TPC

_DIS

_T)

g: V

C to

PC

dela

y (T

VC_P

C)

d

I SSP

I OU

T

I OCP

V VC-

EXT

34

5

6

a

b

8

gef

≥ 26

V



General Characteristics



Mechanical

(Full VIC)

Length L 32.25 / [1.270] 32.5 / [1.280] 32.75 / [1.289] mm/[in]

Width W 21.75 / [0.856] 22.0 / [0.866] 22.25 / [0.876] mm/[in]

Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in]

Volume Vol No heat sink 4.81 / [0.294] cm3/[in3]

Weight W 15.0 / [0.53] g/[oz]

(Half VIC)

Length L 21.7 / [0.85] 22.0 / [0.87] 22.3 / [0.88] mm/[in]

Width W 16.4 / [0.64] 16.5 / [0.65] 16.6 / [0.66] mm/[in]

Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in]

Volume Vol No heat sink 2.44 / [0.150] cm3/[in3]

Weight W 8.0 / [0.28] g/[oz]

Lead finish

Nickel 0.51 2.03

µmPalladium 0.02 0.15

Gold 0.003 0.051

Thermal

Operating temperature TJ -55 125 °C

Thermal Resistance (Full VIC) ΦJCIsothermal heat sink and isothermal

internal PCB1 °C/W

Thermal Resistance (Half VIC) ΦJCIsothermal heat sink and

isothermal internal PCB2.2 °C/W

Assembly

Storage temperature TST -65 125 °C

Moisture sensitivity level MSLMSL 6, TOB = 4 hrs

MSL 5

ESD withstand

ESDHBM

Human Body Model Component Level

ANSI/ESDA/JEDEC JS-001-2012,

Class 1C 1000 to <2000 V

1000

VDC

ESDCDMField Induced Change Device Model

JESD22-C101E, Class II 200 to <500 V200



General Characteristics Cont.



Soldering

Peak temperature during reflowMSL 6, TOB = 4 hrs 245 °C

MSL 5 225 °C

Peak time above 217°C 60 90 s

Peak heating rate during reflow 1.5 3 °C/s

Peak cooling rate post reflow 1.5 6 °C/s

Safety

Isolation voltage (hipot) VHIPOT 2250 VDC

Isolation resistance RIN_OUT 10 MΩ

Agency approvals / standards

cTUVus

cURus

CE Marked for low voltage directive and RoHS recast directive, as applicable



Using the control signals VC, PC, TM, IM

The VTM Control (VC) pin is an input pin which powers the internalVCC circuitry when within the specified voltage range of 12 V to 16.5 V.This voltage is required in order for the VTM module to start, and mustbe applied as long as the input is below 26 V. In order to ensure aproper start, the slew rate of the applied voltage must be within thespecified range.

Some additional notes on the using the VC pin:

n In most applications, the VTM module will be powered by an upstream PRM® which provides a 10 ms VC pulse during startup. In these applications the VC pins of the PRM and VTM should be tied together.

n The VC voltage can be applied indefinitely allowing for continuous operation down to 0 VIN.

n The fault response of the VTM module is latching. A positive edge on VC is required in order to restart the unit. If VC is continuously applied the PC pin may be toggled to restart the module.

Primary Control (PC) pin can be used to accomplish the followingfunctions:

n Delayed start: Upon the application of VC, the PC pin will source a constant 100 µA current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start.

n Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each VTM PC provides a regulated 5 V, 2 mA voltage source.

n Output disable: PC pin can be actively pulled down in order to disable the module. Pull down impedance shall be lower than 400 Ω.

n Fault detection flag: The PC 5 V voltage source is internally turned off as soon as a fault is detected. It is important to notice that PC doesn’t have current sink capability. Therefore, in an array, PC line will not be capable of disabling neighboring modules if a fault is detected.

n Fault reset: PC may be toggled to restart the unit if VC is continuously applied.

Temperature Monitor (TM) pin provides a voltage proportional to theabsolute temperature of the converter control IC.

It can be used to accomplish the following functions:

n Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied, TM can be used to thermally protect the system.

n Fault detection flag: The TM voltage source is internally turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of TM signal.

Current Monitor (IM) (half chip models only) pin provides a voltageproportional to the output current of the VTM module. The nominalvoltage will vary between VIM_NL to VIM_FL over the output current rangeof the module. The accuracy of the IM pin will be within 25% under allline and temperature conditions between 50% and 100% load.

Startup behaviorDepending on the sequencing of the VC with respect to the inputvoltage, the behavior during startup will vary as follows:

n Normal Operation (VC applied prior to Vin): In this case the controller is active prior to ramping the input. When the input voltage is applied, the VTM output voltage will track the input. The inrush current is determined by the input voltage rate of rise and output capacitance. If the VC voltage is removed prior to the input reaching 26 V, the VTM module may shut down.

n Stand Alone Operation (VC applied aer Vin): In this case the module output will begin to rise upon the application of the VC voltage. A so-start circuit may vary the ouput rate of rise in order to limit the inrush current to it’s maximum level. When starting intohigh capacitance, or a short, the output current will be limited for a maximum of 900 µsec. Aer this period, the adaptive so start circuit will time out and the module may shut down. No restart will be attempted until VC is re-applied, or PC is toggled. To ensure a successful start in this mode of operation, additional capacitance on the output of the VTM should be kept to a minimum.

Thermal ConsiderationsVI Chip® products are multi-chip modules whose temperaturedistribution varies greatly for each part number as well as with theinput / output conditions, thermal management and environmentalconditions. Maintaining the top of the VTM case to less than 100ºC willkeep all junctions within the VI Chip below 125ºC for mostapplications.

The percent of total heat dissipated through the top surface versusthrough the J-lead is entirely dependent on the particular mechanicaland thermal environment. The heat dissipated through the top surfaceis typically 60%. The heat dissipated through the J-lead onto the PCBboard surface is typically 40%. Use 100% top surface dissipation whendesigning for a conservative cooling solution.

It is not recommended to use a VI Chip module for an extended periodof time at full load without proper heat sinking

Sine Amplitude Converter™Point of Load ConversionThe Sine Amplitude Converter (SAC™) uses a high frequency resonanttank to move energy from input to output. The resonant LC tank,operated at high frequency, is amplitude modulated as function ofinput voltage and output current. A small amount of capacitanceembedded in the input and output stages of the module is sufficient forfull functionality and is key to achieving power density.

A typical SAC can be simplified into the model above.

At no load:

VOUT = VIN • K (1)

K represents the “turns ratio” of the SAC. Rearranging Eq (1):

K = VOUT (2)

VIN

In the presence of load, Vout is represented by:

VOUT = VIN • K – IOUT • ROUT (3)

and Iout is represented by:

IOUT = IIN – IQ (4)

K

ROUT represents the impedance of the SAC, and is a function of theRDSON of the input and output MOSFETs and the winding resistance ofthe power transformer. Iq represents the quiescent current of the SACcontrol and gate drive circuitry.

The use of DC voltage transformation provides additional interestingattributes. Assuming for the moment that ROUT = 0 Ω and IQ = 0 A, Eq.(3) now becomes Eq. (1) and is essentially load independent. A resistorR is now placed in series with VIN as shown in Figure 2.

The relationship between VIN and VOUT becomes:

VOUT = (VIN – IIN • R) • K (5)

Substituting the simplified version of Eq. (4) (IQ is assumed = 0 A) into Eq. (5) yields:

VOUT = VIN • K – IOUT • R • K2 (6)

This is similar in form to Eq. (3), where ROUT is used to represent thecharacteristic impedance of the SAC™. However, in this case a real R onthe input side of the SAC is effectively scaled by K2 with respect to the output.

Assuming that R = 1 Ω, the effective R as seen from the secondary sideis 0.98 mΩ, with K = 1/32 as shown in Figure 2.

A similar exercise should be performed with the additon of a capacitor,or shunt impedance, at the input to the SAC. A switch in series with VIN

is added to the circuit. This is depicted in Figure 3.



+

–

+

–

VOUT

COUTVIN

V•I

K

+

–

+

–

CIN

IOUT

RCOUT

IQ

ROUT

RCIN

Figure 1 — VI Chip® module AC model (MVTM48EH040M025A00 shown)

0.057 A

1/12 • IOUT 1/12 • VIN

6.2 mΩRCIN6.3 mΩ

150 pH

350 mΩ RCOUT330 µΩ

68 µF

LOUT = 600 pH

900 nFIQ

LIN = 1.7 nH IOUT ROUT

VIN VOUT

COUTCIN

R

SACK = 1/32Vin

Vout+–

Figure 2 — K = 1/32 Sine Amplitude Converter™with series input resistor


A change in VIN with the switch closed would result in a change incapacitor current according to the following equation:

IC(t) = CdVin

(7)dt

Assume that with the capacitor charged to VIN, the switch is openedand the capacitor is discharged through the idealized SAC. In this case,

IC = IOUT • K (8)

Substituting Eq. (1) and (8) into Eq. (7) reveals:

IOUT =C • dVOUT (9)K2 dt

Writing the equation in terms of the output has yielded a K2 scalingfactor for C, this time in the denominator of the equation. For a K factorless than unity, this results in an effectively larger capacitance on theoutput when expressed in terms of the input. With a K = 1/32 as shownin Figure 3, C = 1 µF would effectively appear as C = 1024 µF whenviewed from the output.

Low impedance is a key requirement for powering a high-current, low-voltage load efficiently. A switching regulation stage should haveminimal impedance, while simultaneously providing appropriatefiltering for any switched current. The use of a SAC between theregulation stage and the point of load provides a dual benefit, scalingdown series impedance leading back to the source and scaling up shuntcapacitance (or energy storage) as a function of its K factor squared.However, these benefits are not useful if the series impedance of theSAC is too high. The impedance of the SAC must be low well beyondthe crossover frequency of the system.

A solution for keeping the impedance of the SAC low involvesswitching at a high frequency. This enables magnetic components to besmall since magnetizing currents remain low. Small magnetics meansmall path lengths for turns. Use of low loss core material at highfrequencies reduces core losses as well.

The two main terms of power loss in the VTM module are:

n No load power dissipation (Pnl): defined as the power used to powerup the module with an enabled power train at no load.

n Resistive loss (ROUT): refers to the power loss across the VTM current multiplier modeled as pure resistive impedance.

PDISSIPATED = PNL + PROUT (10)

Therefore,

POUT = PIN – PDISSIPATED = PIN – PNL – PROUT (11)

The above relations can be combined to calculate the overall moduleefficiency:

h =POUT = PIN – PNL – PROUT (12)PIN PIN

=VIN • IIN – PNL – (IOUT)2 • ROUT

VIN • IIN

= 1 – PNL + (IOUT)2 • ROUT

VIN • IIN

Input and Output Filter DesignA major advantage of a SAC™ system versus a conventional PWMconverter is that the former does not require large functional filters.The resonant LC tank, operated at extreme high frequency, is amplitudemodulated as a function of input voltage and output current andefficiently transfers charge through the isolation transformer. A smallamount of capacitance embedded in the input and output stages of themodule is sufficient for full functionality and is key to achieving highpower density.

This paradigm shi requires system design to carefully evaluateexternal filters in order to:

1. Guarantee low source impedance.

To take full advantage of the VTM module dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. Input capacitance may be added to improve transient performance or compensate for high source impedance.

2. Further reduce input and/or output voltage ripple without sacrificing dynamic response.

Given the wide bandwidth of the VTM module, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the module multiplied by its K factor.

3. Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures.

The VI Chip® module input/output voltage ranges must not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it.

C

S

SACK = 1/32Vin

Vout+–

Figure 3 — Sine Amplitude Converter™ with input capacitor

( )




Capacitive Filtering Considerations for a Sine Amplitude ConverterIt is important to consider the impact of adding input and outputcapacitance to a Sine Amplitude Converter™ on the system as a whole.Both the capacitance value, and the effective impedance of thecapacitor must be considered.

A Sine Amplitude Converter has a DC ROUT value which has alreadybeen discussed in the previous section. The AC ROUT of the SAC containsseveral terms:

n Resonant tank impedance

n Input lead inductance and internal capacitance

n Output lead inductance and internal capacitance

The values of these terms are shown in the behavioral model in theprior section. It is important to note on which side of the transformerthese impedances appear and how they reflect across the transformergiven the K factor.

The overall AC impedance varies from model to model but for mostmodels it is dominated by DC Rout value from DC to beyond 500 KHz.

Any capacitors placed at the output of the VTM module reflect back tothe input of the module by the square of the K factor (Eq. 9) with theimpedance of the module appearing in series. It is very important tokeep this in mind when using a PRM® regulator to power the VTM.Most PRM regulators have a limit on the maximum amount ofcapacitance that can be applied to the output. This capacitance includesboth the regulator output capacitance and the current multiplieroutput capacitance reflected back to the input. In PRM regulatorremote sense applications, it is important to consider the reflectedvalue of VTM current multiplier output capacitance when designingand compensating the PRM regulator control loop.

Capacitance placed at the input of the VTM module appear to the loadreflected by the K factor, with the impedance of the VTM module inseries. In step-down VTM ratios, the effective capacitance is increasedby the K factor. The effective ESR of the capacitor is decreased by thesquare of the K factor, but the impedance of the VTM module appearsin series. Still, in most step-down VTM modules an electrolyticcapacitor placed at the input of the module will have a lower effectiveimpedance compared to an electrolytic capacitor placed at the output.This is important to consider when placing capacitors at the output ofthe current multiplier. Even though the capacitor may be placed at theoutput, the majority of the AC current will be sourced from the lowerimpedance, which in most cases will be the VTM current multiplier.This should be studied carefully in any system design using a VTMcurrent multiplier. In most cases, it should be clear that electrolyticoutput capacitors are not necessary to design a stable, well-bypassed system.

Current SharingThe SAC™ topology bases its performance on efficient transfer ofenergy through a transformer without the need of closed loop control.For this reason, the transfer characteristic can be approximated by anideal transformer with some resistive drop and positive temperature coefficient.

This type of characteristic is close to the impedance characteristic of aDC power distribution system, both in behavior (AC dynamic) andabsolute value (DC dynamic).

When connected in an array with the same K factor, the VTM modulewill inherently share the load current with parallel units, according tothe equivalent impedance divider that the system implements from thepower source to the point of load.

Some general recommendations to achieve matched array impedances:

n Dedicate common copper planes within the PCB to deliver and return the current to the modules.

n Provide the PCB layout as symmetric as possible.

n Apply same input / output filters (if present) to each unit.

For further details see AN:016 Using BCM® Bus Converters in High Power Arrays.

Fuse SelectionIn order to provide flexibility in configuring power systems VI Chip®products are not internally fused. Input line fusing of VI Chip productsis recommended at system level to provide thermal protection in caseof catastrophic failure.

The fuse shall be selected by closely matching system requirements with the following characteristics:

n Current rating (usually greater than maximum VTM module current)

n Maximum voltage rating (usually greater than the maximum possible input voltage)

n Ambient temperature

n Nominal melting I2t

Reverse OperationThe MVTM is capable of reverse operation. If a voltage is present at the output which satisfies the condition VOUT >VIN • K at the time the VC voltage is applied, or aer the unit hasstarted, then energy will be transferred from secondary to primary. Theinput to output ratio will be maintained. The MVTM will continue tooperate in reverse as long as the input and output are within thespecified limits. The MVTM has not been qualified for continuousoperation (>10 ms) in the reverse direction.

VIN VOUT

+

– DC

ZIN_EQ1

ZIN_EQ2

ZOUT_EQ1

ZOUT_EQ2

Load

VTM®1RO_1

VTM®2RO_2

VTM®nRO_n

ZOUT_EQnZIN_EQn

Figure 4 — VTM module array

http://www.vicorpower.com/documents/application_notes/vichip_appnote16.pdf

http://www.vicorpower.com/documents/application_notes/vichip_appnote16.pdf



Product Outline & Recommended Land Pattern; Full VIC SMD, 18 pin



Product Outline & Recommended Land Pattern; Full VIC TH, 60 pin



Recommended Heat Sink Push Pin Location; Full

Notes:

1. Maintain 3.50 (0.138) Dia. keep-out zone free of copper, all PCB layers.2. (A) Minimum recommended pitch is 39.50 (1.555). This provides 7.00 (0.275) component edge-to-edge spacing, and 0.50 (0.020) clearance between Vicor heat sinks. (B) Minimum recommended pitch is 41.00 (1.614). This provides 8.50 (0.334) component edge-to-edge spacing, and 2.00 (0.079) clearance between Vicor heat sinks.

3. VI Chip® module land pattern shown for reference only; actual land pattern may differ. Dimensions from edges of land pattern to push–pin holes will be the same for all full-size VI Chip® products.4. RoHS compliant per CST–0001 latest revision.

(NO GROUNDING CLIPS) (WITH GROUNDING CLIPS)

5. Unless otherwise specified: Dimensions are mm (inches) tolerances are: x.x (x.xx) = ±0.3 (0.01) x.xx (x.xxx) = ±0.13 (0.005)6. Plated through holes for grounding clips (33855) shown for reference, heat sink orientation and device pitch will dictate final grounding solution.



Revision History

Revision Date DescriptionPage

Number(s)

1.0 5/2014 Initial Release N/A



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