NOORUL ISLAM CENTRE FOR HIGHER EDUCATION - … · NOORUL ISLAM CENTRE FOR HIGHER EDUCATION NOORUL ISLAM ... EE1502 VLSI Design 3 0 0 ... Taha, H.A., “Operations Research – An

NOORUL ISLAM CENTRE FOR HIGHER EDUCATION

NOORUL ISLAM UNIVERSITY, KUMARACOIL

M.E. APPLIED ELECTRONICS

CURRICULUM & SYLLABUS

SEMESTER I

Sl. No Code No. Course Title L T P C

THEORY

1. MA1501 Advanced Mathematics 3 1 0 4

2. EC1503 Advanced Digital Signal Processing 3 0 0 3

3. EE1501 Advanced Digital System Design 3 0 0 3

4. EE1502 VLSI Design 3 0 0 3

5. CS1501 Advanced Computer Architecture 3 0 0 3

6. XX5E1 Elective I 3 0 0 3

PRACTICAL

7. EE1571 Electronic Design Lab I 0 1 2 2

Total 18 2 2 21

MA1501 ADVANCED MATHEMATICSL T P C3 1 0 4

AIM:To gain a well found knowledge of optimizing a function and variational problems

which provide necessary mathematical support and confidence to tackle real life problems.

OBJECTIVE:The course objective is to extend the ability of the students in the areas of Matrix

Theory and Stochastic Processes. This will be applicable in Engineering practices and serveas a pre-requisite for higher studies and research.

UNIT I ADVANCED MATRIX THEORY 9Generalised Eigen vectors– Jordan canonical form –– Matrix norms – Singular valuedecomposition – Pseudo inverse – Least square approximations – QR algorithm.

UNIT II SPECIAL FUNCTIONS 9Bessel's equation – Bessel function – Recurrence relations - Generating function andorthogonal property for Bessel functions of first kind – Fourier-Bessel expansion.

UNIT III RANDOM PROCESSES 9Classification – Stationary random processes – Ergodic process - Auto correlation – Crosscorrelations – Properties - Power spectral density.

UNIT IV DYNAMIC PROGRAMMING 9Bellman’s principle of optimality – Characteristics of the dynamic programming model –The recursive equation approach – Solution of discrete dynamic programming problem.

UNIT V CALCULUS OF VARIATIONS 9Euler’s equation – Functional dependent on first and higher order derivatives – Functionaldependent on functions of several independent variables -Isoperimetric Problems.

L: 45 + T: 15, TOTAL: 60 PERIODSREFERENCES:

1. Bronson, R., “Matrix Operations”, Schaum’s Outline Series, McGraw–Hill, NewYork

2. Gupta, A.S., “Calculus of Variations with Applications”, Prentice-Hall of India,New Delhi.

3. Dr.Venkataraman, M.K., “ Higher Mathematics for Engineering and Science”,National Publishing Company.1992.

4. Taha, H.A., “Operations Research – An Introduction”, Sixth Edition, Prentice-Hallof India, New Delhi.

5. Gupta, P.K. and Hira, D.S., “Operations Research”, S.Chand & Co. New Delhi.6. Peebles Jr., P.Z., “Probability, Random Variables and Random Signal Principles”,

McGraw-Hill Inc..

EC1503 ADVANCED DIGITAL SIGNAL PROCESSING 3 0 0 3

AIMTo introduce the students the various concepts and techniques used in advanced digitalsignal processing techniques.

OBJECTIVES To study the parametric methods for power spectrum estimation. To study adaptive filtering techniques using lms algorithm and to study the

applications of adaptive filtering. To study multirate signal processing fundamentals. To study the analysis of speech signals. To introduce the student to wavelet transforms.

UNIT I 9DISCRETE RANDOM SIGNAL PROCESSINGDiscrete Random Processes- Ensemble averages, stationary processes, Autocorrelation andAuto covariance matrices. Parseval's Theorem, Wiener-Khintchine Relation- PowerSpectral Density-Periodogram Spectral Factorization, Filtering random processes. LowPass Filtering of White Noise. Parameter estimation: Bias and consistency.

UNIT II 9SPECTRUM ESTIMATIONEstimation of spectra from finite duration signals, Non-Parametric Methods-CorrelationMethod , Periodogram Estimator, Performance Analysis of Estimators -Unbiased,Consistent Estimators- Modified periodogram, Bartlett and Welch methods, Blackman –Tukey method. Parametric Methods - AR, MA, ARMA model based spectral estimation.Parameter Estimation -Yule-Walker equations, solutions using Durbin’s algorithm

UNIT III 9WIENER FILTERS AND LINEAR PREDICTIONLinear prediction- Forward and backward predictions, Solutions of the Normal equations-Levinson-Durbin algorithms. Least mean squared error criterion -Wiener filter for filteringand prediction , FIR Wiener filter and Wiener IIR filters ,Discrete Kalman filter

UNIT IV 9ADAPTIVE FILTERSFIR adaptive filters -adaptive filter based on steepest descent method-Widrow-Hoff LMSadaptive algorithm, Normalized LMS. Adaptive channel equalization-Adaptive echocancellation-Adaptive noise cancellation- Adaptive recursive filters (IIR). RLS adaptivefilters-Exponentially weighted RLS-sliding window RLS.

UNIT V 9MULTIRATE DIGITAL SIGNAL PROCESSINGMathematical description of change of sampling rate - Interpolation and Decimation,Decimation by an integer factor - Interpolation by an integer factor, Sampling rate

conversion by a rational factor, Filter implementation for sampling rate conversion- directform FIR structures, Polyphase filter structures, time-variant structures. Multistageimplementation of multirate system. Application to sub band coding - Wavelet transformand filter bank implementation of wavelet expansion of signals.

TOTAL: 45 PERIODSREFERENCES:

1. Monson H.Hayes, Statistical Digital Signal Processing and Modeling, John Wileyand Sons, Inc.,Singapore, 2002.

2. John G. Proakis, Dimitris G.Manolakis, Digital Signal Processing PearsonEducation, 2002.

3. John G. Proakis et.al.,’Algorithms for Statistical Signal Processing’, PearsonEducation, 2002.

4. Dimitris G.Manolakis et.al.,’Statistical and adaptive signal Processing’, McGrawHill, Newyork,2000.

5. Rafael C. Gonzalez, Richard E.Woods, ‘Digital Image Processing’, PearsonEducation, Inc., Second Edition, 2004.( For Wavelet Transform Topic.

EE1501 ADVANCED DIGITAL SYSTEM DESIGN 3 0 0 3AIM

To do an advanced study of sequential circuit design, asynchronous sequential circuitdesign, fault diagnosis and testability algorithms, synchronous design using programmabledevices and system design using VHDL.

OBJECTIVES

To do a detailed study of sequential circuit design. To study the asynchronous sequential circuit design approaches. To study the fault diagnosis and testability algorithms in detail. To do the detailed study of synchronous design using programmable devices. To study the system design using VHDL.

UNIT I 9SEQUENTIAL CIRCUIT DESIGN

Analysis of Clocked Synchronous Sequential Networks (CSSN) Modeling of CSSN – StateStable Assignment and Reduction – Design of CSSN – Design of Iterative Circuits – ASMChart – ASM Realization.

UNIT II 9ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

Analysis of Asynchronous Sequential Circuit (ASC) – Flow Table Reduction – Races inASC – State Assignment – Problem and the Transition Table – Design of ASC – Static andDynamic Hazards – Essential Hazards – Data Synchronizers – Designing Vending MachineController – Mixed Operating Mode Asynchronous Circuits.

UNIT III 9FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS

Fault Table Method – Path Sensitization Method – Boolean Difference Method – KohaviAlgorithm – Tolerance Techniques – The Compact Algorithm – Practical PLA’s – Fault inPLA – Test Generation – Masking Cycle – DFT Schemes – Built-in Self Test.

UNIT IV 9SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES

EPROM to Realize a Sequential Circuit – Programmable Logic Devices – Designing aSynchronous Sequential Circuit using a GAL – EPROM – Realization State machine usingPLD – FPGA – Xilinx FPGA – Xilinx 2000 - Xilinx 3000

UNIT V 9SYSTEM DESIGN USING VHDL

VHDL Description of Combinational Circuits – Arrays – VHDL Operators – Compilationand Simulation of VHDL Code – Modeling using VHDL – Flip Flops – Registers –Counters – Sequential Machine – Combinational Logic Circuits - VHDL Code for – SerialAdder, Binary Multiplier – Binary Divider – complete Sequential Systems – Design of aSimple Microprocessor.


1. Donald G. Givone “Digital principles and Design” Tata McGraw Hill 2002.2. John M Yarbrough “Digital Logic applications and Design” Thomson Learning,

20013. Nripendra N Biswas “Logic Design Theory” Prentice Hall of India, 20014. Charles H. Roth Jr. “Digital System Design using VHDL” Thomson Learning, 1998.5. Charles H. Roth Jr. “Fundamentals of Logic design” Thomson Learning, 2004.6. Stephen Brown and Zvonk Vranesic “Fundamentals of Digital Logic with VHDL

Design” Tata McGraw Hill, 2002.7. Navabi.Z. “VHDL Analysis and Modeling of Digital Systems. McGraw

International, 19988. Parag K Lala, “Digital System design using PLD” BS Publications, 20039. Peter J Ashendem, “The Designers Guide to VHDL” Harcourt India Pvt Ltd, 200210. Mark Zwolinski, “Digital System Design with VHDL” Pearson Education, 200411. Skahill. K, “VHDL for Programmable Logic” Pearson education, 1996

EE1502 VLSI DESIGN 3 0 0 3

AIM

To do an advanced study of VLSI system component design techniques.

OBJECTIVES

To study the MOS transistor theory and process technology in detail. To do the detailed study of inverters and logic gates. To study the circuit characterization and performance estimation approaches in

detail. To do the detailed study of design of system components using VLSI techniques. To study the verilog hardware description language in detail.

UNIT I 9MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY.

NMOS and PMOS transistors, Threshold voltage- Body effect- Design equations- Secondorder effects. MOS models and small signal AC characteristics. Basic CMOS technology.

UNIT II 9INVERTERS AND LOGIC GATES.

NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient characteristics ,switching times, Super buffers, Driving large capacitance loads, CMOS logic structures ,Transmission gates, Static CMOS design, dynamic CMOS design.

UNIT III 9CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION

Resistance estimation, Capacitance estimation, Inductance, switching characteristics,transistor sizing, power dissipation and design margining. Charge sharing .Scaling.

UNIT IV 9VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICALDESIGN.Multiplexers, Decoders, comparators, priority encoders, Shift registers.Arithmetic circuits – Ripple carry adders, Carry look ahead adders, High-speed adders,Multipliers. Physical design – Delay modelling ,cross talk, floor planning, powerdistribution. Clock distribution. Basics of CMOS testing.

UNIT V 9VERILOG HARDWARE DESCRIPTION LANGUAGE

Overview of digital design with Verilog HDL, hierarchical modelling concepts, modulesand port definitions, gate level modelling, data flow modelling, behavioral modelling, task& functions, Test Bench.

TOTAL: 45 PERIODS

REFERENCES:

1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design,Pearson Education ASIA, 2nd edition, 2000.

2. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons,Inc., 2002.

3. Samir Palnitkar, “Verilog HDL”, Pearson Education, 2nd Edition, 2004.4. Eugene D. Fabricius, Introduction to VLSI Design McGraw Hill International

Editions, 1990.5. J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2nd Edition, 2001.6. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.7. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.

CS1501 ADVANCED COMPUTER ARCHITECTURE 3 0 0 3

AIM

To discuss the basic structure of a digital computer and to study in detail the organization ofthe Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O unit.OBJECTIVES:

To understand the evolution of computer architecture. To understand the state-of-the-art in computer architecture.

To understand the design challenges in building a system.

UNIT I PIPELINING AND ILP 11Fundamentals of Computer Design - Measuring and Reporting Performance - InstructionLevel Parallelism and Its Exploitation - Concepts and Challenges - Overcoming DataHazards with Dynamic Scheduling – Dynamic Branch Prediction - Speculation - MultipleIssue Processors – Case Studies.

UNIT II THREAD-LEVEL PARALLELISM 8Multi-threading – Multiprocessors - Centralized and Distributed Shared MemoryArchitectures – Cache Coherence Issues - Performance Issues – Synchronization Issues –Models of Memory Consistency - Interconnection Networks – Buses, Crossbar and Multi-Stage Switches – Multi-Core Processor Architectures - Case Study.

UNIT III SIMD AND GPU ARCHITECTURES 8SIMD Extensions for Multimedia – Graphics Processing Units – GPU ComputationalStructures – GPY ISA – GPU Memory Structures – Case Study.

UNIT IV MEMORY HIERARCHY DESIGN 9Introduction - Optimizations of Cache Performance - Memory Technology andOptimizations – Name Mapping Implementations - Virtual Memory and Virtual Machines -Design of Memory Hierarchies - Case Studies.

UNIT V WAREHOUSE-SCALE COMPUTERS 9Programming Models and Workloads – Storage Architectures – Physical Infrastructure –Cloud Infrastructure – Case Study

TOTAL: 45 PERIODSREFERENCES:1. John L. Hennessey and David A. Patterson, “Computer Architecture – A quantitativeapproach”, Morgan Kaufmann / Elsevier, Fifth edition, 2012.2. Richard Y. Kain, “Advanced Computer Architecture a Systems Design Approach”, PHI,2011.

EE1571 ELECTRONICS DESIGN LAB - I 0 1 2 2

Aim: To design systems using PIC microcontrollers, DSP processor, FPGA and to designdigital systems using VHDL and Verilog.

Objective: To design systems using PIC microcontroller To implement adaptive filters, periodogram and multistage multirate system in DSP

processor To model sequential digital system using VHDL & Verilog To design ALU using FPGA and to design systems using 16-bit Microprocessors

1. System design using PIC Microcontroller.2. Implementation of Adaptive Filters, periodogram and multistage multirate system in

DSP Processor3. Simulation of QMF using Simulation Packages4. Modeling of Sequential Digital system using VHDL.5. Modeling of Sequential Digital system using Verilog.6. Design and Implementation of ALU using FPGA.7. Simulation of NMOS and CMOS circuits using SPICE.8. System design using 16- bit Microprocessor.

TOTAL: 45 PERIODS





SEMESTER II

Sl.No Code No. Course TitleL T P C

THEORY

1. EE1503Analysis and Design of AnalogIntegrated Circuits

3 0 0 3

2. EE1504 Neural Networks & Applications 3 0 0 3

3.EE1505 Digital Control Engineering 3 0 0 3

4. EE1506 Advanced Embedded Systems 3 0 0 3

5.EC15A7

High Performance CommunicationNetworks

3 0 0 3

6. XX5E2 Elective II 3 0 0 3

PRACTICAL

7. EE1572 Electronic Design Lab II 0 1 2 2

Total18 1 2 20

EE1503 ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS3 0 0 3

AIM

To do an advanced study of analysis and design of integrated circuits, operationalamplifiers and multipliers.

OBJECTIVES

To study the models for integrated circuit active devices in detail. To do the detailed study of current sources, biasing circuits, voltage references and

output stages. To do the detailed study of analysis of operational amplifiers. To do the detailed study of analog multiplier and PLL circuits. To study the analog design with MOS technology in detail.

UNIT I 9MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES

Depletion region of a PN junction – large signal behavior of bipolar transistors- small signalmodel of bipolar transistor- large signal behavior of MOSFET- small signal model of theMOS transistors- short channel effects in MOS transistors – weak inversion in MOStransistors- substrate current flow in MOS transistor.

UNIT II 9CIRCUIT CONFIGURATION FOR LINEAR IC

Current sources, Analysis of difference amplifiers with active load using BJT and FET,supply and temperature independent biasing techniques, voltage references. Output stages:Emitter follower, source follower and Push pull output stages.

UNIT III 9OPERATIONAL AMPLIFIERS

Analysis of operational amplifiers circuit, slew rate model and high frequency analysis,Frequency response of integrated circuits: Single stage and multistage amplifiers,Operational amplifier noise

UNIT IV 9ANALOG MULTIPLIER AND PLL

Analysis of four quadrant and variable trans conductance multiplier, voltage controlledoscillator, closed loop analysis of PLL, Monolithic PLL design in integrated circuits:Sources of noise- Noise models of Integrated-circuit Components – Circuit NoiseCalculations – Equivalent Input Noise Generators – Noise Bandwidth – Noise Figure andNoise Temperature

UNIT V 9ANALOG DESIGN WITH MOS TECHNOLOGY

MOS Current Mirrors – Simple, Cascode, Wilson and Widlar current source – CMOS ClassAB output stages – Two stage MOS Operational Amplifiers, with Cascode, MOSTelescopic-Cascode Operational Amplifier – MOS Folded Cascode and MOS ActiveCascode Operational Amplifiers

TOTAL: 45 PERIODSREFERENCES

1. Gray, Meyer, Lewis, Hurst, “Analysis and design of Analog IC’s”, Fourth Edition,Willey International, 2002.

2. Behzad Razavi, “Principles of data conversion system design”, S.Chand andcompany ltd, 2000

3. Nandita Dasgupata, Amitava Dasgupta,”Semiconductor Devices, Modelling andTechnology”, Prentice Hall of India pvt. ltd, 2004.

4. Grebene, Bipolar and MOS Analog Integrated circuit design”, John Wiley &sons,Inc.,2003.

5. Phillip E.Allen Douglas R. Holberg, “CMOS Analog Circuit Design”, SecondEdition-Oxford University Press-2003

EE1504 NEURAL NETWORKS AND APPLICATIONS 3 0 0 3

AIM

To do an advanced study of basic learning algorithms, radial-basis function networksand support vector machines, committee machines and neural network applications.

OBJECTIVES

To study the basic learning algorithms in detail. To do the detailed study of radial-basis function networks and support vector

machines. To do the detailed study of committee machines and neurodynamic systems. To do the detailed study of attractor neural networks and Adaptive Resonance theory

approaches. To study about self-organizing maps and pulsed neuron models.

UNIT I 9BASIC LEARNING ALGORITHMS

Biological Neuron – Artificial Neural Model - Types of activation functions – Architecture:Feedforward and Feedback – Learning Process: Error Correction Learning –Memory BasedLearning – Hebbian Learning – Competitive Learning - Boltzman Learning – Supervisedand Unsupervised Learning – Learning Tasks: Pattern Space – Weight Space – PatternAssociation – Pattern Recognition – Function Approximation – Control – Filtering -Beamforming – Memory – Adaptation - Statistical Learning Theory – Single Layer

Perceptron – Perceptron Learning Algorithm – Perceptron Convergence Theorem – LeastMean Square Learning Algorithm – Multilayer Perceptron – Back Propagation Algorithm –XOR problem – Limitations of Back Propagation Algorithm.

UNIT II 9RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR MACHINES:RADIAL BASIS FUNCTION NETWORKS:

Cover’s Theorem on the Separability of Patterns - Exact Interpolator – RegularizationTheory – Generalized Radial Basis Function Networks - Learning in Radial Basis FunctionNetworks - Applications: XOR Problem – Image Classification.SUPPORT VECTOR MACHINES:Optimal Hyperplane for Linearly Separable Patterns and Nonseparable Patterns – SupportVector Machine for Pattern Recognition – XOR Problem - -insensitive Loss Function –Support Vector Machines for Nonlinear Regression

UNIT III 9COMMITTEE MACHINES:

Ensemble Averaging - Boosting – Associative Gaussian Mixture Model – HierarchicalMixture of Experts Model(HME) – Model Selection using a Standard Decision Tree – APriori and Postpriori Probabilities – Maximum Likelihood Estimation – Learning Strategiesfor the HME Model - EM Algorithm – Applications of EM Algorithm to HME ModelNEURODYNAMICS SYSTEMS:

Dynamical Systems – Attractors and Stability – Non-linear Dynamical Systems- LyapunovStability – Neurodynamical Systems – The Cohen-Grossberg Theorem.

UNIT IV 9ATTRACTOR NEURAL NETWORKS:

Associative Learning – Attractor Neural Network Associative Memory – LinearAssociative Memory – Hopfield Network – Content Addressable Memory – StrangeAttractors and Chaos - Error Performance of Hopfield Networks - Applications of HopfieldNetworks – Simulated Annealing – Boltzmann Machine – Bidirectional AssociativeMemory – BAM Stability Analysis – Error Correction in BAMs - Memory Annihilation ofStructured Maps in BAMS – Continuous BAMs – Adaptive BAMs – ApplicationsADAPTIVE RESONANCE THEORY:

Noise-Saturation Dilemma - Solving Noise-Saturation Dilemma – Recurrent On-center –Off-surround Networks – Building Blocks of Adaptive Resonance – Substrate of ResonanceStructural Details of Resonance Model – Adaptive Resonance Theory – Applications

UNIT V 9SELF ORGANISING MAPS:

Self-organizing Map – Maximal Eigenvector Filtering – Sanger’s Rule – GeneralizedLearning Law – Competitive Learning - Vector Quantization – Mexican Hat Networks -Self-organizing Feature Maps – Applications

PULSED NEURON MODELS:Spiking Neuron Model – Integrate-and-Fire Neurons – Conductance Based Models –Computing with Spiking Neurons.


1. Satish Kumar, “Neural Networks: A Classroom Approach”, Tata McGraw-HillPublishing Company Limited, New Delhi, 2004.

2. Simon Haykin, “Neural Networks: A Comprehensive Foundation”, 2ed., AddisonWesley Longman (Singapore) Private Limited, Delhi, 2001.

3. Martin T.Hagan, Howard B. Demuth, and Mark Beale, “Neural Network Design”,Thomson Learning, New Delhi, 2003.

4. James A. Freeman and David M. Skapura, “Neural Networks Algorithms,Applications, and Programming Techniques, Pearson Education (Singapore) PrivateLimited, Delhi, 2003.

EE1505 DIGITAL CONTROL ENGINEERING 3 0 0 3AIM

To do an advanced study of digital controllers, sampled data control systems, digitalcontrol algorithms.

OBJECTIVES

To study the digital PID controllers in detail. To do the detailed study of signal processing in digital control. To do the detailed study of modeling and analysis of sampled data control system. To do the detailed study of design of digital control algorithms. To study about the practical aspects of digital control algorithms.

UNIT I 9

Review of frequency and time response analysis and specifications of control systems, needfor controllers, continues time compensations, continues time PI, PD, PID controllers,digital PID controllers.

UNIT II 9SIGNAL PROCESSING IN DIGITAL CONTROL

Sampling, time and frequency domain description, aliasing, hold operation, mathematicalmodel of sample and hold, zero and first order hold, factors limiting the choice of samplingrate, reconstruction.

UNIT III 9MODELING AND ANALYSIS OF SAMPLED DATA CONTROL SYSTEM

Difference equation description, Z-transform method of description, pulse transfer function,time and frequency response of discrete time control systems, stability of digital control

systems, Jury's stability test, state variable concepts, first companion, second companion,Jordan canonical models, discrete state variable models, elementary principles.

UNIT IV 9DESIGN OF DIGITAL CONTROL ALGORITHMS

Review of principle of compensator design, Z-plane specifications, digital compensatordesign using frequency response plots, discrete integrator, discrete differentiator,development of digital PID controller, transfer function, design in the Z-plane.

UNIT V 9PRACTICAL ASPECTS OF DIGITAL CONTROL ALGORITHMS

Algorithm development of PID control algorithms, software implementation,implementation using microprocessors and microcontrollers, finite word length effects,choice of data acquisition systems, micro controller based temperature control systems,micro controller based motor speed control systems.

TOTAL: 45 PERIODS

REFERENCES

1. M.Gopal, "Digital Control and Static Variable Methods", Tata McGraw Hill, NewDelhi, 1997.

2. John J. D'Azzo, "Constantive Houpios, Linear Control System Analysis and Design",Mc Graw Hill, 1995.

3. Kenneth J. Ayala, "The 8051 Microcontroller- Architecture, Programming andApplications", Penram International, 2nd Edition, 1996.

EE1506 ADVANCED EMBEDDED SYSTEMS 3 0 0 3

AIM

To do an advanced study of embedded architecture, embedded processor and computingplatform, networks, real time characteristics and system design techniques.

OBJECTIVES

To study the architecture and design of embedded systems with examples. To do the detailed study of ARM processor architecture and design with examples. To study the architecture of Distributed Embedded Architecture in detail with

example. To do the detailed study of real time characteristic approaches. To study the Design Methodologies in detail.

UNIT I 9EMBEDDED ARCHITECTURE

Embedded Computers, Characteristics of Embedded Computing Applications, Challenges in

Embedded Computing system design, Embedded system design process- Requirements,Specification, Architectural Design, Designing Hardware and Software Components,System Integration, Formalism for System Design- Structural Description, BehavioralDescription, Design Example: Model Train Controller

UNIT II 9EMBEDDED PROCESSOR AND COMPUTING PLATFORM

ARM processor- processor and memory organization, Data operations, Flow of Control,SHARC processor- Memory organization, Data operations, Flow of Control, parallelismwith instructions, CPU Bus configuration, ARM Bus, SHARC Bus, Memory devices,Input/output devices, Component interfacing, designing with microprocessor developmentand debugging, Design Example : Alarm Clock.

UNIT III 9NETWORKS

Distributed Embedded Architecture- Hardware and Software Architectures, Networks forembedded systems- I2C, CAN Bus, SHARC link pports, Ethernet, Myrinet, Internet,Network-Based design- Communication Analysis, system performance Analysis, Hardwareplatform design, Allocation and scheduling, Design Example: Elevator Controller.

UNIT IV 9REAL-TIME CHARACTERISTICS

Clock driven Approach, weighted round robin Approach, Priority driven Approach,Dynamic Versus Static systems, effective release times and deadlines, Optimality of theEarliest deadline first (EDF) algorithm, challenges in validating timing constraints inpriority driven systems, Off-line Versus On-line scheduling.

UNIT V 9SYSTEM DESIGN TECHNIQUES

Design Methodologies, Requirement Analysis, Specification, System Analysis andArchitecture Design, Quality Assurance, Design Example: Telephone PBX- SystemArchitecture, Ink jet printer- Hardware Design and Software Design, Personal DigitalAssistants, Set-top Boxes.

TOTAL: 45

REFERENCES

1. Wayne Wolf, Computers as Components: Principles of Embedded Computing SystemDesign, Morgan Kaufman Publishers, 2001.

2. Jane.W.S. Liu Real-Time systems, Pearson Education Asia, 20003. C. M. Krishna and K. G. Shin , Real-Time Systems, ,McGraw-Hill, 19974. Frank Vahid and Tony Givargi Embedded System Design: A Unified Hardware/Software

Introduction, s, John Wiley & Sons, 2000.

EC15A7 HIGH PERFORMANCE COMMUNICATION NETWORKS 3 0 0 3

PREREQUISITE: Computer Networks.

AIMTo study some fundamental concepts in wireless networks.

OBJECTIVES

To understand physical and wireless MAC layer alternatives techniques. To learn planning and operation of wireless networks. To study various wireless LAN and WAN concepts. To understand WPAN and geo-location systems.

UNIT I 9PACKET SWITCHED NETWORKSOSI and IP models, Ethernet (IEEE 802.3), Token ring (IEEE 802.5), Wireless LAN (IEEE802.11) FDDI, DQDB, SMDS: Internetworking with SMDS

UNIT II 9ISDN AND BROADBAND ISDNISDN - overview, interfaces and functions, Layers and services - Signaling System 7 (SS7) -Broadband ISDN architecture and Protocols.

UNIT III 9ATM AND FRAME RELAYATM: Main features-addressing, signaling and routing, ATM header structure-adaptationlayer, management and control, ATM switching and transmission. Frame Relay: Protocolsand services, Congestion control

UNIT IV 9ADVANCED NETWORK ARCHITECTUREIP forwarding architectures overlay model, Multi Protocol Label Switching (MPLS),integrated services in the Internet, Resource Reservation Protocol (RSVP), Differentiatedservices

UNIT V 9BLUE TOOTH TECHNOLOGYThe Blue tooth module-Protocol stack Part I: Antennas, Radio interface, Base band, TheLink controller, Audio, The Link Manager, The Host controller interface; The Blue toothmodule-Protocol stack Part I: Logical link control and adaptation protocol, RFCOMM,Service discovery protocol, Wireless access protocol, Telephony control protocol.

TOTAL: 45 PERIODS

REFERENCES1. William Stallings, “ISDN and Broadband ISDN with Frame Relay and ATM”, 4th

edition, Pearson education Asia, 2002.2. Leon Gracia, Widjaja, “Communication networks ", Tata McGraw-Hill, New Delhi,

2000.3. Jennifer Bray and Charles F.Sturman, “Blue Tooth” Pearson education Asia, 2001.4. Sumit Kasera, Pankaj Sethi, “ATM Networks ", Tata McGraw-Hill, New Delhi, 2000.5. Rainer Handel, Manfred N.Huber and Stefan Schroder ,”ATM Networks”,3rd edition,

Pearson education asia, 2002.6. Jean Walrand and Pravin varaiya ,”High Performance Communication networks”,2nd

edition, Harcourt and Morgan Kauffman,London,2000.7. William Stallings, “High-speed Networks and Internets”, 2nd edition, Pearson

education Asia, 2003.8. Behrouz A. Forouzan, “Data Communication and Networking”, 5th Edition, McGraw-

Hill Higher Education, 2012

EE1572 ELECTRONIC DESIGN LAB II 0 1 2 2

1. System design using PLL2. System design using CPLD3. Alarm clock using embedded micro controller4. Model train controller using embedded micro controller5. Elevator controller using embedded micro controller6. Simulation of Non adaptive Digital Control System using MAT LAB control system

toolbox7. Simulation of Adaptive Digital Control System using MAT LAB control system

toolbox

TOTAL: 45 PERIODS





SEMESTER III

Sl.No. Code No. Course Title L T P C

THEORY

1. XX5E3 Elective III 3 0 0 3

2. XX5E4 Elective IV 3 0 0 3

3. XX5E5 Elective V 3 0 0 3

PRACTICAL

4. EE1573 Embedded System Lab 0 1 2 2

5. EE15P1 Project Work - Phase I 0 0 12 6

TOTAL 9 1 14 17

EE1573 EMBEDDED SYSTEM LAB 0 1 2 2

1. Micro controller 8051/8031 & Flash controller programminga) Simple application programs with kit and through assemblerb) Data flash with erase, verify, fusing through ATMEL and INTEL tools.

2. Testing RTOS Environment and System Programming.a) Keil Toolsb) RTOS System Solutions with Tornado tools.

3. Complex Programmable Logic Devices and Device Programming with VHDL fitterand Cool runner

a) Warp tools-Cypress-Active HDL Simulator & Galaxy-VHDL, FSM modelsb) Mixed signal handling.

4. Third party design toolsa) Mentor Graphicsb) Cadence.

5. VLSI designing with various Tools and Design methodologiesa) AT40K FPGA series-synthesis-design-simulation of application programs.b) Xilinx EDA design tools-device programming –PROM programming.c) ALTERA and Mentor graphics-IC design tools.

6. Embedded DSP based System Designing.a) Code compressor studio for embedded DSP using Texas tool kit.b) Analog DSP tool kit.

7. IPCORE usage in VOIP Through SoC2 toolsa) Cypress PsoC designing Toolsb) SoPC designing Tools

8. FPSLIC synthesis, Designing and Testing and BLUE TOOTH wirelessCommunication Designing.

a) ATMEL FPSLIC toolsb) CYPRESS BLUE TOOTH tools.

TOTAL: 45 PERIODS





SEMESTER IV

Sl.No Code No. Course Title L T P C

PRACTICAL

1. EE15P5 Project Work - Phase II 0 0 36 18





LIST OF ELECTIVES

Sl.No

CodeNo. Course Title L T P C

1. EE15A1 Robotics 3 0 0 3

2. EE15A2Electromagnetic Interference andCompatibility in System Design

3 0 0 3

3. EE15A3 Advanced Microprocessor and Microcontroller 3 0 0 3

4. EE15A4 Low Power VLSI 3 0 0 3

5. EE15A5 Digital signal processors 3 0 0 3

6. EE15A6 Embedded Analog Interfacing 3 0 0 3

ELECTIVES

EE15A1 ROBOTICS 3 0 0 3

PREREQUISITE: Artificial Intelligence and Expert System

AIM

Robots are slowly and steadily replacing human beings in many fields. The aim ofthis course is to introduce the students into this area so that they could use the same whenthey enter the industries.

OBJECTIVE

The course has been so designed to give the students an overall view of the mechanicalcomponents

The mathematics associated with the same. Actuators and sensors necessary for the functioning of the robot.

UNIT I 9INTRODUCTION TO ROBOTICSMotion - Potential Function, Road maps, Cell decomposition and Sensor and sensorplanning. Kinematics. Forward and Inverse Kinematics - Transformation matrix and DHtransformation. Inverse Kinematics - Geometric methods and Algebraic methods. Non-Holonomic constraints.

UNIT II 9COMPUTER VISIONProjection - Optics, Projection on the Image Plane and Radiometry. Image Processing -Connectivity, Images-Gray Scale and Binary Images, Blob Filling,Thresholding, Histogram. Convolution - Digital Convolution and Filtering and MaskingTechniques. Edge Detection - Mono and Stereo Vision.

UNIT III 9SENSORS AND SENSING DEVICESIntroduction to various types of sensor. Resistive sensors. Range sensors - Ladar (laserdistance and ranging), Sonar, Radar and Infra-red. Introduction to sensing - Light sensing,Heat sensing, Touch sensing and Position sensing.

UNIT IV 9ARTIFICIAL INTELLIGENCEUniform Search strategies - Breadth first, Depth first, Depth limited, Iterative and deepeningdepth first search and Bidirectional search. The A* algorithm. Planning - State-SpacePlanning , Plan-Space Planning, Graphplan/SatPlan and their Comparison, Multi-agentplanning 1, and Multi-agent planning 2, Probabilistic Reasoning - Bayesian Networks,Decision Trees and Bayes net inference .

UNIT V 9

INTEGRATION TO ROBOTBuilding of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors forobstacle detection - AI algorithms for path finding and decision making

TOTAL: 45 PERIODS

REFERENCES

1. Duda, Hart and Stork, Pattern Recognition. Wiley-Interscience, 2000.2. Mallot, Computational Vision: Information Processing in Perception and Visual

Behavior. Cambridge, MA: MIT Press, 2000.3. Artificial Intelligence-A Modern Approach By Stuart Russell and Peter Norvig, Pearson

Education Series in Artificial Intelligence, 20044. Fundamentals of Robotics, Analysis and control By Robert Schilling and Craig, Hall of

India Private Limied, New Delhi, 2003.5. Computer Vision, A modern Approach By Forsyth and Ponce, Person Education, 2003.

EE15A2 ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY INSYSTEM DESIGN 3 0 0 3

PREREQUISITE: Electromagnetic Theory

AIM

To do an advanced study of electromagnetic interference and compatibility in systemdesign.

OBJECTIVES

To study the EMI/EMC concepts and definitions in detail. To do the detailed study of EMI coupling. To study the EMI/EMC standards and measurements in detail. To do the detailed study of EMI control techniques. To study the EMC design of PCB in detail.

UNIT I 9EMI ENVIRONMENTEMI/EMC concepts and definitions, Sources of EMI, conducted and radiated EMI,Transient EMI, Time domain Vs Frequency domain EMI, Units of measurement parameters,Emission and immunity concepts, ESD.

UNIT II 9EMI COUPLING PRINCIPLESConducted, Radiated and Transient Coupling, Common Impedance Ground Coupling,Radiated Common Mode and Ground Loop Coupling, Radiated Differential ModeCoupling, Near Field Cable to Cable Coupling, Power Mains and Power Supply coupling.

UNIT III 9EMI/EMC STANDARDS AND MEASUREMENTSCivilian standards - FCC,CISPR,IEC,EN,Military standards - MIL STD 461D/462, EMITest Instruments /Systems, EMI Shielded Chamber, Open Area Test Site, TEM Cell,Sensors/Injectors/Couplers, Test beds for ESD and EFT, Military Test Method andProcedures (462).

UNIT IV 9EMI CONTROL TECHNIQUESShielding, Filtering, Grounding, Bonding, Isolation Transformer, Transient Suppressors,Cable Routing, Signal Control, Component Selection and Mounting.

UNIT V 9EMC DESIGN OF PCBsPCB Traces Cross Talk, Impedance Control, Power Distribution Decoupling, Zoning,Motherboard Designs and Propagation Delay Performance Models.

TOTAL: 45 PERIODS

REFERENCES

1. Henry W.Ott, "Noise Reduction Techniques in Electronic Systems", John Wiley andSons, NewYork. 1988.

2. C.R.Paul, “Introduction to Electromagnetic Compatibility” , John Wiley and Sons,Inc, 1992

3. V.P.Kodali, "Engineering EMC Principles, Measurements and Technologies", IEEEPress, 1996.

4. Bernhard Keiser, "Principles of Electromagnetic Compatibility", Artech house, 3rdEd, 1986.

EE15A3 ADVANCED MICROPROCESSORS AND MICRO CONTROLLERS3 0 0 3

PREREQUISITE: Microprocessor and micro controllers.

AIMTo do an advanced study of microprocessor, Pentium, ARM architectures and

MOTOROLA 68HC11 and PIC micro controller architecture.

OBJECTIVES To do a detailed study of microprocessor architecture. To study the Pentium processor in detail. To study the ARM processor in detail. To do the detailed study of MOTOROLA 68HC11 micro controller. To do the detailed study of PIC micro controller.

UNIT I 9MICROPROCESSOR ARCHITECTUREInstruction set – Data formats – Instruction formats – Addressing modes – Memoryhierarchy – register file – Cache – Virtual memory and paging – Segmentation – Pipelining– The instruction pipeline – pipeline hazards – Instruction level parallelism – reducedinstruction set – Computer principles – RISC versus CISC – RISC properties – RISCevaluation – On-chip register files versus cache evaluation .

UNIT II 9HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUMThe software model – functional description – CPU pin descriptions – RISC concepts –bus operations – Super scalar architecture – pipe lining – Branch prediction – Theinstruction and caches – Floating point unit –protected mode operation – Segmentation –paging – Protection – multitasking – Exception and interrupts – Input /Output – Virtual8086 model – Interrupt processing -Instruction types – Addressing modes – Processor flags– Instruction set -programming the Pentium processor.

UNIT III 9HIGH PERFORMANCE RISC ARCHITECTURE: ARMThe ARM architecture – ARM assembly language program – ARM organization andimplementation – The ARM instruction set - The thumb instruction set – ARM CPU cores.

UNIT IV 9MOTOROLA 68HC11 MICROCONTROLLERSInstructions and addressing modes – operating modes – Hardware reset – Interruptsystem – Parallel I/O ports – Flags – Real time clock – Programmable timer – pulseaccumulator – serial communication interface – A/D converter – hardware expansion –Assembly language ProgrammingUNIT V 9PIC MICRO CONTROLLERCPU architecture – Instruction set - Interrupts – Timers – I/O port expansion –I2C bus forperipheral chip access – A/D converter – UART

TOTAL: 45 PERIODS

REFERENCES:1. Daniel Tabak , ‘’ Advanced Microprocessors” McGraw Hill.Inc., 19952. James L. Antonakos, “The Pentium Microprocessor ‘’ Pearson Education, 1997.3. Steve Furber, ‘’ ARM System –On –Chip architecture “Addison Wesley, 2000.4. Gene .H.Miller.” Micro Computer Engineering,” Pearson Education, 2003.5. John .B.Peatman, “Design with PIC Microcontroller, Prentice hall, 1997.6. James L.Antonakos,” An Introduction to the Intel family of Microprocessors ‘’

Pearson Education 1999.7. Barry.B.Breg,” The Intel Microprocessors Architecture , Programming and

Interfacing “, PHI, 2002.8. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first

reprints 2001.

EE15A4 LOW POWER VLSI 3 0 0 3

UNIT – I 9Low Power Design, An Over View: Introduction to low- voltage low power design,limitations, Silicon-on-Insulator.MOS/BiCMOS PROCESSES : Bi CMOS processes, Integration and Isolationconsiderations, Integrated Analog/Digital CMOS Process.

UNIT – II 9Low-Voltage/Low Power CMOS/ BiCMOS Processes: Deep submicron processes, SOI,CMOS, lateral BJT on SOI, future trends and directions of CMOS/BiCMOS processes.

UNIT – III 9Device Behavior And Modeling: Advanced MOSFET models, limitations of MOSFETmodels, Bipolar models.Analytical and Experimental characterization of sub-half micron MOS devices, MOSFET ina Hybrid mode environment.

UNIT – IV 9Cmos And Bi-CMOS Logic Gates: Conventional CMOS and BiCMOS logic gates.Performance evaluationLow- Voltage Low Power Logic Circuits: Comparison of advanced BiCMOS Digitalcircuits. ESD-free Bi CMOS, Digital circuit operation and comparative Evaluation.

UNIT – V 9Low Power Latches And Flip Flops: Evolution of Latches and Flip flops-quality measuresfor latches and Flip flops, Design perspective.

TOTAL: 45 PERIODSTEXT BOOKS:

1. CMOS/BiCMOS ULSI low voltage, low power by Yeo Rofail/ Gohl(3 Authors) -Pearson Education Asia 1st Indian reprint, 2002

REFERENCES:1. Digital Integrated circuits, J.Rabaey PH. N.J 19962. CMOS Digital ICs sung-mo Kang and yusuf leblebici 3rd edition TMH20033. VLSI DSP systems, Parhi, John Wiley & sons, 2003 (chapter 17)4. IEEE Trans Electron Devices, IEEE J.Solid State Circuits, and other National and

International Conferences and Symposia

EE15A5 DIGITAL SIGNAL PROCESSORS 3 0 0 3

PREREQUISITE: Microprocessors and microcontrollers

AIMTo do an advanced study of TMS320F2407 Digital signal processor.

OBJECTIVES To do a detailed study of TMS320F2407 architecture. To study the addressing modes and instruction set in detail. To study the system configuration and interrupts in detail. To do the detailed study of digital input & output and ADC. To study the event manager and PWM generation in detail.

UNIT I 9INTRODUCTION TO TMS320F2407

Introduction to 2407 – Architectural Overview – Architecture Summary –C24XCPU Internal Bus Structure-Memory-CPU-Program Control-Memory And IO Spaces –Overview of Memory and IO Spaces - Program Memory – Data Memory – Global DataMemory - I/O Space – Central Processing Unit Input Scaling - Multiplier – CentralArithmetic logic – Auxiliary Register Arithmetic Unit – Status Registers - ProgramControl – Program Address Generation – Pipeline Operation – Branches, Calls and returns -Conditional Branches, Calls – Repeating a single instruction

UNIT II 9ADDRESSING MODES AND INSTRUCTION SET

Addressing Modes – Immediate addressing modes – Direct Addressing Mode –Indirect Addressing Mode – Instruction Set - Instruction Set Summary - Accumulator andALU Instruction - Auxiliary Register Instruction – TREG, PREG and Multiply Instructions- Branch Instructions - Control Instructions - IO and Memory Instructions-How to useInstruction Descriptions-syntax-operands-opcode-Execution-status bits-Description-words-cycles-study of instructions- ADD-SUB-MAC-BACC-BCND-SETC-CLRC-SPLK-IN-OUT

UNIT III 9SYSTEM CONFIGURATION AND INTERRUPTS

System Configuration - Configuration Registers –System Control And StatusRegisters – Interrupts- Interrupt priority and Vectors - Peripheral Interrupt ExpansionController – Interrupt operation sequence –CPU Interrupt Registers -Peripheral Interruptregisters – Clocks and Low Power Modes – Phased Locked Loop – Watchdog TimerClock – Low Power Modes

UNIT IV 9DIGITAL INPUT & OUTPUT AND ADC

Digital Input and Output Interface – Introduction – IO Implementation - IO MuxControl Registers - Data and Direction Control Registers – Analog To Digital Converter –

Features of ADC - ADC overview – ADC Input Channel Selection – ADC Trigger SourceInput -ADC Clock pre scalar - Calibration of ADC - ADC Control Registers

UNIT V 9EVENT MANAGER & PWM GENERATION

Event Manager Functional Blocks – Event Manager Registers - General Purpose Timer -Compare Units –PWM circuits associated with compare unit – Programmable Dead bandunit- Output Control unit - PWM Wave form generation with compare units - RegisterSetup for PWM generation – Asymmetric Waveform generation – Symmetric PWMwaveform Generation

TOTAL: 45 PERIODS

REFERENCE

1. Texas Instruments Inc., TMS320F24x DSP Controller Reference Guide – CPU andInstruction Set - SPRU160C or www.ti.com

2. Texas Instruments Inc., TMS320F240x DSP Controller Reference Guide –Systems and Peripherals – SPRU357B or www.ti.com

3. Hamid. A Toliyat, Steven G. Campbell, DSP Based Electro-Mechanical MotionControl – CRC Press 2004, ISBN: 0-8493-1918-8

EE51A6 EMBEDDED ANALOG INTERFACING 3 0 0 3

PREREQUISITE: Embedded Systems

AIMTo do an advanced study of measurement system design, analog to digital converters,sensors and peripherals, output control methods and micro controller interfacing

OBJECTIVES To do a detailed study of measurement system design. To study the analog to digital converters in detail. To study the sensors and peripherals in detail. To do the detailed study of output control methods. To study in detail about the micro controller interfacing.

UNIT I 9MEASUREMENT SYSTEM DESIGNCharacteristics of Instrumentation – Measurement accuracy – Measurement standards -Dynamic Range – Calibration – Bandwidth – Digital interfacing advantages

UNIT II 9ANALOG-TO-DIGITAL CONVERTERSTypes of ADCs - ADC Comparison - Sample and Hold - ADC Types - Flash ADC -Successive Approximation ADC - Dual-Slope (Integrating) ADC - Sigma-Delta ADC -

Microprocessor Interfacing - Clocked Interfaces - Serial Interfaces – Integrated ADCEmbedded Controllers

UNIT III 9SENSORS & PERIPHERALSTemperature Sensors - Optical Sensors – CCDs - Magnetic Sensors - Motion/AccelerationSensors - Strain Gauges - Solenoids – Heaters – Coolers – LEDs – DACs - DigitalPotentiometers - Analog Switches - Stepper Motors - DC Motors

UNIT IV 9OUTPUT CONTROL METHODSMeasuring Period versus Frequency - Voltage-to-Frequency Converters - Open-LoopControl - Negative Feedback and Control - Microprocessor-Based Systems- On-Off Control- Proportional Control - Proportional, Integral, Derivative Control - Motor Control -Predictive Control - Measuring and Analyzing Control Loops

UNIT V 9MICROCONTROLLER INTERFACINGStandard Interfaces - IEEE 1451.2 - 4–20 ma Current Loop – Fieldbus - MicrocontrollerSupply and Reference - Resistor Networks - Multiple Input Control -AC Control - VoltageMonitors and Supervisory Circuits - Driving Bipolar Transistors/ MOSFET- ReadingNegative Voltages – PWM based control

TOTAL: 45 PERIODS

REFERENCE1. Analog Interfacing to Embedded Microprocessor Systems by Stuart R. Ball.2. The measurement, Instrumentation, & sensors Handbook by John G. Webster.3. Microcontroller-Based Temperature Monitoring and Control by by Dogan Ibrahim.

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NOORUL ISLAM CENTRE FOR HIGHER EDUCATION - … · NOORUL ISLAM CENTRE FOR HIGHER EDUCATION NOORUL ISLAM ... EE1502 VLSI Design 3 0 0 ... Taha, H.A., “Operations Research – An