Nonalloyed GaAs metal-semiconductor ®eld e�ecttransistor

Ching-Ting Lee*, Jen-Hou Huang, Chang-Da Tsai

Institute of Optical Sciences, National Central University, Chung-Li, Taiwan, ROC

Received 14 July 1999; accepted 18 August 1999

Abstract

A novel GaAs metal-semiconductor ®eld-e�ect transistor (MESFET) with Al0.25Ga0.75As/GaAs multiquantumbarrier (MQB) bu�er layer and narrow band InAs/graded InGaAs capping layer was demonstrated. The MQBbu�er layer can improve the sidegating e�ect and isolation. The capping layer can perform nonalloy ohmic contactwith Ti/Pt/Au metals. Furthermore, the Ti/Pt/Au metals directly contact with GaAs active channel layer can work

as Schottky barrier. For the fabrication of this novel MESFET, the thermal alloy and alignment processes can beavoided. # 2000 Elsevier Science Ltd. All rights reserved.

1. Introduction

By evaporating an Al Schottky-barrier gate directly

onto an n-type GaAs channel, the ®rst metal-semicon-

ductor ®eld-e�ect transistor (MESFET) was demon-strated [1]. The GaAs MESFETs have played a key

role for many microwave and high-speed applications

in analog and digital systems. For the conventional

photolithographic fabrication process of MESFETs,

source and drain ohmic metals were deposited and

alloyed ®rst, and then gate pattern between source and

drain regions was prudently aligned in the photoresist.

After the channel was recessed, the gate Schottky

metal was then evaporated, and the excess metal was

removed by using lift-o� technique [2]. The associated

performance and yield for MESFETs would be

restricted by the critical fabrication process of short

gate aligned de®ning between a narrow spacing of the

source and drain regions. To improve the fabrication

process, a self-aligned gate technology was developed

[3,4]. Furthermore, to reduce the parasitic interaction

or sidegating e�ect and provide better isolation, a mul-tiple quantum barrier (MQB) structure was grown

between the active channel and bu�er layers [5,6].

However, the surface roughness, decomposition and

interdi�usion of MQB structure would be induced

during the thermal alloy process. Therefore, the nonu-

niform currents ¯ow and degraded microstructures

could be resulted due to the formation of spiky inter-

face. To avoid thermal alloy process, many useful non-alloyed ohmic structures and metals on compound

semiconductors have been studied, recently [7±9]. The

low contact resistance and thermal stability for nonal-

loyed Ti/Pt/Au ohmic contacts with n-InAs/graded

InGaAs/n-GaAs channel structures were demonstrated

[10]. It is worth noting that the Ti/Pt/Au metals are

conventional Schottky contact for GaAs material. It

would be a promising process by depositing Ti/Pt/Aumetallization system on the source and drain regions

as ohmic contact and on the gate region as Schottky

contact, simultaneously. The fabrication process not

only can be simpli®ed but the thermal alloy process

can be avoided. In this paper, we studied a novel

Solid-State Electronics 44 (2000) 143±146

0038-1101/00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved.

PII: S0038-1101(99 )00222-1

* Corresponding author. Tel.: +886-3-426-3914; fax: +886-

3-425-2897.

E-mail address: t260003@cc.ncu.edu.tw (C.-T. Lee).

MESFET structure with n-InAs/graded InGaAs cap-ping layers for nonalloyed ohmic contact and MQB

structure for reducing of parasitic interaction and side-gating e�ect.

2. Device structure and fabrication

Fig. 1 shows the cross section of the novel MESFETdevice. The epitaxial layers were grown on a (100)-

oriented semi-insulating GaAs substrate by a solid-source molecular beam epitaxial system. A typicallayer structure consists of a 500 nm-thick undopedGaAs bu�er layer, followed by a 56.32 nm-thick

undoped Al0.25Ga0.75As/GaAs multiple quantum bar-rier (MQB) structure. The Si-doped GaAs active chan-nel layer with thickness of 200 nm and carrier

concentration of 3 � 1017 cmÿ3 was grown in sequence.To employ narrow bandgap material for nonalloyedohmic contact, a heavily Si-doped InAs capping layer

(20 nm, 5 � 1018 cmÿ3) was grown on a heavily Si-doped graded InxGa1ÿxAs (referred to as gradedInGaAs) layer (60 nm, 5 � 1018 cmÿ3). The compo-sition of the graded InxGa1ÿxAs is gradually changed

from x � 0 (at the GaAs active channel layer interface)to x � 1 (at the InAs capping layer interface) within athickness of 60 nm. The purpose of the graded

InGaAs interlayer grown between InAs and GaAslayers is to release strain and dislocations inducedfrom the layer lattice mismatch between InAs and

GaAs [11]. The MQB structure is periodically stackedby pairs of undoped GaAs well and undopedAl0.25Ga0.75As barrier. The MQB structure was con-

structed with three stacks by (60; 12, 10, 1; 7, 8, 3; 5,7, 6) with 199 monolayers (about 56.32 nm) as shownin Fig. 2(a). The thick Al0.25Ga0.75As barrier with 60monolayers is on the top layer of the MQB and con-

tacts with the GaAs active channel layer to evade low-energy electron tunneling. Using transfer matrixmethod [12] and adopting reported parameters [13],

the electron re¯ectivity against its energy normalizedby the potential barrier height U0 is shown in Fig.2(b). The e�ective potential barrier height is estimated

to be 3U0, where U0 � 178 meV is the potential barrierheight between GaAs and Al0.25Ga0.75As layers.The novel MESFETs was fabricated using a stan-

dard photolithography and lift-o� technique. Mesa

regions (100 � 100 mm2) were de®ned by using chemi-cal solution of H2SO4:H2O2:H2O=1:8:80 to etch thewafer down to the GaAs bu�er layer. To perform gate

recess region (3 � 100 mm2), the same chemical sol-ution was used to etch the central part of the mesaregion down to the GaAs active channel layer.

Following the gate recess etching process, the patternsof source, drain and gate regions were de®ned sequen-tially. The gate with length of 1mm and width of

Fig. 1. The structure of nonalloyed GaAs MESFET.

Fig. 2. (a) The schematic structure of the MQB bu�er layer

and (b) the calculated electron wave re¯ectivity for the MQB

structure.

C.-T. Lee et al. / Solid-State Electronics 44 (2000) 143±146144

100 mm was located between drain and source regionsand put on the gate recess region. The separation betweendrain and source regions was 5 mm. The drain and source

regions were put on the heavily Si-doped InAs cappinglayer. Prior to metal deposition, the native oxidation wasremoved by chemical solution of NH4OH:H2O=1:10.Metal system of Ti/Pt/Au (50/100/300 nm) was then

deposited on the sample using an electron-beam evap-orator under high vacuum (2 � 10ÿ6 Torr). Accordingto our previous report of the Ti/Pt/Au directly con-

tacted on InAs/graded InGaAs, the speci®c contact re-

sistance of 9.8 � 10ÿ7 O cm2 of the ohmic contact was

achieved [10]. Furthermore, the Ti/Pt/Au metal systemcontacted with GaAs material is a conventionalSchottky contact [14,15].

3. Experimental results

The MESFETs performances were measured using

an HP4145B semiconductor parameter analyzer. Thedrain-source current (Ids) ± drain-source voltage (Vds)characteristics are shown in Fig. 3. The MESFET is

completely pinched o� at gate-source voltage (Vgs) ofÿ2 V. According to this phenomenon, the MQB bu�erlayer performed a very good isolation and carrier con-®nement between the GaAs active channel layer and

the MQB bu�er layer.To investigate the gate performance, the measured

gate-source current Igs as a function of the gate-source

voltage Vgs is shown in Fig. 4. It can be seen that theIgs biased at Vgs=ÿ10 V is about 7.5 mA. We ®nd thatthis MESFET can operate more than Vgs=ÿ20 V,

since the Igs is still less than 10 mA and very slowlychanging with bias. To study the thermal stability, thefabricated MESFETs are thermally treated at various

temperatures for 30 min. The temperature dependenceof Igs on Vgs is shown in Fig. 5. The Igs biased atVgs=ÿ10 V is 10, 34, 45 and 55 mA at 100, 200, 300and 4008C, respectively. In view of the point of the

gate leakage current, this MESFET can operate atleast above 3008C. Furthermore, we can ®nd that thegate leakage is degraded at 4008C. The gate leakage

degradation would be attributed to the formation ofTiAs at 4008C. The TiAs layer is apparently a poor

Fig. 3. The dependence of drain-source current Ids on drain-

source voltage Vds.

Fig. 4. The gate-source current Igs as a function of gate-source

bias voltage Vgs.

Fig. 5. The gate-source current Igs as a function of gate-source

bias voltage Vgs at various thermal temperatures for 30 min.

C.-T. Lee et al. / Solid-State Electronics 44 (2000) 143±146 145

barrier for Ga and Pt di�usion [15]. Therefore, theSchottky barrier height would be reduced due to the

formation of PtAs2 and Pt3Ga compositions. In ad-dition, the speci®c contact resistance of source anddrain ohmic performances was deteriorated owing to

the decomposition of the graded InGaAs layer andInAs capping layer at 4008C [16,17]. The surface leak-age between gate and source regions would be

increased due to the decomposition of InAs andgraded InGaAs layers. Besides, the reduction of theSchottky barrier height between Ti/Pt/Au metals and

GaAs active channel layer of the MESFETs thermallytreated at 4008C would be considered as anotherreason for the signi®cant increase in Igs.

4. Summary

A novel MESFET without thermal annealing pro-cess and gate alignment was reported in this paper.The metal system of Ti/Pt/Au was deposited and used

as ohmic contact for source and drain and Schottkycontact for gate, simultaneously. The DC character-istics are measured to demonstrate the novel

MESFETs performance. Besides, the associated gateleakage performance and thermal reliability are stu-died. The gate leakage current would be degraded bythe reduction of Schottky barrier height and the de-

composition of InAs capping layer and graded InGaAslayer. The novel MESFET structure was ®rst reportedhere in the literature. The purpose of this study is to

demonstrate a MESFET con®guration with simpli®edfabrication process and without alloy process. Thisnovel structure and fabrication process would be useful

for MESFET-based integrated circuit. High speed andhigh performances can be expected by using wellknown short gate and special design rule.

Acknowledgements

The authors wish to thank the support from theNational Science Council of the Republic of Chinaunder the grant NSC 88-2218-E-008-015.

References

[1] Mead CA. Proc IEEE 1966;54:307±8.

[2] Chou YC, Lee CT, Chen CD, Chou KC. Electron Lett

1987;23:7±8.

[3] Drukier I. Microwave J 1980;23:59±64.

[4] Singh HP, Sadler RA, Irvine JA, Gorder GE. IEEE

Trans Electron Devices 1989;36:240±9.

[5] Lee CT, Tsai CD, Wang CY, Shiao HP, Nee TE, Shen

JN. Appl Phys Lett 1995;67:2046±8.

[6] Lee CT. IEEE Trans Electron Devices 1998;45:2083±5.

[7] Woodall JM, Freeouf JL, Pettit GM, Jackson TJ,

Kirchner PJ. Vac Sci Technol 1981;19:626±7.

[8] Stareev G, Kunzel HJ. Appl Phys 1993;74:7592±5.

[9] Shiraishi Y, Furuhata N, Okamoto AJ. Appl Phys

1994;76:5099±110.

[10] Lee CT, Jaw KL, Tsai CD. Solid-State Electron

1998;42:871±5.

[11] Peng CK, Ji G, Kumar NS, Morkoc H. Appl Phys Lett

1988;53:900±1.

[12] Jonsson B, Eng ST. IEEE J Quantum Electron

1990;26:2025±35.

[13] Adachi SJ. Appl Phys 1985;58:R1±R29.

[14] Kwok SPJ. Vac Sci Technol B 1986;4:1383±91.

[15] Sinka AK, Smith TE, Read MH, Poate JM. Solid-State

Electron 1976;19:489±92.

[16] Lee CT, Shiao HP, Chou YC. Solid-State Electron

1995;38:1529±31.

[17] Wu JW, Chang CY, Lin KC, Chang EY, Chen JS, Lee

CT. J Electron Mater 1995;24:79±82.

C.-T. Lee et al. / Solid-State Electronics 44 (2000) 143±146146