1841 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

Noise Performance of Si/Sil_,Ge, FET’s A. F. M. Anwar, Kuo-Wei Liu, and Vijay P. Kesan, Member, IEEE

Abstract-Noise characteristics are evaluated for SiGdSi based n-channel MODFET’s and p-channel MOSFET’s. The analysis is based on a self-consistent solution of Schriidinger and Poisson’s equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFET’s behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temper- ature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FET’s.

I. INTRODUCTION HE introduction of sophisticated epitaxial growth tech- T niques have enabled us to successfully grow strained

layer material system like SiGe [ll-[7]. Efforts using this material system have already resulted in the fabrication of SiGe HBTs [I], [2], p-channel MOSFET’s [3]-[5] and n- channel MODFET’s [6], [7 ] . Moreover, different optoelec- tronic devices are also realized.

The use of this system has prompted studies in the areas of transport, devices modeling, and device performance as compared to the existing Si technology. The performance of this class of devices in some cases is comparable to that of AlGaAs/GaAs material system. Device performance may be evaluated from different aspects and one such aspect is the determination of noise.

In this paper, for the first time, the noise behavior of SiGe/Si based n-channel MODFET’s and p-channel MOS- E T ’ S are reported. The calculations are based on a more realistic velocity-electric field characteristics [8], [9] and a self- consistent solution of Schrodinger and Poisson’s equation [ lo]. The predicted noise parameters are presented. The results may aid in the design and optimization of SiGe/Si based devices.

11. MODEL The modeling of noise proceeds by first quantifying the

quantum well (QW) and identifying a velocity-electric field characteristic [SI, [9]. Instead of using a two-line [ I l l or an exponential [I21 approximation the following Ud - &

Manuscript received July 29, 1994; revised April 17, 1995. The review of this paper was arranged by Associate Editor J. R. Hauser. The work was supported in part by the University of Connecticut Research Foundation under Grant 441204 and by the State of Connecticut under Grant 5-26-94 DED(CI1).

A. F. M. Anwar and K.-W. Liu are with the Department of Electrical and Systems Engineering, The University of Connecticut, Storrs, CT 06269-3 157 USA.

V. P. Kesan was with the IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is currently with Pennie & Edmonds, Washington, D.C. 20006 USA

IEEE Log Number 9413957.

characteristic is used in this calculation [8], [9]:

where 71, is the saturation velocity, po is the low field mobility, and E is the applied electric field along the channel. This Ud - & characteristic makes the dc current-voltage and small signal parameters analytic in nature and provides a better agreement with results obtained from Monte Carlo simulation. The QW behavior is introduced in the calculation of noise by recognizing the functional dependence of the average distance of the electron cloud x,,, the position of the Fermi level EF on the 2DEG concentration n, and are expressed in the following functional forms [lo]:

za,(ns(x)) = a - b . ln(.s(.)) (A) (2) EF(.s(x)) = + Y.1.(%(.)) (.VI (3)

where z represents any point x in the channel and a , b , EF(O) and y are defined in Table I. Only heavy holes are used in the simulation of the quantum well formed in the valence band in p-channel devices. The effective channel width Ad can be calculated as Ad = x,, . E S ~ G ~ / E S ~ . F represents the permittivity of respective layers. The effective channel width Ad is calculated and modified along the channel depending on n,(x). The channel is narrower at the source (x = 0 ) and widens as one move towards the drain region (x = L g ) . In all previous noise models [ l l l , [15], [16], [18], [19], only the first two-subbands related to the calculation of 2DEG concentration and distribution and an effective channel width Ad is assumed to be a constant around 80 8, at room temperature. In addition to the functional relationship of x,, and EF with two-dimensional electron gas (2DEG) concentration n,, the definition of reduced potential s, p and w for source, drain, and any point x in the channel are used to calculate device dc current-voltage characteristic [ 131 and small-signal parameters [ 131, [ 141, such as transconductance gmr drain resistance r d , and gate-source capacitance Cgs. The unity current gain cut-off frequency fT can be obtained by using the relationship, f~ = g T n / ( 2 . 7r . Cgs) . The present analytical calculations of dc analysis [lo], [13] are able to explain all experimental data reported by experimenters [3], [6] for this class of devices.

The analysis of noise is based on the identification of the different noise sources that are present in the channel [9], [17], [20], namely, a) Johnson Noise in the ohmic region, b) noise associated with spontaneous generation of dipole layers in the saturation region, c) gate noise due to elementary voltage fluctuations in the channel, and d) induced gate noise in the saturation region.

0018-9383/95$04.00 0 1995 IEEE

1842 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

TABLE I THE QUA“ WELL PARAMETERS FOR

SiGelSi BASED n- AND p-CHANNEL FET’s

The analysis starts by developing a modified expression for the mean square noise voltage at the drain region

. cosh’ (-) -2 4 . IC .T’Af T . L2

2 . deff . [PO + P o + p6 +%] (4)

with

- P6 = - y.S.p2 ’ [cos-’ ( n . P ) - cosp1 (-)I n

where the noise temperature parameter 6 is assumed to be 2, n is assumed to be 10, and Esat = n . Eo, which represent the use of an improved Ud-E characteristic ((1)). In the saturation region, Vd is assumed to be 99.99% (or better) of vs when E reaches Esat. The presence of y and Ad in deff reflect the use of a self-consistent solution to model the QW ((2) and (3)). Puce1 et al. [ l l ] formulated vzl using only two drain noise coefficients, namely, Po and P6. However, the above two drain coeffcients have to be modified for it to be useful in HEMT analysis. Ando et al. [20] in his treatment to study HEMT’s used a form similar to (4). The four drain noise coefficients in this treatment, include the effect of a nonlinear U$& characteristics and the parameters obtained from a self- consistent solution of Schrodinger and Poisson’s quations for the QW formed in a SiGe/Si/SiGe heterointerface. The drain voltage fluctuation due to diffusion noise in the saturation region

n s . Jm d 2 - x

x = exp (-) T ’ L2 2 . deff

where A f is the frequency range, T is the operating temper- ature in degree Kelvin, k is the Boltzmann constant, Ids is

the saturation drain current [9], Dh = 30, is the high field diffusion constant, L2 is the length of the saturation region. d,R = di + dd + Ad, di is the spacer layer thickness and dd is the width of the donor layer. In this work, X is calculated based on Ad, whereas, in the previous treatment [l 11, [15], [16], [18]-[20] an effective channel width Ad is assumed to be a constant at room temperature.

Considering the fluctuation of the gate current due to the capacitive coupling between the channel and the gate, we obtain the mean square Johnson noise induced gate current in the region I (ohmic region) as

-;2 4.IC.T.Af .w2.d , f f .L? T . L2 - .cosh’ (-) 291 -

2 . E . r i . v i .p3 2 . deff . [Ro +& + R6 + E & ] (6)

where L1 is the length of the linear region

Ro = lVTl. (IC’ - p .p )2 [ p 3 . (2n2 - 1 ) + s . [s’ . (n2 + 1 ) - 3.n2 .p’]

3 + P . (IC’ - P . P )

p4 .(n2 - 1 ) + s 2 . [s” (n2 + 1) - 2 .n2 . p 2 ] 2

2 . p 5 . ( 2 n 2 - 3 ) + s3. [3s2. (n2 + 1 ) - 1 5 . n 2 . p 2 ] 15 + P

1 + - 1 . (n’ + 1 ) . ( s 2 - p 2 ) 2

+ 2 . P . ( k / - P .PI p 3 . (2n2 - 1) + s . [ s2 . (n2 + 1) - 3.n2 . p 2 ]

3

1 + -(s2 P2 - p 2 ) . [s2 . (n2 + 1 ) + (I - n2) .p’] 4

n2 + 1 ‘ . -

nL . p a

+ p2 . 1 2 . (n2 + 1)3,2

ANWAR et al.: NOISE PERFORMANCE OF Si/Sil_,Ge, FET'S 1843

s . d m + \/s2 . (n2 + 1) - 722 . p2

p . m + p

p 3 . [ J s 2 . ( n 2 + 1 ) - n 2 . p 2 - p ] n2 + 1 1 + p 2 .

and (see equations at the bottom of this page). The induced gate noise in the saturation region is written as

:2 - 64. q . I d , . d& . A f . w2 . LI . K"

6 292 - ~5 . ~2 . U," . 2 2 . A d 2 . p2 .

(7)

To facilitate the evaluation of noise performance of devices, dimensionless noise coefficients are introduced: -

and

where is the equivalent noise voltage at the drain region and 3 is the equivalent noise induced gate current. P I , P2 and R I , R2 are of the same form as P and R, but with subscripts 1 and 2 on different noise sources in the region I (ohmic region) and region I1 (saturation region), respectively. The correlation coefficient, C, between different noise sources can be written as

where C1 = C 1 1 J m and C2 = C 2 2 J m .

C11 is the gate-drain noise current correlation coefficient in the ohmic region

- -

where

. [p3 . ( 2 . n2 - 1) - 3 ' n2 . s . p2 + s2 . (n2 + l)]

- c0s-l (-)) n + ~ P . P 3 m dFTT

s . d m + Js . (n2 + 1) - n2. p2

p . m + p

C22 is the gate-drain noise current correlation coefficient in the saturation region and is suggested to be 1 [9], [20]. It should be pointed out that Puce1 et al. [ 111 model is based only upon the use of PO, P6, Ro, Rg. SO and Sa, which are modified to reflect the use of a self-consistent calculation and

1844 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 42, NO. 10, OCTOBER 1995

a nonlinear wd-E characteristic to be useful in the present analysis. Moreover, in the present model additional terms are required (PO, P6, Ro , R6, SO and %) to properly model noise in HEMT’s.

The minimum noise figure, Fmin [9] and the minimum noise temperature, Tmin [ 171

_ _ _ _ _

where gn is the noise conductance

( i ) . [P + R - 2 . C . m] (14)

and Zs,opt and T, are optimum external source impedance and noise resistance, respectively [9], [ 171, 2, = R, + j X , = R, + is the correlation impedance, R, and R, are the source and drain impedance and Ri = L,(v, . C,,), is the gate charging resistance. L, represents the length of the gate. In several cases, the device is not matched for the minimum noise figure and the mismatch effect on the noise figure can be expressed as [18]

R, + Rz - ( j / W C , , ) . ( P . R. (1 - CZ))/(P+ R - 2. c . m) ,

where 2, = R, + j X , the input termination, or source, impedance. Equation (15) shows that the mismatch effect is less sensitive for low values of the noise conductance g,.

111. RESULTS AND DISCUSSION

In this section the noise performance of n-channel MOD- FET’s and p-channel MOSFET’s are presented. The analysis is based on devices reported by Kesan et al. [3] and Ismail et al. [6]. The device parameters used in this analysis are listed in Table TI. In Fig. 1, the calculated minimum noise figures, Fmin

(dB), are plotted as a function of the drain-source current for n-channel MODFET’s and p-channel MOSFET’s with tem- perature as a parameter. The calculations are performed at 15 GHz. It is observed that the minimum noise figure of n-channel MODFET’s are smaller than that of p-channel MOSFET’s. The results may be explained by using (12) through (14). From (14), the quadratic term ( f / f ~ ) ’ dominates the behavior of g,, except when f approaches f ~ , then gm dominates. N- channel devices have a larger gm as compared to p-channel FET’s, however, their behavior is similar as a function of drain current. On the other hand, f~ for p-channel devices peaks at a lower drain current and then gradually decreases, as depicted in Fig. 2. At lower drain current an increasing f~ and gm produces a lower gn which is turn results in lower Fmin (Tmin). At higher drain current, gn increases producing a higher Fmil,. f~ for n-channel devices initially increases with drain current and then saturates (see Fig. 2). Moreover, f T for n-channel devices are much greater than p-channel FETs. This explains the lower Fmin for n-channel devices as compared to p-channel FET’s. Also to be noted is the behavior of the correlation coefficient C (( 10)). For n-channel MODFET’s C is near unity at higher drain current producing a lower gn

TABLE I1 THE DEVICE PARAMETERS FOR SiGelSi FET’s

I Devices I 300K n- I 7°K n- I 300K D- I 82 P- I 0.25

I PI I [GI i [31- i Reference 0.25 I 0.25 I

,- ,’ ‘IFrequency = 15 GHz ’ , ’ , ‘ ,- 300K ,,’ ,’ ,’ 8 Z K ”

” ”

/’ ,” ,’ ,’

/’ ,’ ’ ,

p-channel SiGe/Si MOSFETs

\\.--.1. n-channel SiGe/Si MODFETs

7 7 K 01 - I I I I

0 20 40

Drain Current (mA)

60

Fig. 1. Minimum noise figures &in are plotted as a function of drain current for SiGelSi n-channel MODFET’s (solid lines) and p-channel MOSFET’s (dashed lines) with temperature as a parameter (the drain-source current in p-channel FET’s is scaled up by 5).

hence a lower Fmin. However, for p-channel FET’s the gate and drain noise are strongly correlated (C near 1) and less correlated (C > 1) at low and high drain current, respectively.

In Fig. 3, &in is plotted as a function of frequency for n- and p-channel FET’s at various temperatures. The p- channel MOSFET is biased V,, = -2.5 V (-1.64 V) and V,, = -2.5 V at 300 K (82 K). The n-channel MODFET is biased V,, = -0.65 V (-0.53 V) and V,, = 3.0 V at 300 K (77 K). Fmin increases with frequency for both families of FET’s. A higher f~ for n-channel MODFET’s results in a lower Fmin. We have observed that &, in decreases with increasing QW width. This decrease in not so significant at the high frequency end. At 60 GHz a well width increase from 50-300 8, may result in a reduction of Fmin by 1.5 dB for n- channel FET’s. Fmin is less sensitive QW width variation at cryogenic temperatures.

In Fig. 4, minimum noise temperature Tmin is plotted as a function of the gate length and frequency for an n-channel de- vice at room temperature. Tmin increases with increasing gate length and frequency. Tmin is lower at cryogenic temperatures

I

ANWAR er al.: NOISE PERFORMANCE OF Si/Sil_,Ge, E T ’ S

loo

L_ n-channel MODFETs

..-.. p-channel MOSFETs

8 2 K

300K, p-channel SiGe/Si MOSFETs

15 GHz, Vd = -2.5 V

1 I I I I 1

0 15 30 45 60 75

I , , (mA)

Fig. 2. The calculated unity-gain cutoff frequency f~ is plotted as a function of drain-source current Ids for the n-channel E T ’ S (solid lines) at 300 and 77 K, and for the p-channel FET’s (dashed lines) (the drain-source current in p-channel E T ’ S is scaled up by 5 ) at 300 and 82 K, respectively.

8

6

h

m a v

E 4 3 E

2

C

- n-channel MODFETs p-channel MOSFETs . . . . . . .

0

QW Width 2 0 0 A 300K ;

:: 8 2 K . . . . . . . .

..

-I I , 1 10

Frequency (GHz) 100

Fig. 3. n-channel E T ’ S (solid lines) and p-channel FET’s (dashed lines).

Minimum noise figure Fmin is plotted as a function of frequency for

for both n- and p-channel FET’s. The behavior of Tmin can again be explained in terms of the noise conductance gn, as shown in Fig. 5. gn increases with the gate length and is a weak function of QW width at cryogenic temperature. Moreover, gn for p-channel FET’s are order of magnitude greater than that for n-channel FET’s. For example, gn for p-channel FET’s at 300 K is 60 mS, whereas, for n-channel FET’s it is 0.03 mS. A smaller gn implies that the noise figure is less sensitive to the degradation caused by nonoptimized input termination. For a given drain-source voltage, the thermal noise induced by the ohmic region will increase for increasing gate length (also increasing the length of ohmic region). Therefore, noise will

1845

300K. n-channel SiCe/Si MODFET

Tmin (I

12717

8479

4242

0.150 1

Fig. 4. length and frequency for an n-channel FET at room temperature.

Minimum noise temperature Tmin is plotted as a function of the gate

80

60 h

v1 E tac v

40

20

50A ,/

I

0.0 0.2 0.4 0.6 0.8 1.0 Gate Length (um)

Fig. 5. Noise conductance y,, is plotted as a function of gate length for a p-channel FET at room temperature. The solid, dashed, and dot-dashed lines represent devices with 50, 150 8,, and 300 8, QW width.

increase by increasing gate length for both n- and p-channel devices.

In Fig. 6, Fmin is plotted as a function of the doped epilayer thickness ( d d ) and frequency for an n-channel FET at 77 K. As observed, a range of dd exists (75 A - 200 A) where Fmin is a minimum (Fmin < 1.0 dB at 60 GHz for 75 A 5 dd 5 200 A). The reduction in Fn,in is prominent at higher frequencies. For p-channel devices Fmin increases slightly with increasing d d

(29 dB at 75 A to 30 dB at 450 A at 60 GHz). Another interesting point to note is that though Fmin is very small for a certain range of dd for n-channel FET’s the maximum value of Fmin (34 dB at 60 GHz for dd = 450 A) is greater than the maximum Fmin for p-channel FET’s (30 dB at 60 GHz for

1846 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 10, OCTOBER 1995

77K, n-channel SiGe/Si MODFET 1

Fmin ((

38.72

25.81

12.91

0.01 4 350 250 150 50

0

Doped Epilayer Thickness (A)

Fig. 6. and frequency for an n-channel FET at 77 K.

Minimum noise figure is plotted as a function of epilayer thickness

dd = 450 A). This may be due to smaller variation of Ids in p-channel FETs as compared to n-channel devices (see Fig. 1).

IV. CONCLUSION We report the noise performances of the SiGe based n-

channel MODFET and p-channel MOSFET devices. The pre- dictions of the minimum noise figure, noise temperature, noise resistance, and optimum source impedance are reported for these devices. A method of optimizing noise performance of the devices has been suggested based on the epitaxial layer thickness. The calculated values of the noise parameters over a range of frequency can be used to estimate the performance of the several elements in the noise equivalent circuit which could be helpful for the design of the low noise circuits.

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[2] J. C. Sturm, E. J. Prinz, and C. W. Magee, “Graded-base Si/%, -,Ge,/Si heterojunction bipolar transistors grown by rapid thermal chemical vapor deposition with near-ideal electrical characteristics,’’ IEEE Electron Device Lett., vol. 12, no. 6, pp. 303-305, June 1991.

[3] V. P. Kesan, S. Subbanna, P. J. Restle, and M. J. Tejwanl, “High performance 0.25 p m p-MOSFET’s with silicon-germanium channel for 300 and 77 K operation,” in IEDM 91, 1991, pp. 2.2.1-2.2.4.

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[8] A. N. Khondker and A. F. M. Anwar, “Approximate analytic current- voltage calculation for MODFET’s,” IEEE Trans. Electron Devices, vol. 37, pp. 314-317, 1990.

[9] A. F. M. Anwar and K.-W. Liu, “Noise properties of AIGaAs/GaAs MODFET’s,” IEEE. Trans. Electron Devices, vol. 40, no. 6, pp. 1174-1 176, June 1993.

[lo] A. F. M. Anwar, K.-W. Liu, and R. D. Carroll, “An envelope func- tion description of the quantum well formed in strain layer SiGelSi MODFET’s,” J. Appl. Phys., vol. 74, no. 3, pp. 2064-2066, Aug. 1993.

[ l l ] R. A. Pucel et al., “Signal and noise properties of Gallium Arsenide microwave field-effect transistors,” Advances Electron, Electron Phys.,

[12] C.-S. Chang and H. R. Fetterman, “An analytic model for HEMT’s using velocity-field dependence,” IEEE Trans. Electron Devices, vol. ED-34, no. 7, pp. 1456-1462, 1987.

[I31 K.-W. Liu, A. F. M. Anwar, and V. P. Kesan, “An analytical model for current-voltage characteristics and DC small-signal parameters for Si/Sil-,Ge, FETs,” Solid-state Electron., vol. 37, no. 8, pp. 1570-1572, Aug. 1994.

[I41 K.-W. Liu and A. F. M. Anwar, “A self-consistent calculation of the small-signal parameters for AlGaAdGaAs and AlGaAs/InGaAs/GaAs HEMTs,” Solid-state Electron., vol. 37, no. I , pp. 51-54, Jan. 1994.

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A. F. M. Anwar, for a photograph and biography, see p. 590 of the April 1995 issue of this TRANSACTIONS.

Kuo-Wei Liu, for a photograph and biography, see p. 590 of the April 1995 issue of this TRANSACTIONS.

Vijay P. Kesan (S’86-M’8&M’89) was born in Bombay, India, on October 8, 1962. He received the B.S. degree in electrical engineering with highest honors from the University of Mysore, India, in 1984, and the M.S. and Ph.D. degrees in electri- cal and computer engineering from the University of Texas, Austin, in 1986 and 1989, respectively. For his doctoral work, he designed and fabricated quantum well devices for microwave oscillator ap- plications.

From 1989 to 1993, he was a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, in the Exploratory Device and Matenals Technology Group working on Si/SiGe-based matenals and devices. He is currently with Pennie & Edmonds, Washington, D.C., pursuing opportunities in business and science and technology-related law.