NHNG LU V THI GIAN (TIMING) VI THIT K CN BN DNG VHDLy l hng dn v chc nng nh thi (timing) trong phn mm Alteras Quartus II c m t nh th no trong thit k c bn vi ngn ng m t phn cng VHDL. Ti liu trnh by v phn tch nhng tham s nh thi khc nhau v gii thch nhng rng buc, hn ch c trng ca chc nng nh thi nh th no c th thit lp bi ngi s dng. Ni dung: Mch in v d Bo co phn tch thi gian Xc nh nhng rng buc thi gian M phng thi gian

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Phn mm Quartus II a ra m-un Timing Analyzer c chc nng thc hin phn tch cn k thi gian tr ca mch c bin dch thi hnh trn mt chip FPGA. Hng dn ny ni v cc kiu thc hin phn tch v ch ra nhng iu kin nh thi ring bit c th c thit lp bi ngi s dng. Ch cho ngi c quen thuc vi thao tc c bn ca phn mm Quartus II, ging nh c th bit t mt bi gii thiu. Vi hng dn ny, ngi c s bit v: Tham s c nh gi bi Timing Analyzer Thit lp gi tr mong mun ca tham s thi gian S dng m phng thi gian Nhng hiu qu thi gian c ch ra trong v d di y vi hng dn s dng phn mm Quartus II phin bn 9.0, nhng vi nhng phin bn khc ca phn mm vn c th s dng c. 1. Mch in v d Vn thi gian v cng quan trng trong mch, mch gm nhng ng truyn di xuyn sut c kh nng kt hp phn t logic vi b m ti u vo v u ra ca nhng ng truyn . Nh trong v d, chng ta s s dng b cng/tr hin th trn hnh 1. N c th cng, tr, v cng dn n-bit s s dng cch biu din s b 2. Hai u vo u tin l A= an-1an-2...a0 v B = bn-1bn-2...b0, v cng ra u tin Z= zn-1zn-2...z0. Cng vo khc l Addsub iu khin tn hiu khi Addsub=0 th thc hin php ton Z = A + B v Z = A - B khi AddSub =1. Cng vo iu khin th hai, Sel c s dng chn cch thc hot ng ca b cng. Nu Sel = 0, thc hin Z = A B, nhng nu Sel = 1, th B c cng thm hoc tr i t gi tr Z hin ti. Nu gi tr ca kt qu cng hoc tr trong thut ton b trn, mt cng ra, Overflow s bo hiu. Ni mt cch n gin hn vi nhng tn hiu u vo khng ng b, chng ta np vo flip-flop trn bin dng ca xung nhp. Khi , u vo A v B s c np trn b m Areg v Breg, trong khi Sel v AddSub s c np vo flip-flops SelR v AddSubR, ring tng cng. Mch cng/tr t kt qu trong thanh ghi Zreg.

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Hnh 1: Mch cng tr Mch yu cu c m t bng m VHDL trong Hnh 2. Trong v d ny, chng ta s dng mch 16-bit bng cch thit lp n = 16. Thc hin mch theo cc bc: To mt d n tn addersubtractor. a vo file addersubtractor.vhd, tng ng trong Hnh 2, trong d n. thch hp thit b, tp ny c cung cp trong th mc DE2_tutorials\design_file, cha trong CD-ROM i cng bng mch DE2 v cng c th tm thy trn trang web Alteras DE2. Chn thit b Cyclone II EP2C35F672C6 thch hp vi chip FPGA trn bng mch Alteras DE2. Hon thnh thit k. 3

LIBRARY ieee ; USE ieee.std_logic_1164.all ; Top-level module ENTITY addersubtractor IS GENERIC ( n : INTEGER := 16 ) ; PORT (A, B : IN STD_LOGIC_VECTOR(n1 DOWNTO 0) ; Clock, Reset, Sel, AddSub : IN STD_LOGIC ; Z : BUFFER STD_LOGIC_VECTOR(n1 DOWNTO 0) ; Overflow : OUT STD_LOGIC ) ; END addersubtractor ; ARCHITECTURE Behavior OF addersubtractor IS SIGNAL G, H, M, Areg, Breg, Zreg, AddSubR_n : STD_LOGIC_VECTOR(n-1 DOWNTO 0) ; SIGNAL SelR, AddSubR, carryout, over_flow : STD_LOGIC ; COMPONENT mux2to1 GENERIC ( k : INTEGER := 8 ) ; PORT ( V, W : IN STD_LOGIC_VECTOR(k-1 DOWNTO 0) ; Selm : IN STD_LOGIC ; F : OUT STD_LOGIC_VECTOR(k-1 DOWNTO 0) ) ; END COMPONENT ; COMPONENT adderk GENERIC ( k : INTEGER := 8 ) ; PORT (carryin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(k-1 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(k-1 DOWNTO 0) ; carryout : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN PROCESS ( Reset, Clock ) BEGIN IF Reset = 1 THEN Areg 0); Breg 0); Zreg 0); SelR