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New trends in silicon technology G. Casse 5 th Summer School on Intelligent signal processing for FrontIEr research and Industry (INFIERI) - 12-26 May 2019, Huazhong University of Science and Technology in Wuhan, China CMM Centre for Materials and Microsystems Abstract : Modern detector science and technology has originated from High Energy Physics experiment needs in the 80’s of the past century, based on the achievement and knowledge of the silicon industry of the time. The first segmented array of diodes (a microstrip sensor) was developed to track vertices at the NA11 experiment at the SPS accelerator at CERN (Geneva, CH). During the following years, detector technology developed into a special branch of the huge silicon technology enterprise that has been arguably the biggest contributor to the evolution of most of the economical, social and scientific activities of mankind. If, and how, detector technology for science has kept the pace with the spectacular speed of evolution of mainstream silicon technology (namely, the microelectronics industry) is the object of this lecture, that will also point out the special requirements of detectors for science and how these can be linked to modern microelectronics trends.

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Page 1: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

New trends in silicon technologyG. Casse

5th Summer School on Intelligent signal processing for FrontIEr research and Industry(INFIERI) - 12-26 May 2019, Huazhong University of Science and Technology in

Wuhan, China

CMMCentre for Materials and Microsystems

Abstract:

Modern detector science and technology has originated from High Energy Physics experiment needs in the ‘80’s of the past

century, based on the achievement and knowledge of the silicon industry of the time. The first segmented array of diodes (a

microstrip sensor) was developed to track vertices at the NA11 experiment at the SPS accelerator at CERN (Geneva, CH).

During the following years, detector technology developed into a special branch of the huge silicon technology enterprise that

has been arguably the biggest contributor to the evolution of most of the economical, social and scientific activities of

mankind. If, and how, detector technology for science has kept the pace with the spectacular speed of evolution of mainstream

silicon technology (namely, the microelectronics industry) is the object of this lecture, that will also point out the special

requirements of detectors for science and how these can be linked to modern microelectronics trends.

Page 2: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

OUTLINE:

• The revolutionary impact of silicon detectors in HEP• Detectors and microelectronics, a powerful synergy• Evolution of silicon sensors and electronics: overcoming

every challenge, to date• Modern microelectronics trends: too fast forward for

sensors?

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 2

Page 3: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 3

Collider physics requirementsRequired performance for general purpose

particle physics detectors:

• full solid angle coverage

• accurate momentum and/or energy measurement

• identification of all particles

• no dead time

• Vertices identification

Page 4: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 4

Technologies for HEP detectors

Three major families:

• Gaseous detectors: sensing ionisation in gas (mip charge ~ 90

e/ion pairs cm-1)

• Solid state detectors (mip charge ~ 40 to 160 e/h pairs µm-1)

• Scintillating detectors (scintillating light detected by photon

detectors)

Page 5: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 5

Silicon for HEP detectorsSilicon:

Widely available

For Minimum Ionising Particles: ~ 40 to 160 e/h pairs µm-1

Fast signal formation

Small feature size (high granularity)

Wide band

semiconductors:

for operating at non-cryo

temperatures.

Page 6: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 6

Silicon:

Tipically 100-500 µm thick segmented arrays (µ-strips) or

matrices (pixels) of silicon diodes are the sensitive part of

a detector system.

Silicon detectors

Page 7: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 7

Silicon detectors

Digital readout

Analogue amplifiers

A complete detector is made of:

Diodes (reverse biased)

Page 8: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 8

Vertex identification, key to collider physics. Needs for track reconstruction (late ‘80’s): high resolution, low mass (minimise multiple Coulomb scattering). NA11 (1978 – 1988), fixed target experiment: first silicon micro-strip sensors inserted in 1983. Electronics ‘’remote’’ and ‘’discrete’’.

Vertex identification in Collider Physics

Example:

Mean decay length Bs ( 1.5 ps):

in Bs-frame: c 450 m

in lab frame c = few mm!

Ds ( ~0.5 ps):

in Ds-frame: c 150 m

in lab frame c = few mm!

(lower mass more relativistic) 24 mm

36

mm

Page 9: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 9

ASIC’s for silicon detector readout: 1988 (UA2 at the CERN/SPS): first collider experiment with silicon detectors with ASIC read-out, namely the AMPLEX, 16 channel, 3 μm Feature Size (S) CMOS chip for read-out and signal multiplexing ( E. Heijne, P. Jarron).

The Spectacular success of Silicon detectors

Page 10: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 10

Silicon detector systems have many ingredients, but a crucial element is that the improvement of silicon detectors is linked to the evolution of CMOS technology.

The Spectacular success of Silicon detectors

Page 11: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 11

UA2

The Spectacular success of Silicon detectors

A virtuous interaction between technology and experiment needs: technology improvements allow better physics performance and experiment requirements push on the technology.BUT: CMOS technology evolution is driven by motivations outside physics.

Page 12: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 12

Microelectronics: the Moore’s law

Mosfet Scaling in microelectronics enabled, together with R&D in the sensor (diode), the accelerated improvement of detectors for Physics.

Page 13: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 13

T. Hemperek, Future of Tracking, Oxford 1-2 April 2019.

Moore’s law in electronics for pixel sensorsFE-I3 CMOS 250 nm

FE-I4 CMOS 130 nm

RD-53 CMOS 65 nm

Page 14: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 14

Silicon detectors and Readout Electronics arrangements

Sensitive diode, Analogue circuit and Digital circuits are the ever present elements.

The hybrid solution

Amplified diode and Alalogue/Digital readout

Monolithic solution

Page 15: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 15

Silicon detectors and Readout Electronics arrangements

Sensitive diode, Analogue circuit and Digital circuits are the ever present elements.

The hybrid solution

Amplified diode and Alalogue/Digital readout

Monolithic solution

Page 16: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 16

Silicon detectors and Readout Electronics arrangements

Sensitive diode, Analogue circuit and Digital circuits are the ever present elements.

The hybrid solution Amplified diode solution Monolithic solution

Page 17: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 17

Silicon detectors and Readout Electronics arrangements

Sensitive diode, Analogue circuit and Digital circuits are the ever present elements.

The hybrid solution Amplified diode solution Monolithic solutionMost used

Page 18: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 18

The diode signal and the electronics

Signal and electronics chain:

Page 19: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 19

Examples and typical sizes of the different architectures

40 – 110 m pitch, 1 – 4 cm long strips. Readout: Beetle chip, 0.25 μm CMOS.

Monolithic solution

Pixel sensor (200 μm thick) and FE-I4 (400 μm thick) readout hybrid (bump-bonded) assembly. 130 nm CMOS, 20x18.8 mm2, 26880 pixel, size 50x250 μm2).

MAP sensor 50 μm thick, 80 x 80 μm2. R&D for mu3e, 180 nm CMOS.

Page 20: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 20

Manufacturing of sensors and electronics

Who makes sensors and who makes electronics

Custom diode arrays foundries Commercial large scale CMOS manufacturers

IMEC, IBM, TSMC, AMS, TJ, LF, GF, …..

HPK, CIS, CNM, CSEM, FBK, Micron, MPI, SINTEF, VTT, …..

Page 21: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 21

What Defines an Efficient detector?

An efficient detector (diode + readout electronics chain) allows for clear

separation of the signal from minimum ionizing particles (mip’s) from the noise

fluctuations. This is described by the quantity: S/N (signal over noise ratio).

Page 22: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 22

What Defines an Efficient detector?The signal over noise ratio (S/N)

Signal parameters:

The expected signal charge is a

function of the detector

Depleted thickness:

Typical thickness: 100-500 m

Most probable signal ~ 7600-38000

Page 23: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 23

NOISE

Noise of the detector/electronics chain:

Cd = detector capacitance

Ib = bias current

Rp = bias resistor

Rs = strip resistance

Vna2 = Preamplifier noise

+ front end electronics: ENCfe = a + bCd

2

iENCNoise

Page 24: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 24

What can silicon detector do?

Measure energy/momentum:

Measure position:

Measure time:

Delphi

t

V

Comparator threshold

t0

381) (1963) 24 NIM ,Gluckstern (R.L.

4

720

3.0

)()(

:tsmeasurement equidistan For

2

NBL

Px

P

P

N

Page 25: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 25

Silicon detectors and ever more difficult challenges from experiment’s requirements

• Interaction rates• Position resolution• Reduced mass• Reduced power• Timing capabilities• Radiation tolerance

ATLAS 120 pile-up collisions

Page 26: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 26

Example: the ALICE (A Large Ion Collider Experiment at CERN)

Interaction rate challenge

Very High Multiplicity every bunch crossing (25 ns).Drives requirements to small individual channel area, fast repetition rates. Specifications for the sensors:

Sensor thickness (μm) 50 50

Spatial resolution (μm) 5 10

Dimensions (mm2) 15 × 30 15 × 30

Power density (mW cm−2) 300 100

Time resolution (μs) 30 30

Detection efficiency (%) 99 99

Fake hit rate 10−5 10−5

TID radiation hardness (krad) 2700 100

NIEL radiation hardness 1.7× 1013 1012

Outer Inner

Page 27: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 27

ALPIDE 1.5 × 3 cm2 Monolithic Active Pixel with 512×1024 (row×column) 28x28 µm2 pixels that are read out in a binary hit/no-hit fashion. It combines a continuously active, low-power, in-pixel discriminating front-end with a fully asynchronous, hit-driven combinatorial circuit.

ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade NIM A, Volume 824, 11 July 2016, Pages 434-438Author links open overlay panel M.MagerOn behalf of the ALICE Collaboration

Interaction rate challenge

Page 28: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 28

Need to move away from optimal shaping time choices

Interaction rate challenge

Page 29: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 29

Position resolution challenge

Small pixel size also results in better spatial resolution:With binary readout the resolution is Pitch/sqrt(12).Interest in going towards very small pixels.

xL xR

12pitchx

L R

Page 30: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 30

Position reconstruction with good analogue output

LR

R

QQ

Q

xL xR

If a particle passes between two strips the deposited charge flows to the

nearest strip. Due to transverse diffusion (~10 m) and track angle the

charge can be shared between readout electrodes.

Ideally: linear relation and x

xL xR

LRL xxxx

L R

Typical situation

Position resolution challenge

Need good S/N (detector thickness), heavy

on data readout.

Page 31: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 31

Monolithic

Reduced mass challenge

Can be very thin (~25 µm of silicon in total)

and still fully efficient!

One of the main feature of MAPS

Page 32: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 32

Multiple scattering scales with the amount of material traversed. (beam-pipe, detectors, magnet,..)

Thus for precise measurement momentum, should also have as little material as possible in the

tracking detectors. (also important for precise energy measurement in the calorimeters.)

MSmeas

MS

CPCP

P

pLXBp

p

s

s

Ls

X

L

X

Lz

cp

MeV

)(

)! ofnt (independe 1

05.0

34

ln038.016.13

0

rms

plane

0rms

plane

00

0

rms

plane

A charged particle undergoes many “small–angle” scatters.

Mostly Coulomb interactions and some strong interactions (for

hadrons).

The width of the cumulated angular deflection in the xy-plane is:

Page 33: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 33

Reduced power challenge 3.3V

-HV

N-well

P-bulk

Electronics outside the collection well:• very small capacitance so low

noise, low power • collection by drift and diffusion

Electronics inside the collection well:• higher capacitance so higher noise,

power and cross-talk• faster collection by drift

e e

Besides: small feature size electronics, with lower Vdrive, has lower power consumption per operation

Page 34: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 34

Timing challenge (4d Tracking)

Great position resolution (10 m) combined with < 50 pstime resolution.

Noise and signal are key in term of timing performance.

2T = 2

TW + 2j + 2

TDC

2TW VTH/S ; VTH = Threshold voltage

S = Signal height

2j (S/N)-1 ; N = Noise

2TDC ; Not considered

Page 35: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 35

Radiation tolerance challengeRadiation Background Simulation: LHC and HL-LHC

At inner pixel radii - target survival to 2-3×1016 neq/cm2

Page 36: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

photo: J. Wenninger

http://cern.ch/fcc

FCC

PS

SPS

LHC

photo: J. Wenninger

HE-LHC

Work supported by the European Commission under the HORIZON 2020 projects EuroCirCol, grant agreement 654305; EASITrain, grant agreement no. 764879; ARIES, grant agreement 730871; and E-JADE, contract no. 645479

Future Circular Collider

Page 37: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

15.05.2019 Alain Blondel FCC CDR presentation Outlook 37

Target survival 1×1017 neq/cm2/Y

Page 38: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Radiation with protons/neutrons

Bulk damage: displacement of Si atoms within the crystal leaves vacancies and interstitials (defects).

• Energy needed to displace atom from lattice=15eV

• Damage energy dependent

< 2 keV isolated point defect

2-12 keV defect cluster

>12 keV many defect clusters

• This damage is called:

Non-Ionizing Energy Loss (NIEL)

– Results scaled to 1MeV neutrons

(e.g. ATLAS ID up to ~21014 neqcm-2yr-1)

• Electrons and photons don’t make defects!

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 38

Surface damage: ion trapping in SiO2, leading to charge on Si-SiO2 interface. Sensor design must be robust against this (not discussed here).

Orthogonal to mostof the abovesolutions to the otherchallenges

Page 39: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Surface damage• This effect is due to the presence in the SiO2 and SiO2-Si

interface of positive charges1. Fixed charges from production process2. Mobile positive impurity ions same as 1.3. Trapped holes from irradiation

• The trapped holes (less mobile than electrons) are generated by ionization• Heavy charged particles high ionization density high

recombination• Electrons/photons low ionization density low recombination

dominates

• This charged layer changes the electric properties of the segmented side of the detector• Increases the interstrip capacitance (Cint)• Increases the surface current• Reduce the breakdown voltage

• Depends on the crystal orientation

• Important for Linear Collider and Xfel experimentsG. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 39

Page 40: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Microscopic view...

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 40

The damaged lattice ‘zoo’

These can:

• donate electron/holes

• capture electron/holes (trapping)

• increase leakage current (two-step transitions valence to conduction band)

• act as recombination centres

Damaging effects on Silicon detectors:

• increased leakage currents

• type-inversion (change of effective doping type)

• reduced charge collection efficiency and charge carrier mobility

Page 41: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

41

Reduction of the chargecollection efficiency

tQtQ

heeff

hehe

,

,0,

1exp)(

eqhe

heeff

tT ),(1

,

,,

Increase of the VFDIncrease of the reverse current

Page 42: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

More relevant method: analogue readout with LHC speed electronics

Mip signal from 90Sr source

Analogue information from the Alibava board (equipped with Beetle chip) 42G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China

Page 43: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Results with proton irradiated 300 m n-in-p Micron sensors (up to 1x1016 neq cm-2)

RED: irradiated with 24GeV/c protonsOther: 26MeV protons

43G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China

Irradiated with reactor neutrons

Look at the voltage scale!!

Page 44: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Role of thickness

44

Charge degradation vs fluence for silicon sensors with different

thicknesses

The onset of Charge Multiplication breaks a few rules, like the

proportionality of the signal with thickness.....

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China

Page 45: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

45

• Array of electrode columns passing through substrate

• Electrode spacing << wafer thickness (e.g. 30m:300m)

• Benefits

• Vdepletion (Electrode spacing)2

• Collection time Electrode spacing

• Reduced charge sharing

• More complicated fabrication - micromachining

Different detector structure: 3D Detectors

Planar 3D

Around

30µm

+ve +ve-ve

holes

300µm

n-type

electrode

p-type

electrode

electrons

ParticleAround

30µm

+ve +ve-ve

holes

300µm

n-type

electrode

p-type

electrode

electrons

Particle

300300

+ve+ve

holes

-ve

electrons

Lightly

doped

p-type

silicon

n-type

electrode

p-type

electrode

Particle

+ve+ve

holes

-ve

electrons

Lightly

doped

p-type

silicon

n-type

electrode

p-type

electrode

Particle

µmµm

Proposed by S. Parker

and C. Kenney of the

University of Hawaii in

1995.

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China

Page 46: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

3d Sensor radiation hardness

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 46

• 3D pixel detectors bump bonded to ATLAS FE-I4 show > 98% efficiency after 3x1016 neq cm-2.

• Modern electronics with small feature size show very good radiation tolerance by technology.

• This is also been shown with dedicated irradiation runs with 65 nm circuits (not yet on full assemblies)

Page 47: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Mitigation of sensor degradation

One essentially needs:

• Very high Electric field (voltage)

• Low noise

Parameters: Sensor geometry, operation conditions (cooling)

Parameters: Sensor geometry, operation conditions (cooling), electronics

At intermediate radiation damage one can

play other tricks:

Choice of bulk resistivity

Choice of bulk type (impurity content)

Page 48: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

Applying High Voltage to D-CMOS

HV

Page 49: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

From LingxinMeng PhD thesis.

Applying High Voltage to D-CMOS: Top biasing

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 49

Page 50: New trends in silicon technology - Home · Indico · 2019. 6. 4. · New trends in silicon technology G. Casse 5th Summer School on Intelligent signal processing for FrontIEr research

It is possible, with careful design, to apply HV to D-CMOS devices

From LingxinMeng PhD thesis.

Applying High Voltage to D-CMOS: Backside biasing

G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 50

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A few results with D-CMOS

Other relevant metrics! Non irradiated sensor for mu3e.

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Radiation hardening of D-CMOS

Max irradiation 5e15 neq cm-2.

M. Benoit et al., Characterization Results of a HVCMOS Sensor for ATLAS, NIMA

M. Benoit et al., Test beam measurement of ams H35 HV-CMOS

capacitively coupled , JINST 13 (2018) no.12, P12009

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A look at the electronics

• Is electronics still evolving at Moore’s law speed?• Can we just take the most advanced development of

micro-electronics and used it in detector technology?

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G. Casse, 5th INFIERI, 12-26 May 2019, HUST, Wuhan, China 54

CMOS industryShort channel effects limit scaling of CMOS!

From A. Marchioro Seminar, May 2019

In 2001:CMOS extendible down to 14 nm for High-Performance logicand 35 nm for low power applications

Characteristics of a transistor:• ON/OFF sharp characteristics• Off current ≈ 0 A• High On current (1mA/m)• Small Vdrive (for power, P = C*VTr

2)

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Short channel effects

Short channel effects: Velocity saturationDrain Induce Barrier Lowering (DIBL)Gate oxide leakage current

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CMOS industryShort channel effects: Velocity saturation

From A. Marchioro Seminar, May 2019

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Short channel effects: Velocity saturation

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Drain Induce Barrier Lowering (DIBL)

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Transistor Current-Voltage characteristics

Gate engineering: Transistor operations

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Transistor Gate delay

Gate engineering: Transistor operations

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Gate oxide leakage currentGate oxide:Thickness down to 2 nm (65 nm) and going lower!!

High K material bring great improvement

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CMOS and detectors today

Expected position resolution > 15 µm.Thanks to small (65 nm) feature size, 600M transistors in total, most in the digital section. The analogue area needs much larger transistors!!

The pixel size cannot scale down with the technology feature size.

RD53 65 nm CMOS pixel readout chip for extreme

data rates and radiation levels (V. Re et al., CERN/RD53

collaboration)

Advanced readout chip for the pixel layers of ATLAS and CMS Upgrades at CERN

State-of-the-art

50 µm

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For mixed signal devices, there is little gain from going beyond the 65 nm

process, signalling a stop in the evolution of mixed signal ASICs.

Moore’s law is broken in sensor evolution.

Reduction of the transistor

channel length (feature size,

S) over the years.

65 nm first

functional ASIC

produced in spring

2018 (RD53)

Technologies

adopted for Si

sensors

10

6

3

10.8

0.6

0.350.25

0.180.13

0.090.065

0.0450.032

0.022

0.0140.01

0.0070.005

0.001

0.01

0.1

1

10

1960 1970 1980 1990 2000 2010 2020 2030

Size

in m

icro

n (

µm

)Year

Feature size exploited for

mixed signal pixel devices for

particle detection.

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A point of attention: the overcoming of small channel effects to carry on

Moore’s law DOES NOT HOLD for analogue performance!

Moore’s law is broken in sensor evolution.

Reduction of the transistor

channel length (feature size,

S) over the years.

65 nm first

functional ASIC

produced in spring

2018 (RD53)

Technologies

adopted for Si

sensors

10

6

3

10.8

0.6

0.350.25

0.180.13

0.090.065

0.0450.032

0.022

0.0140.01

0.0070.005

0.001

0.01

0.1

1

10

1960 1970 1980 1990 2000 2010 2020 2030

Size

in m

icro

n (

µm

)Year

Feature size exploited for

mixed signal pixel devices for

particle detection.

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Sensor trends: CMOS and sensors tomorrow?

65

The hybrid solution Amplified diode solution Monolithic solutionMost used

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Sensor trends

66

The hybrid solution Amplified diode solution Monolithic solutionMost used

… and the winner is …….

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Sensor trends

67

The hybrid solution Amplified diode solution Monolithic solutionMost used

… is it? …….

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How does see it industry?

http://www.sony.net/Products/SC-HP/cx_news/vol68/pdf/sideview_vol68.pdf#page=1

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Sensor trends: CMOS and sensors tomorrow?

69

The hybrid solution Amplified diode solution Monolithic solutionMost used

This is the most powerful solution technically available (given a number of conditions).

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SUMMARY

Silicon tracker detectors have been developed to serve the needs of Particle Physics collider experiments and had an accelerated evolution over the years. A key component of this success has been the spectacular improvements of CMOS. The detector systems have overcome all the extreme challenges posed by HEP experiments over the years, from very high multiplicities, high interaction rates, extreme radiation tolerance, high position resolution demand, ….Several new concepts have been introduced in the technology, like n-side readout and 3D geometries for radiation tolerance, low mass sensors, monolithic sensors, 4D devices, ….HEP sensors have also found their ways in many other scientific endeavours or technology applications. The technology and the synergy between the sensor part (diode) and the electronics has seen a departure from the parallel evolution. This is mainly due to the lack of analogue performance quality in the most extreme (< 65 nm) CMOS technologies. So, if the last few years trend was to move the technology more towards monolithic devices, the current best guess for enhanced performance in the next few years is to separate the analogue tier from the digital one, in order to use different CMOS nodes (very small in the digital node for increase readout and computational local capabilities and larger nodes like 130/65 nm for analogue electronics). Interconnectivity (bump bonding will not be envisaged at these scales) is an issue, already solved in industry. But, in the future, new ideas could surface to change again the detector field. And, meanwhile, HEP is preparing experiment ideas that are pushing again the detector science to extreme territories (radiation, low mass, speed).