New 8085 Mnemonics

MICROPROCESSOR, INSTRUMENTATION & CONTROL LABORATORY

8085

INSTRUCTION SET

&

LIST OF EXPERIMENTS

MODULE: ELEC 2104 8085 INSTRUCTION SET AND MACHINE CODE

ACI :Add immediate to accumulator with carry.

This document is prepared by Associate Prof. C. Bhurtun and should not be used/ reproduced without permission

1

Description :The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator,and the result stored in the accumulator.M-Cycles : 2T-States : 7Machine code :CEAll flags are modified.

ADC : Add register to accumulator with carry.Description : The contents of the operand (register or memory) and the Carry flag are added to the content of the accumulator and the result is placed in the accumulator. The contents of the operand are not altered; however the previous Carry flag is reset.M-Cycles : 1 (register), 2 (memory)T-states : 4 (register), 7 (memory)Machine Code : Register Code B 88 C 89 D 8A E 8B H 8C L 8D M 8E A 8FAll flags are modified.

ADD : Add register to accumulator.Description : The contents of the operand (register or memory) are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location , it is indicated by the 16-bit address in the HL register.M-Cycles : 1(register), 2(memory)T-states : 4(register), 7(memory)Machine Code : Register Code B 80 C 81 D 82 E 83 H 84 L 85 M 86 A 87All flags are modified.ADI : Add immediate to accumulator.Description : The 8-bit data (operand) is added to the contents of the accumulator, and the result is placed in the accumulator.


2

M-Cycles : 2T-states : 7Machine Code : C6All flags are modified.

ANA : Logical AND with the accumulator.Description : The contents of the accumulator are logically ANDed with the contents of the operand (register or memory),and the result is placed in the acc. If the operand is a memory location , its address is specified by the content of the HL pair.M-Cycles : 1 (register), 2 (memory)T-states : 4 (register), 7 (memory)Machine Code : Register Code B A0 C A1 D A2 E A3 H A4 L A5 M A6 A A7Flags S,Z,P are modified. CY is reset. AC is set.

ANI : AND immediate with accumulator.Description : The contents of the acc. are logically ANDed with the 8-bit data (operand) and the result placed in the acc.M-Cycle : 2T-states : 7Machine Code : E6Flags S,Z,P are modified. CY is reset. AC is set

CALL : Unconditional subroutine call.Description : The program sequence is transferred to the address specified by the operand. Before the transfer , the address of the next instruction to CALL (the content of the Program Counter) is pushed on the stack.M-Cycles : 5T-states : 18Machine Code : CDNo flags are affected.

Conditional Call to Subroutine Operand -- 16 bit AddressMnemonics Description Flag status Machine Code M-Cycles T-states CC Call on carry CY= 1 DC 2 9 : if condition is


3

CNC Call with no carry CY= 0 D4 not true. CP Call on positive S= 0 F4 CM Call on minus S= 1 FC 5 18 : if condition CPE Call on parity even P= 1 EC is true. CPO Call on parity Odd P= 0 E4 CZ Call on zero Z= 1 CC CNZ Call on no zero Z= 0 C4No flags are affected.

CMA : Complement AccumulatorDescription : The contents of the accumulator are complemented.M-Cycles : 1T-states : 4Machine Code : 2FNo flags are affected.

CMC : Complement Carry.Description : The Carry flag is complemented.M-Cycles : 1T-states : 4Machine Code : 3FThe Carry flag is modified; no other flags are affected.

CMP : Compare with accumulatorDescription : The contents of the operand (register or memory) are compared with the contents of the accumulator. Both contents are preserved and the comparison is shown by setting the flags as follows:-- If [A] < [Reg./Mem] : Carry flag is set.- If [A] = [Reg./Mem] : Zero flag is set.- If [A] > [Reg./Mem] : Carry and Zero flag are reset.M-Cycles : 1 (register), 2 (memory)T-states : 4 (register), 7 (memory)Machine Code : Register Code B B8 C B9 D BA E BB H BC L BD M BE A BFFlags S,P,AC are also modified in addition to Z and C.

CPI : Compare immediate with accumulatorDescription : The 8-bit data is compared with the content of the accumulator. The values being compared remain unchanged and the results of


4

the comparison are indicated by setting the flags as follows:-- If [A] < data: Carry flag is set.- If [A] = data: Zero flag is set.- If [A] > data: Neither Z nor C is set.M-Cycles : 2T-states : 7Machine Code : FEFlags S,P,AC are also modified in addition to Z and C.

DAA : Decimal adjust accumulatorDescription : The contents of the acc. are changed from a binary value to two 4-bit BCD digits.This is the only instruction that uses the auxiliary flag (internally) to perform the binary to BCD conversion.M-Cycles : 1T-states : 4Machine Code : 27Flags S,Z,AC,P,CY flags are altered to reflect the results of the operation.

DAD : Add register pair to H and L pair registers.Description : The 16-bit contents of the specified register pair are added to the contents of the HL pair and the sum is saved in the HL pair.The contents of the source register pair are not altered.M-Cycles : 3T-states : 10Machine Code : Reg. pair Code BC 09 DE 19 HL 29 SP 39CY flag is set if the result is larger than 16-bit.No other flags are affected.

DCR :Decrement source by 1Description : The contents of the designated register/memory is decremented by 1 and the result is stored in the same place.If the operand is a memory location , it is specified by the contents of the HL pair.M-cycle : 1 (register), 3 (memory) T-states : 4 (register), 10 (memory)

Machine Code : Register Code B 05 C 0D


5

D 15 E 1D H 25 L 2D M 35 A 3DS, Z, P, AC are affected.CY is not modified.

DCX : Decrement register pair by 1.Description : The contents of the specified register pair are decremented by 1.This instruction views the contents of the registers as a 16-bit number.M - Cycles : 1T - States : 6Machine Code : Register Code B 0B D 1B H 2B SP 3B No flags are affected.

DI : Disable interrupts.Description : the Interrupt Enable flip-flop is reset and all the interrupts except the TRAP are disabled.M - Cycles : 1T - States : 4Machine Code : F3No flags are affected.

EI : Enable interrupts.Description : The Interrupt Enable flip-flop is set and all interrupts are enabled.M - Cycles : 1T - States : 4Machine Code : FBNo flags are affected.

HLT : Halt and enter WAIT state.Description : The processor executes the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the HALT state.


6

M - Cycles : 2 or more.T - States : 5 or more.Machine Code : 76No flags are affected.

IN : Input data to acc. from a port with 8-bit address.Description : The contents of the input port designated in the operand are read and loaded in the acc.M - Cycles : 3T - States : 10Machine Code : DBNo flags are affected.

INR : Increment contents of register/memory by 1Description : The contents of the designated register/memory are incremented by 1 and the results are stored in the same place. If the operand is a memory location , it is specified by the contents of H-L pair.M - Cycles : 1(register) , 3(memory)T - States : 4(register) , 10(memory)Machine Code : Register Code B 04 C 0C D 14 E 1C H 24 L 2C M 34 A 3CFlags S , Z , P , AC are modified.CY is not affected.

INX : Increment register pair by 1Description : The contents of the specified register pair are incremented by 1. The instruction views the contents of the two registers as a 16-bit number.M - Cycles : 1T - States : 5Machine Code : Register Pair Code B 03 D 13 H 23 SP 33No flags are affected.JMP : jump unconditionally Description : The program sequence is transferred to the memory location specified by the 16-bit address. This is a 3-byte instruction , the 2nd byte


7

specifies the low-order byte and the 3rd byte specifies the high-order byte.M - Cycles : 3T - States : 10Machine Code : C3No flags are affected.

JUMP CONDITIONALLYOperand : 16-bit AddressCode Description Flag status Machine code M-Cycles/T-States JC Jump on carry CY = 1 DA 2M / 7T (if condition JNC Jump on no carry CY = 0 D2 is not true) JP Jump on positive S = 0 F2 JM Jump on minus S = 1 FA 3M / 10T (if condition JPE Jump on parity even P = 1 EA is true) JPO Jump on parity odd P = 0 E2 JZ Jump on zero Z = 1 CA JNZ Jump on no zero Z = 0 C2No flags are affected.

LDA : Load accumulator directDescription : The content of a memory location , specified by a 16-bit address in the operand , are copied to the acc. the contents of the source are not altered. This is a 3-byte instruction , the 2nd byte specifies the low-order address amd the 3rd byte , the high-order address.M -Cycles : 3T - States : 13Machine Code : 3ANo flags are affected.

LDAX : Load accumulator indirectDescription : The contents of the designated register pair point to a memory location. This instruction copies the contents of that location into the accumulator. The contents of both the register pair and memory location are not affected.M - Cycles : 2T - States : 7Machine Code : Register Code BC 0A DE 1ANo flags are affected.

LHLD : Load HL pair direct.Description : The instruction copies the contents of the memory location pointed out by the 16-bit address in register L and copies the contents of the next memory location in register H. The contents of source memory locations


8

are not altered.M - Cycles : 5T - States : 16Machine Code : 2ANo flags are affected.

LXI : Load register pair immediateDescription : The instruction loads 16-bit data in the register pair designated in the operand.This is a 3-byte instruction , the 2nd byte specifies the low- order byte and the 3rd byte specifies the high-order byte.M- Cycles : 3T - States : 10Machine Code : Reg. pair Code B 01 D 11 H 21 SP 31No flags are affected.

MOV : Copy from source to destinationDescription : The instruction copies the contents of the source register into the destination register ; the content of the source register is not altered. If one of the operands is a memory location , it is specified in the HL pair.M - Cycles : 1(register to register) , 2(register to memory and vice versa)T - States : 4(register to register) , 7(register to memory and vice versa)Machine Code : Source Location

B C D E H L M A B 40 41 42 43 44 45 46 47 C 48 49 4A 4B 4C 4D 4E 4F D 50 51 52 53 54 55 56 57

Destination E 58 59 5A 5B 5C 5D 5E 5FLocation H 60 61 62 63 64 65 66 67

L 68 69 6A 6B 6C 6D 6E 6F M 70 71 72 73 74 75 77 A 78 79 7A 7B 7C 7D 7E 7F

No flags are affected.

MVI : Move immediate 8-bitDescription : The 8-bit data is stored in the destination register or memory. If the operand


9

is a memory location , it is specified in the HL pair.M- Cycles : 2(register) , 3(memory)T - States : 7(register) , 10(memory)Machine Code : Register Code

B 06 C 0E D 16 E 1E H 26 L 2E

M 36 A 3E


NOP : No operationDescription : No operation is performed. The instruction is fetched and decoded; however no operation is executed.M - Cycles : 1T - States : 4Machine Code : 00No flags are affected.

ORA : Logical OR with the accumulatorDescription : The content of the acc. is logically ORed with the contents of the operand (register or memory), and the results are placed in the acc. If the operand is a memory location , its address is specified in the HL pair.M - Cycles : 1(register) , 2(memory)T - States : 4(register) , 7(memory)Machine Code : Register Code

B B0 C B1 D B2 E B3 H B4 L B5 M B6

A B7Flags Z , S , P are modified. AC and CY are reset.

ORI : Logically OR immediate


10

Description : The contents of the acc. are logically ORed with the 8-bit data in the operand and the results are placed in the acc.M - Cycles : 2T - States : 7Machine Code : F6Flags Z , S , P are modified . CY and AC are reset.

OUT : Output data from accumulator to a port with 8-bit address.Description : The contents of the acc. is copied into the I / O port specified by the operand.M - Cycles : 3T - States : 10Machine Code : D3No flags are affected.

PCHL : Load Program Counter with HL contentsDescription : The contents of registers H & L are copied into the PC. The contents of H are placed as the higher byte and of L as the lower byte.M - Cycles : 1T - States : 6Machine Code : E9No flags are affected.

POP : Pop off stack to register pairDescription : The contents of the memory location pointed by the stack pointer register are copied to the low-order register (such as C , E , L , and flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B , D , H , A) of the operand. The SP register is again incremented by 1.M - Cycles : 3T - States : 10Machine Code : Register Code

B C1 D D1 H E1 PSW F1



11

PUSH : Push register pair onto stack.Description : The contents of the register pair designated in the operand are copied into the stack in the following sequence. The SP register is decremented and the contents of the high-order register (B , D , H , A) are copied into that location. The SP register is decremented again and the contents of the low- order register (C , E , L , flags) are copied to that location.M - Cycles : 3T - States : 12Machine Code : Register Code

B C5 D D5 H E5 PSW F5

NO flags are affected.

RAL : Rotate accumulator left through carry.Description : Each bit of the acc. is rotated left by 1 position through the carry flag. Bit 7 is placed in the Carry flag and the bit in the Carry flag is placed in the least significant position (bit 0).M - Cycles : 1T - States : 4Machine Code : 17CY is modified according to bit 7. S , Z , AC , P are not affected.

RAR : Rotate accumulator right through carry.Description : Each bit of the acc. is rotated right by 1 position through the CY flag. Bit 0 is placed in the CY flag and the bit in the CY flag is placed in the most significant position (bit 7).M - Cycles : 1T - States : 4Machine Code : 1FCY is modified according to bit 0. S , Z , P , AC are not affected.

RLC : Rotate accumulator leftDescription : Each bit of the acc. is rotated left by 1 position. Bit 7 is placed in the position of bit 0 as well as in the CY flag.M - Cycles : 1T - States : 4Machine Code : 07CY is modified according to bit 7. S , Z , P , AC are not affected.


12

RRC : Rotate accumulator right.Description : Each bit of the acc. is rotated right by 1 position. Bit 0 is placed in the position of bit 7 as well in the CY flag.M - Cycles : 1T - States : 4Machine Code : 0FCY is modified according to bit 0. S , Z , P , A are not affected.

RET : Return from subroutine unconditionally.Description : The program sequence is transferred from the subroutine to the calling program. The 2 bytes from the top of the stack are copied into the PC and the program execution begins at the new address. The instruction is equivalent to POP PCM - Cycles : 3T - States : 10Machine Code : C9No flags are affected.

RETURN CONDITIONALLYCode Description Flag Status Machine Code M-Cycles / T-StatesRC Return on carry CY = 1 D8 1 / 6 If condition is not trueRNC Return on no carry CY = 0 D0 3 /12 If condition is trueRP Return on positive S = 0 F0RM Return on minus S = 1 F8 Note : If the condition is not trueRPE Return on parity even P = 1 E8 it continues the sequence andRPO Return on parity odd P = 0 E0 thus requires fewer T- States.RZ Return on zero Z = 1 C8 If condition is true it returnsRNZ Return on No zero Z = 0 C0 to the calling program and thusNo flags are affected requires more T- States.

RIM : Read interrupt mask.Description : This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5 and 5.5 , and read serial data input bit.M - Cycles : 1T - States : 4Machine Code : 20No flags are affected.


13

SBB : Subtract source and borrow from accumulatorDescription : The contents of the operand (register or memory) and the Borrow Flag are subtracted from the contents of the acc. and the results are placed in the acc. The contents of the operand are not altered; however the previous Borrow Flag is reset.M - Cycles : 1(register) , 2(memory)T - states : 4(register) , 7(memory)Machine Code : Register Code

B 98 C 99 D 9A E 9B H 9C L 9D M 9E A 9F

All flags are altered to reflect the result of the subtraction.

SBI : Subtract immediate with borrow.Description : The 8-bit data (operand) and the borrow are subtracted from the contents of the acc. and the results are placed in the acc.M - Cycles : 2T - States : 7Machine Code : DEAll flags are altered to reflect the result of the operation.

SHLD : Store H & L registers direct.Description : The contents of register L are stored in the stored in the memory location specified by the 16-bit address in the operand and the contents of H register are stored in the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3-byte instruction , the second byte specifies the low-order address and the third byte specifies the high-order address.M - Cycles : 3T - States : 16Machine Code : 22No flags are affected.

SIM : Set interrupt mask


14

Description : This is a multipurpose instruction and used to implement the 8085 interrupts (RST 7.5 , 6.5 , 5.5) and serial data output.M - Cycles : 1T - States : 4Machine Code : 30No flags are affected.SPHL : Copy H & L to the SPDescription : The instruction loads the contents of the H & L registers into the stack pointer register , the contents of H provide the high-order address and the contents of the L register provide the low-order address. The contents of the H & L registers are not affected.M - Cycles : 1T - States : 6Machine Code : F9No flags are affected.

STA : Store the accumulator direct.Description : The contents of the acc. are copied to a memory location specified by the operand. This is a 3-byte instruction , the 2nd byte specifies the low-order address and the 3rd byte specifies the high-order address.M - Cycles : 4T - States : 13Machine Code : 32No flags are affected.

STAX : Store accumulator indIrect.Description : The contents of the acc. are copied into the memory location specified by the contents of the operand (register pair). The contents of the acc. are not affected.M - Cycles : 2T - States : 7Machine Code : Register Code

B 02 C 12


STC : Set carryDescription : The CY flag is set to 1M - Cycles : 1T - States : 4Machine Code : 37No other flags are affected.


15

SUB : Subtract register or memory from accumulator.Description : The contents of the register or the memory location specified by the operand are subtracted from the contents of the acc. , and the result placed in the acc. The contents of the source are not altered.M - Cycles : 1(register) , 2(memory)T - States : 4(register) , 7(memory)Machine Code : Register Code

B 90 C 91 D 92 E 93 H 94 L 95 M 96 A 97

All flags are affected to reflect the result of the subtraction.

SUI : Subtract immediate with accumulator.Description : The 8-bit data is subtracted from the contents of the acc. and the result placed in the acc.M -Cycles : 2T - States : 7Machine Code : D6All flags are modified to reflect the result of the operation.

XCHG : Exchange H & L with D & EDescription : The contents of the register H are exchanged with that of register D and the contents of L are exchanged with that of E.M - Cycles : 1T - States : 4Machine Code : EBNo flags are affected

XRA : Exclusive OR with the accumulator.Description : The contents of the operand are Exclusive-ORed with the contents of the acc and the results placed in the acc. The contents of the operand are not altered.M - Cycles : 1(register) , 2(memory)T - States : 4(register) , 7(memory)


16

Machine Code : Register Code B A8 C A9 D AA E AB H AC L AD M AE A AF

Z , S , P are altered to reflect the result of the operation. CY and AC are reset.

XRI : Exclusive OR immediate with accumulator.Description : The 8-bit data is Exclusive ORed with the contents of the acc. and the results are placed in the acc.M - Cycles : 2T - States : 7Machine Code : EEZ , S , P are altered. CY and AC are reset.

Microprocessor, Instrumentation & Control lab.


17

Documents

New 8085 Mnemonics