Network On Chip Network On Chip Cache CoherencyCache CoherencyFinal presentation – Part AFinal presentation – Part A

Students:Students: Zemer Tzach Zemer Tzach Kalifon EthanKalifon Ethan

Instructor:Instructor: Walter Walter IsascharIsaschar

Spring 2008Spring 2008

AgendaAgendaProject’s general concepts.

Design architecture of the router.

Implementation of the router (using HDL Designer).

Router’s simulations.

Demonstration of our NoC.

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General BackgroundGeneral Background

Modern CPU’s are based on CMP - Multi-Core Processor.

Improved performance is achieved by “Distribution and Parallelism”.

Cores interact by using NoC – Network on Chip.

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NoC’s General DiagramNoC’s General Diagram

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NoC’s CharacteristicsNoC’s Characteristics

Wormhole packet routing.

Packet’s path is X-Y.

Units can communicate simultaneously.

Reduce power consumption.

Scalability.

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Cache CoherencyCache Coherency

Definition: CMP cores use only up to date data.

Originally, Cache Coherency in CMP was achieved by using a central memory control unit.

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Cache Coherency Cache Coherency Protocol NowadaysProtocol Nowadays

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Problem DescriptionProblem Description

Prior Cache Coherency protocols are irrelevant – NoC doesn’t have central unit.

Adding such unit will damage both NoC’s scalability and parallelism.

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Solution RequirementsSolution Requirements

Won’t affect main NoC’s characteristics (e.g. scalability).

Avoid “Hot Spots” and “Bottle Necks”.

Minimize use of NoC’s resources.

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SolutionSolution

Memory control distribution among a number of units according to memory spaces.

Placement of control units as part of the NoC.

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Solution DiagramSolution Diagram

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Project’s GoalsProject’s Goals

Primary Goal:Primary Goal: Design and Design and

implement Cache Coherencyimplement Cache Coherency

protocol for CMP.protocol for CMP.Implement NoC (including NoC’s router).Assemble CMP based on NoC.

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NoC Packet’s StructureNoC Packet’s StructurePacket is divided into flits.

There are four flit types: Start, Body, End and Idle.

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Flit’s StructureFlit’s StructureFlit contain two fields: Data and Type.

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5 Ports Router5 Ports Router

Direct packets according to X-Y routing.5 ports – North, East, West, South and

Processing Unit.Processing Units are using the network’s

communication protocol.2 Virtual Channels (VC) per port.

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5 Ports Router Structure 5 Ports Router Structure

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Input PortInput Port

Receives Flits from Router or from Processing unit.

Analyze and save the current packet direction.

Switch between Virtual Channels.

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Input Port StructureInput Port Structure

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Output PortOutput Port

Transmits Flits to Router or to Processing unit.

Each Virtual Channel save the currently serviced input port (CSIP).

Switch between Virtual Channels.

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Output Port StructureOutput Port Structure

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Cross BarCross Bar

Transfer Flits from Input Port to the matching Output Port.

Consists of 5 controllers – one for every Output Port.

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Cross Bar StructureCross Bar Structure

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Network’s characteristics Network’s characteristics

The width of the Data bus is 8 bit.The size of the ports’ buffers is 4 flits (can

contain 4 flit at the most).The NoC is composed of 9 routers, placed

in 3x3 grid formation.

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Input’s VC ImplementationInput’s VC Implementation

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Output’s VC Output’s VC ImplementationImplementation

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Input Port ImplementationInput Port Implementation

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Output Port Output Port ImplementationImplementation

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Output’s Controller Output’s Controller ImplementationImplementation

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Crossbar_Mux ImplementationCrossbar_Mux Implementation

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Cross Bar ImplementationCross Bar Implementation

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Router ImplementationRouter Implementation

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Synthesis ParametersSynthesis Parameters

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Network’s PerformanceNetwork’s Performance

Latency of the router is 2 cycles.Throughput of the router is 1 flit per cycle.System’s clock frequency is 100 [MHz].Packets can be routed simultaneously.Packets can by-pass each other.

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Cross TransmitCross Transmit

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Routing two packets simultaneously: port 0 to port 2 and port 3 to port 2.

Traffic avoidance by using VCTraffic avoidance by using VC

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First packet from port 0 to port 1 get blocked in output port.Packet from port 3 to port 1 by-pass it.

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Demonstration DiagramDemonstration Diagram

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General DescriptionGeneral Description

Dummy units transmit packets.Destination is being set by the switch-

buttons.The Dummy port start transmitting

according to its push-button.

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Project Schedule Project Schedule (1(1stst Semester) Semester)Familiarize with design tools – 3 weeks.Familiarize with VirtexII Pro FPGA (application

& components) – 4 weeks.Design & Implement NoC’s router – 5

weeks.Assemble CMP using our router

implementation – 2 weeks.

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Project Schedule Project Schedule (2(2ndnd Semester) Semester)Assemble CMP using our router

implementation – 4 weeks.Design Cache Coherency protocol for CMP

based on faculty research – 4 weeks.Implement the protocol as part of the

assembled CMP – 6 weeks.

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