A Project Report on

NEGATIVE BIAS TEMPERATURE INSTABILITY

EE311 Term Paper

Prashant Khokhar Y9427

Shiv Prakash Y9551

Shouvik Ganguly Y9558

Rakesh Meena Y9474

Kundan Kanwaria Y9300

Asutosh Tiwari Y9152

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1.Introduction

Negative Bias Temperature Instability (NBTI) is a key reliability issue in MOSFETs. It is of

immediate concern in p-channel MOs devices, since they almost always operate with negative gate-

to-source voltage; however, the very same mechanism affects also n-MOS transistors when biased in

the accumulation regime, i.e. with a negative bias applied to the gate too. NBTI manifests as an

increase in the threshold voltage, a degradation of the mobility, drain current and trans-conductance.

This instability in MOSFETs has been known since 1996. It is become a reliability issue in silicon

integrated circuits, because gate electric field have increased as a result of scaling, increased chip

operating temperature, surface p-channel MOSFETs have replaced buried channel devices, and

nitrogen is routinely added to thermally grown SiO2.

A brief history on NBTI shows that reliability issue in MOSFETs is a serious issue:

Experiments in late 1960s by Deal and Grove at Fairchild Role of Si-H bonds and BTI vs. NBTI story (J. Electrochem Soc. 1973;114:266)

Came out naturally as PMOS was dominant

Important in FAMOS and p-MOS EEPROMS (Solid State Circuits 1971;6:301)

Theory in late 1970s by Jeppson (JAP, 1977; 48:2004) Generalized Reaction-Diffusion Model

Discusses the role of relaxation, bulk traps

Comprehensive study of available experiments Early 1980s

Issue disappears with NMOS technology and buried channel PMOS

Early 1980s

Issue disappears with NMOS technology and buried channel PMOS

Late 1980s and Early 1990s Begins to become an issue with dual poly gate, but HCI dominates device reliability

Late 1990s/Early 2000 (Kimizuka, IRPS97; 282. Yamamoto, TED99; 46:921. Mitani, IEDM02;

509)

Voltage scaling reduces HCI and TDDB, but increasing field & temperature reintroduce NBTI

concerns for both analogue and digital circuits.

Numerical solution is extensively used for theoretical modeling of NBTI

What is NBTI?

NBTI is an increase in the absolute threshold voltage, a degradation of the mobility, drain current, and

transconductance of p-channel MOSFETs. These typesof effects are generally found in pMOSFETs.

When a PMOS transistor is biased in inversion, the dissociation of Si-H bonds along the silicon-oxide

interface causes the generation of interface traps. The rate of generation of these traps is accelerated

by temperature, and the time of applied stress. These traps cause an increase in the threshold voltage

(Vth) of the PMOS transistors. An increase in Vth causes the circuit delay to degrade, and when this

degradation exceeds a certain magnitude, the circuit may fail to meet its timing specifications. This

effect is known as the Negative Bias Temperature Instability (NBTI). Mechanism of NBTI is the

degradation of Si-H bonds broken by the chemical reaction with high energy holes on SiO2/Si surface.

In PMOS voltage between gate and the source is negative (Vgs = -Vdd), causes the interface traps and

when (Vgs = 0) causes the reduction in the interface traps. Thus the effect of NBTI on the PMOS

depends on the time the device has been stressed, and relaxed.

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It is commonly accepted that two kinds of trap contribute to NBTI:

When Vgs is negative, interface traps are generated. Those traps cannot be recovered over a

reasonable time of operation i.e. Vgs= 0. It is believed that the electric field is able to break Si-H bonds

located at the Silicon-oxide interface. H is released in the substrate where it migrates. The remaining

dangling bonds (Si-Pb center) contribute to the threshold voltage degradation.

On top of the interface states generation some pre-existing traps located in the bulk of the dielectric

(and supposedly nitrogen related), are filled with holes coming from the channel of p-MOS. Those

traps can be emptied when the stress voltage is removed. This Vth degradation can be recovered over

time.

NBTI Models

Many models have been discussed on the NBTI. Here we discuss some model on which NBTI affects,

which include Reaction Diffusion model, Models of Source Drain bias.

Model of Source Drain Bias

In this experimental model following devices were used: surface channel P+poly-silicon gate p-

MOSFETs fabricated with silicon oxynitride (SiON) gate dielectric using a 90 nm nodeCMOS

technology, with channel width of 10µm, andvarious channel lengths. The gate dielectrics

withequivalent oxide thickness (EOT) = 1.9 nm were grownby thermal oxidation followed by plasma

nitridation and post-deposition thermal annealing.

In this experiment, negative voltage was applied to the gate and drain, source and substrate grounded.

The stress circuit diagram is given here:

Fig 1.1: Stress Circuit Diagram

The experimental result of source drain bias shows the effect of Vds on ∆Vth (Vth shift). The graph

given below shows the effect of source drain bias in threshold shift of pMOSFET for different

channel lengths.

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Fig 1.2: Vth vs Vds for different channel lengths

From the graph, we observe that for L = 0.1�m, when |Vds| changes from 0 to 0.5V then ∆Vth does not

change much but further increasing |Vds| increases NBTI degradation. For L = 0.3�m the NBTI

degradation is initially reduced but increases after |Vds| = 1.5V. We also observe that minimum

degradation occurs around |Vds| =1.5 V. This degradation leads to the generation of non-uniform

neutral hydrogen. Generation of more interface traps leads to the diffusion of hydrogen from the

source to the drain. The following figure shows the diffusion of hydrogen.

Fig 1.3: Hydrogen Diffusion

When there is S/D bias the interface traps density (Nit) at the drain canbe reduced and the Vth shift will

be less. In above figure it is also observed that devices are more stressed in the linear region since |Vgs|

> |Vth| and |Vds| < |Vgs|. The drain current, which is linearly dependent on the Vds, can be expressed as

Id = �

��C(Vgs – Vth)Vds

where w is the channel length in cm, � is the carrier mobility in cm2/(V-sec), and C is oxide

capacitance inF/cm2.

The drain current can also be expressed in terms of carrier velocity as

Id =qpvA

where p is carrier density in cm-3

, vis carrier velocity incm/sec and A is the cross-section area in cm2.

A = W.H

where H is the inversion layer thickness in cm.

From the above equations we can find the carrier velocity as

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v= �

� qH

VVC thgs )( −

L

Vds

In the linear region, the carrier density (p) can beexpressed as the oxide charge (Qin

Coulomb/cm2)divided by the inversion layer thickness (H) and the unitcharge (q):

p = �

�

Q = C(Vgs – Vth)

Then v = �.L

Vds

The average energy of hole is

E =�

�mpv

2 =

�

�mp

2

2

2

L

Vdsµ

So, the larger is Vds, larger will be the hole velocity and higher the hole energy. Generally, the energy

required to break the Si-H bond is around 0.3eV. So, energy higher than this enhances the NBTI and

this enhanced NBTI leads to more Si-H bond breakdowns. Fig. 1.4 shows the variation of average

hole energy with the S/D bias i.e. Vds.

Fig 1.4: Average Energy vs S/D bias

The main contribution to the Vth shift is the energetic hole which induces higher NBTI degradation

with higher S/D bias.

2. Reaction-Diffusion model

This analytical model captures the effect of stress and relaxation. These types of R-D model limited to

a single stress cycle and a single relaxation cycle.This analytical model includes stress and relaxation

phase as well as frequency independent property of NBTI.In this model interface traps are occurred at

the SiO2/Si interface and this reaction release the Hydrogen and this reaction also depend linearly on

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the stress time. In the next diffusion phase, hydrogen diffuses from the interface into oxide diffusion

with time dependence, tn where n = 0.25 for neutral hydrogen. This reaction occurs for a short time, so

we cannot observe it directly, but we can observe and verify the diffusion phase. The interface

generation equations are given below

∆Nit (t) = 2/3411

2

ABt

At

++

=

HRf

F

DtkNk

tNk

5.0/11

2

2/3

0

0

++

where kF and kR are the forward and backward reaction rates respectively, N0 is the initial defect

density, and DH, the hydrogen diffusion coefficient. During reaction phase i.e. for a small time

interval,

∆Nit (t) At = kFN0t

For diffusion phase

∆Nit (t) B

At1/4

=Rk

N

2

k 0F (DHt)1/4

The experimental data shows that the time exponent observed is less than 0.25. The generation of

interface traps is universally true, but the positive oxide charges generated during NBTI is not

confirmed yet.

The experimental plot of generation of interface traps verses stress time is given below.

Fig 2.1: ∆Nit vs Stress Time

Solution to the Reaction - Diffusion Model

According to the model, the rate of generation of interface traps initially depends on the rate of

dissociation of the Si - H bonds (controlled by the rate constant, ��) and the local self-annealing

process (which is governed by the rate constant, ��).

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Thus the reaction occurring in the R-D model can be quantified as

We now present the analytical solution of the R-D model assuming that alternate periods of stress and

relaxation, each of equal duration��, are applied to the gate of a PMOS device(shown in the figure),

whose source and bulk are tied to ��� while the drain is grounded.

Four different cases arise in this model, namely, the stress and relaxation phases, appearing alternately.

This analytical model is extended to the subsequent stress/relaxation phases. The final analytical

expression is given below. After the second recovery phase, we get

The analytical solution of the R-D model for the first two cycles is plotted. The black curve

corresponds to the case where the device is stressed continuously, while the blue curve corresponds to

the previous case, i.e., stress and relaxation applied alternately.

Fig 2.2: Analytical solution to the R-D model for the first two cycles and

Comparison with experimental data

3. Mechanism of interface traps and oxide charges Silicon is tetrahedrally bonded to four other silicon atoms. When Si is oxidized, some Si atoms are

bonded to oxygen and some are bonded to hydrogen. The bonding configuration on the surface is

shown in the figure given below for (111) and (100) orientations.

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Fig 3.1: Bonding configuration for Si

An interface trap is an interface trivalent Si atom with one unpaired electron at the SiO2/Si surface.

This interface trap is denoted as

Si3≡Si•

Interface traps are also known as Pb centres. From the above figure we observe that in (111)

orientation, Pb centre orbital is perpendicular to the interface. In (100) orientation, the four

tetrahedralSi–Si directions intersect the interface plane at the sameangle. Two types of interface

centres are found in this orientation,Pb1 and Pb0, by electron spin resonance (ESR).The identification

of Pb0 and Pb1 is not perfectly calculated. The two types of traps in (100) orientation are

producedbecause ofthe strain relief in the (100) silicon. The defects result from the naturally occurring

mismatch-induced stress at the SiO2/Si interface during oxide growth.Pb0centres result when strain

relaxation occurs with adefect residing at (111) microfacets at the Si/SiO2 interface, while Pb1centres

result when strain relaxation occurswith a defect at (100)Si/SiO2 transition regions. These interface

traps are electrically active with an energy distribution throughout the Si band gap. The generation

and recombination processes of these traps causes the leakage current, low-frequency noise, and

reduced mobility, drain current, and trans-conductance. Electron and holes occupy the interface traps

and they become charge and contribute to threshold voltage shift. The potential voltage at the surface

is dependent on the occupied traps. The band diagram in Fig 2.4 illustrates the dependency of surface

voltage on occupied traps:

Fig 3.2: Band Diagrams

From Fig 3.2(a)we observe that interface traps are acceptor-like in upper half band and donor like in

lower half band gap. From Fig 3.2 (a) we also observe that flat-band with electrons occupy states

below the Fermi energy and the states in the lower half of the band gap are neutral (occupied donors

designated by ‘‘0’’). Those between mid-gapand the Fermi energy are negatively charged

(occupiedacceptors designated by ‘‘-‘‘), and those above EF are neutral(unoccupied acceptors). We

observe from Fig 3.2 (b) that the interface traps between mid-gap and the Femi level are now

unoccupied donors, leading to positively charged interface traps (designatedby ‘‘+’’). Hence, interface

traps in p-channel devices ininversion are positively charged, leading to negative thresholdvoltage

shifts. Negative bias stress generates donorstates in the lower half of the band gap.

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The traps are positively charged when occupied by the holes and neutral when occupied by hydrogen.

Oxide charges located near the oxide/substrate interface lead to higher threshold shift than the charge

near the gate/oxide interface. We have already discussed the change of threshold voltage in the

section ‘S/D bias’. The change in the threshold voltage is determined by changing the channel

holedensity and measuring the change in threshold voltage.Thehole density can be changed by

changing Vth through fabrication or substrate bias. The p-MOSFET threshold voltage can be given as

Vth =ox

SF

ox

Fit

ox

oxMS

C

Q

C

Q

C

Q−−−− φ

φφ 2

)2(

where MSφ is the work function difference between the gate and substrate, Fφ the Fermi potential, Qox

the positive oxide charge density, QS the semiconductor charge density,and Cox the oxide

capacitance/unit area. Qit depends on the surface potential, according to the equation

Qit= qDit∆E = qNit

where∆E is the energy range over which interface traps areactive.

The threshold voltage change is given as:

∆Vth= ox

ox

itox

ox

itox tK

NNq

C

QQ

0

)(

ε

∆+∆−=

∆+∆−

= -4.6 oxitox tNN )(10 7 ∆+∆× −

We have already discussed the effect of stress time on the change in threshold voltage and change in

the interface trap density. From the experimental database the change in threshold voltage (∆Vth) and

change in the generation of interface traps density (∆Nit) verses stress time data are shown in the

graphs given below:

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Fig 3.3: (a) Relative ∆VT vs Stress Time

(b) Relative ∆Nit vs Stress Time

4. Frequency Independence An important requirement of any physical model for NBTIis that it should be able to explain the

phenomenon of frequencyindependence, observed over a wide range of frequencies. Frequency

independence implies that for any two periodicwaveforms with frequencies ��and��, and the same

duty cycle, thenumber of interface traps generated at any time t, such thatt>>�

��andt>>

�

��is the same.

Experiments have consistently shown that forfrequencies less than 10MHz, this is true.Mathematical

proof for square waveforms is as given below.

Fig 4.1: Two different square waveforms with different time periods ( ���and ���) but equal

duty cycles (50%)

Let the number of interface traps after time � for the two cases be denoted as �� (��� , ��,) and ��

(���,��,) respectively. By “frequency independence”, we imply

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We can prove this equation mathematically by using expressions for "#

Using the above equations, we have

5. Signal Probability and Activity Factor based Solution to the R-D

Model (SPAF Method)

While the NBTI impact has been analyzed fora square wave, such waveforms are rarely seen in digital

circuits,due to the random distribution of node probabilities. We describea methodology to estimate

the NBTI-induced �$%degradation of aPMOS device. This method, called the SPAF (Signal

Probability andActivity Factor) method, is based on signal probability (SP) andactivity factor (AF),

i.e., with respect toa reference clock.

Fig 5.1: (a) Signal probability dependency of trap generation shown for fourwaveforms of equal

frequency but varying duty cycles.

(b) Simulations for25% and 75% duty cycle waveforms showing the SPAF method

SPAF Method

The SPAF method helps to convert a random aperiodic signal to anequivalent deterministic waveform,

based on its statistical information(SP). Since the interface trap density is independent of theAF of a

signal, the crux of the SPAF method is to use the signal probabilities of any given node,

computed using logic simulators or otherwise. The SP information can now be used to compute

anequivalent rectangular periodic waveform with the same SP value. Such a transformation is

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equivalent to representing a 100Hz square waveform by a 1Hz square waveform, both of which have

the same SP.

Let the total time period of this new waveform be k cycles, such that it is low for m cycles and high

for k - m cycles. Let n indicate the number of such periods, each of duration k. We can determine the

number of interface traps generated. Using the "# notation, we have:

The SPAF method of equivalent waveform construction is verifiedfor two random waveforms of SP =

0.25 and SP = 0.75. The samplesare accumulated over 10000 cycles.

The two curves practicallycoincide, thereby validating the SPAF method of equivalent

waveformconstruction. The SPAF method can reduce a random aperiodicsignal to an equivalent

periodic rectangular waveform, and hence, candecrease the amount of computation, without loss of

accuracy.

6. Impact of NBTI on Circuit Delays

In this section, we present the simulation methodology to computethe delay degradation of ISCAS85

benchmarks, and the simulationresults. We pre-computethe statistical information (SP and AF) of the

various nodesin the digital circuit. The SPAF method is used to convert these probabilisticwaveforms

into deterministic periodic signals. We choose the equivalent waveform tobe of frequency 1Hz in

order to reduce the amount of computation.

We note here that for higher frequencies, thedependency of trap generation on the frequency is rather

weak.

The results are presented in Table above. The percentage increase in delays is plotted in thelast

column and an average degradation of 8.33%is seen for thesecombinational benchmarks.

Expectedly, the rise and fall arrival times show asimilar extent of increase in delay due to NBTI.

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References

[1] Negative bias temperature instability: What do we understand?

Dieter K. Schroder, Department of Electrical Engineering and Centre for Solid State Electronics

Research, Arizona State University, Tempe, AZ 85287-5706, USA

[2] Negative Bias Temperature Instability Basics/Modelling

Muhammad A. Alam Purdue University West Lafayette, IN

[3] An Analytical Model for Negative Bias Temperature Instability

Sanjay V. Kumar, Chris H. Kim, and Sachin S. Sapatnekar, Department of Electrical and Computer

Engineering, University of Minnesota, Minneapolis, MN 55455

[4] Negative Bias Temperature Instability of Deep Sub-Micronp-MOSFETs

Under Pulsed Bias Stress B. Zhu, J. S. Suehle, Y. Chen, and J. B. Bemstein

Centre for Reliability Engineering, University of Maryland, College Park, MD 20742

Semiconductor Electronics Division, National Institute of Standards and Technology,

Gaithersburg, MD 208993, Agere Systems, Orlando, FL 32837

[5] Investigation and Modelling of Interface and Bulk Trap Generation during Negative Bias

Temperature Instability of p-MOSFETs Souvik Mahapatra, P. Bharath Kumar, Student Member, IEEE, and M. A. Alam

[6] Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature

Polycrystalline Silicon Thin-Film Transistors

Chih-Yang Chen, Student Member, IEEE, Jam-Wem Lee, Wei-Cheng Chen, Hsiao-Yi Lin,

Kuan-Lin Yeh, Po-Hao Lee, Shen-De Wang, and Tan-Fu Lei

[7] Negative Bias Temperature Instability in Low-Temperature Polycrystalline

Silicon Thin-Film Transistors

[8] Models of Source/Drain Bias on Negative Bias Temperature Instability

Z. H. Gan, C. C. Liao, M. Liao, J. P.Wang, W.Wong, B.G. Yan, J. F. Kang, Y. Y. Wong,

Semiconductor Manufacturing International Corporation

[9] Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Yuichiro Mitani, Hideki Satake, and Akira Toriumi, Member, IEEE

[10] Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain

Bias in Nanoscale PMOS Devices Baoguang Yan, Student Member, IEEE, Jingfeng Yang, Zhiliang Xia, Xiaoyan Liu, Gang Du, Ruqi

Han, Jinfeng Kang, C. C. Liao, Zhenghao Gan, Miao Liao, J. P. Wang, and Waisum Wong

[11] A Rigorous Study of Measurement Techniques for Negative Bias Temperature Instability

Tibor Grasser, Senior Member, IEEE, Paul-Jürgen Wagner, Philipp Hehenberger, Wolfgang Goes,

and Ben Kaczer